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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * armboot - Startup Code for XScale
3 *
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
wdenka8c7c702003-12-06 19:49:23 +00007 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
wdenk1cb8e982003-03-06 21:55:29 +00008 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
Wolfgang Denk951a9542006-03-06 23:18:48 +01009 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
wdenkc6097192002-11-03 00:24:07 +000011 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk384ae022002-11-05 00:17:55 +000022 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc6097192002-11-03 00:24:07 +000023 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
wdenkc6097192002-11-03 00:24:07 +000031#include <config.h>
32#include <version.h>
Markus Klotzbüchere8cd0082006-02-28 23:11:07 +010033#include <asm/arch/pxa-regs.h>
wdenkc6097192002-11-03 00:24:07 +000034
35.globl _start
wdenk384ae022002-11-05 00:17:55 +000036_start: b reset
wdenkc6097192002-11-03 00:24:07 +000037 ldr pc, _undefined_instruction
38 ldr pc, _software_interrupt
39 ldr pc, _prefetch_abort
40 ldr pc, _data_abort
41 ldr pc, _not_used
42 ldr pc, _irq
43 ldr pc, _fiq
44
wdenk384ae022002-11-05 00:17:55 +000045_undefined_instruction: .word undefined_instruction
wdenkc6097192002-11-03 00:24:07 +000046_software_interrupt: .word software_interrupt
47_prefetch_abort: .word prefetch_abort
48_data_abort: .word data_abort
49_not_used: .word not_used
50_irq: .word irq
51_fiq: .word fiq
52
53 .balignl 16,0xdeadbeef
54
55
56/*
57 * Startup Code (reset vector)
58 *
wdenka8c7c702003-12-06 19:49:23 +000059 * do important init only if we don't start from RAM!
wdenkc6097192002-11-03 00:24:07 +000060 * - relocate armboot to ram
61 * - setup stack
62 * - jump to second stage
63 */
64
wdenkc6097192002-11-03 00:24:07 +000065_TEXT_BASE:
66 .word TEXT_BASE
67
68.globl _armboot_start
69_armboot_start:
70 .word _start
71
72/*
wdenkf6e20fc2004-02-08 19:38:38 +000073 * These are defined in the board-specific linker script.
wdenk47cd00f2003-03-06 13:39:27 +000074 */
wdenk8bde7f72003-06-27 21:31:46 +000075.globl _bss_start
76_bss_start:
wdenkf6e20fc2004-02-08 19:38:38 +000077 .word __bss_start
wdenk47cd00f2003-03-06 13:39:27 +000078
79.globl _bss_end
80_bss_end:
wdenkf6e20fc2004-02-08 19:38:38 +000081 .word _end
wdenk47cd00f2003-03-06 13:39:27 +000082
wdenkc6097192002-11-03 00:24:07 +000083#ifdef CONFIG_USE_IRQ
84/* IRQ stack memory (calculated at run-time) */
85.globl IRQ_STACK_START
86IRQ_STACK_START:
87 .word 0x0badc0de
88
89/* IRQ stack memory (calculated at run-time) */
90.globl FIQ_STACK_START
91FIQ_STACK_START:
92 .word 0x0badc0de
93#endif
94
95
96/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +000097/* */
98/* the actual reset code */
99/* */
wdenkc6097192002-11-03 00:24:07 +0000100/****************************************************************************/
101
102reset:
wdenk384ae022002-11-05 00:17:55 +0000103 mrs r0,cpsr /* set the cpu to SVC32 mode */
104 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
wdenkc6097192002-11-03 00:24:07 +0000105 orr r0,r0,#0x13
106 msr cpsr,r0
107
wdenka8c7c702003-12-06 19:49:23 +0000108 /*
109 * we do sys-critical inits only at reboot,
110 * not when booting from ram!
111 */
wdenk8aa1a2d2005-04-04 12:44:11 +0000112#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenk384ae022002-11-05 00:17:55 +0000113 bl cpu_init_crit /* we do sys-critical inits */
wdenka8c7c702003-12-06 19:49:23 +0000114#endif
wdenkc6097192002-11-03 00:24:07 +0000115
wdenk8aa1a2d2005-04-04 12:44:11 +0000116#ifndef CONFIG_SKIP_RELOCATE_UBOOT
wdenk1cb8e982003-03-06 21:55:29 +0000117relocate: /* relocate U-Boot to RAM */
118 adr r0, _start /* r0 <- current position of code */
wdenk8bde7f72003-06-27 21:31:46 +0000119 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100120 cmp r0, r1 /* don't reloc during debug */
121 beq stack_setup
wdenk1cb8e982003-03-06 21:55:29 +0000122
wdenkc6097192002-11-03 00:24:07 +0000123 ldr r2, _armboot_start
wdenkf6e20fc2004-02-08 19:38:38 +0000124 ldr r3, _bss_start
Wolfgang Denk951a9542006-03-06 23:18:48 +0100125 sub r2, r3, r2 /* r2 <- size of armboot */
126 add r2, r0, r2 /* r2 <- source end address */
wdenkc6097192002-11-03 00:24:07 +0000127
128copy_loop:
129 ldmia r0!, {r3-r10} /* copy from source address [r0] */
130 stmia r1!, {r3-r10} /* copy to target address [r1] */
131 cmp r0, r2 /* until source end addreee [r2] */
132 ble copy_loop
wdenk8aa1a2d2005-04-04 12:44:11 +0000133#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
wdenkc6097192002-11-03 00:24:07 +0000134
wdenk384ae022002-11-05 00:17:55 +0000135 /* Set up the stack */
wdenk1cb8e982003-03-06 21:55:29 +0000136stack_setup:
wdenka8c7c702003-12-06 19:49:23 +0000137 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100138 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
139 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
wdenka8c7c702003-12-06 19:49:23 +0000140#ifdef CONFIG_USE_IRQ
141 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
142#endif
wdenk47cd00f2003-03-06 13:39:27 +0000143 sub sp, r0, #12 /* leave 3 words for abort-stack */
144
145clear_bss:
Wolfgang Denk951a9542006-03-06 23:18:48 +0100146 ldr r0, _bss_start /* find start of bss segment */
147 ldr r1, _bss_end /* stop here */
148 mov r2, #0x00000000 /* clear */
wdenk47cd00f2003-03-06 13:39:27 +0000149
Wolfgang Denk951a9542006-03-06 23:18:48 +0100150clbss_l:str r2, [r0] /* clear loop... */
wdenk47cd00f2003-03-06 13:39:27 +0000151 add r0, r0, #4
152 cmp r0, r1
wdenka1191902005-01-09 17:12:27 +0000153 ble clbss_l
wdenk47cd00f2003-03-06 13:39:27 +0000154
wdenkc6097192002-11-03 00:24:07 +0000155 ldr pc, _start_armboot
156
wdenk384ae022002-11-05 00:17:55 +0000157_start_armboot: .word start_armboot
wdenkc6097192002-11-03 00:24:07 +0000158
159
160/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000161/* */
162/* CPU_init_critical registers */
163/* */
164/* - setup important registers */
165/* - setup memory timing */
166/* */
wdenkc6097192002-11-03 00:24:07 +0000167/****************************************************************************/
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100168/* mk@tbd: Fix this! */
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +0200169#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS)
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100170#undef ICMR
171#undef OSMR3
172#undef OSCR
173#undef OWER
174#undef OIER
175#endif
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +0200176#ifdef CONFIG_PXA250
177#undef RCSR
178#undef CCCR
179#endif
wdenkc6097192002-11-03 00:24:07 +0000180
Wolfgang Denk951a9542006-03-06 23:18:48 +0100181/* Interrupt-Controller base address */
wdenkc6097192002-11-03 00:24:07 +0000182IC_BASE: .word 0x40d00000
183#define ICMR 0x04
184
185/* Reset-Controller */
wdenk384ae022002-11-05 00:17:55 +0000186RST_BASE: .word 0x40f00030
wdenkc6097192002-11-03 00:24:07 +0000187#define RCSR 0x00
188
wdenk1cb8e982003-03-06 21:55:29 +0000189/* Operating System Timer */
wdenk384ae022002-11-05 00:17:55 +0000190OSTIMER_BASE: .word 0x40a00000
191#define OSMR3 0x0C
192#define OSCR 0x10
193#define OWER 0x18
194#define OIER 0x1C
wdenkc6097192002-11-03 00:24:07 +0000195
Wolfgang Denk951a9542006-03-06 23:18:48 +0100196/* Clock Manager Registers */
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100197#ifdef CONFIG_CPU_MONAHANS
198# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
199# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
200# endif
201# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
202# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
203# endif
204#else /* ! CONFIG_CPU_MONAHANS */
wdenka8c7c702003-12-06 19:49:23 +0000205#ifdef CFG_CPUSPEED
wdenk384ae022002-11-05 00:17:55 +0000206CC_BASE: .word 0x41300000
207#define CCCR 0x00
208cpuspeed: .word CFG_CPUSPEED
wdenka8c7c702003-12-06 19:49:23 +0000209#else
210#error "You have to define CFG_CPUSPEED!!"
211#endif
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100212#endif /* CONFIG_CPU_MONAHANS */
wdenk1cb8e982003-03-06 21:55:29 +0000213
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100214 /* takes care the CP15 update has taken place */
215 .macro CPWAIT reg
216 mrc p15,0,\reg,c2,c0,0
217 mov \reg,\reg
wdenkc6097192002-11-03 00:24:07 +0000218 sub pc,pc,#4
219 .endm
220
wdenkc6097192002-11-03 00:24:07 +0000221cpu_init_crit:
222
wdenk384ae022002-11-05 00:17:55 +0000223 /* mask all IRQs */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100224#ifndef CONFIG_CPU_MONAHANS
wdenkc6097192002-11-03 00:24:07 +0000225 ldr r0, IC_BASE
226 mov r1, #0x00
227 str r1, [r0, #ICMR]
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100228#else
229 /* Step 1 - Enable CP6 permission */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100230 mrc p15, 0, r1, c15, c1, 0 @ read CPAR
231 orr r1, r1, #0x40
232 mcr p15, 0, r1, c15, c1, 0
233 CPWAIT r1
wdenkc6097192002-11-03 00:24:07 +0000234
Wolfgang Denk951a9542006-03-06 23:18:48 +0100235 /* Step 2 - Mask ICMR & ICMR2 */
236 mov r1, #0
237 mcr p6, 0, r1, c1, c0, 0 @ ICMR
238 mcr p6, 0, r1, c7, c0, 0 @ ICMR2
Markus Klotzbüchere8cd0082006-02-28 23:11:07 +0100239
240 /* turn off all clocks but the ones we will definitly require */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100241 ldr r1, =CKENA
242 ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
243 str r2, [r1]
244 ldr r1, =CKENB
245 ldr r2, =(CKENB_6_IRQ)
246 str r2, [r1]
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100247#endif
wdenk1cb8e982003-03-06 21:55:29 +0000248
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100249 /* set clock speed */
250#ifdef CONFIG_CPU_MONAHANS
251 ldr r0, =ACCR
252 ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
253 str r1, [r0]
254#else /* ! CONFIG_CPU_MONAHANS */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100255#ifdef CFG_CPUSPEED
wdenkc6097192002-11-03 00:24:07 +0000256 ldr r0, CC_BASE
257 ldr r1, cpuspeed
258 str r1, [r0, #CCCR]
wdenk1cb8e982003-03-06 21:55:29 +0000259 mov r0, #2
wdenk7f6c2cb2002-11-10 22:06:23 +0000260 mcr p14, 0, r0, c6, c0, 0
wdenk1cb8e982003-03-06 21:55:29 +0000261
262setspeed_done:
Wolfgang Denk951a9542006-03-06 23:18:48 +0100263
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100264#endif /* CFG_CPUSPEED */
265#endif /* CONFIG_CPU_MONAHANS */
wdenkc6097192002-11-03 00:24:07 +0000266
267 /*
268 * before relocating, we have to setup RAM timing
269 * because memory timing is board-dependend, you will
wdenk400558b2005-04-02 23:52:25 +0000270 * find a lowlevel_init.S in your board directory.
wdenkc6097192002-11-03 00:24:07 +0000271 */
272 mov ip, lr
wdenk400558b2005-04-02 23:52:25 +0000273 bl lowlevel_init
wdenkc6097192002-11-03 00:24:07 +0000274 mov lr, ip
275
276 /* Memory interfaces are working. Disable MMU and enable I-cache. */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100277 /* mk: hmm, this is not in the monahans docs, leave it now but
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100278 * check here if it doesn't work :-) */
wdenkc6097192002-11-03 00:24:07 +0000279
wdenk384ae022002-11-05 00:17:55 +0000280 ldr r0, =0x2001 /* enable access to all coproc. */
wdenkc6097192002-11-03 00:24:07 +0000281 mcr p15, 0, r0, c15, c1, 0
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100282 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000283
284 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100285 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000286
wdenk384ae022002-11-05 00:17:55 +0000287 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100288 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000289
290 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100291 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000292
wdenk384ae022002-11-05 00:17:55 +0000293 /* Enable the Icache */
wdenkc6097192002-11-03 00:24:07 +0000294/*
295 mrc p15, 0, r0, c1, c0, 0
296 orr r0, r0, #0x1800
297 mcr p15, 0, r0, c1, c0, 0
wdenk699b13a2002-11-03 18:03:52 +0000298 CPWAIT
wdenkc6097192002-11-03 00:24:07 +0000299*/
300 mov pc, lr
301
302
303/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000304/* */
305/* Interrupt handling */
306/* */
wdenkc6097192002-11-03 00:24:07 +0000307/****************************************************************************/
308
wdenk384ae022002-11-05 00:17:55 +0000309/* IRQ stack frame */
wdenkc6097192002-11-03 00:24:07 +0000310
311#define S_FRAME_SIZE 72
312
313#define S_OLD_R0 68
314#define S_PSR 64
315#define S_PC 60
316#define S_LR 56
317#define S_SP 52
318
319#define S_IP 48
320#define S_FP 44
321#define S_R10 40
322#define S_R9 36
323#define S_R8 32
324#define S_R7 28
325#define S_R6 24
326#define S_R5 20
327#define S_R4 16
328#define S_R3 12
329#define S_R2 8
330#define S_R1 4
331#define S_R0 0
332
333#define MODE_SVC 0x13
334
wdenk384ae022002-11-05 00:17:55 +0000335 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
wdenkc6097192002-11-03 00:24:07 +0000336
337 .macro bad_save_user_regs
338 sub sp, sp, #S_FRAME_SIZE
wdenk384ae022002-11-05 00:17:55 +0000339 stmia sp, {r0 - r12} /* Calling r0-r12 */
340 add r8, sp, #S_PC
wdenkc6097192002-11-03 00:24:07 +0000341
wdenkf6e20fc2004-02-08 19:38:38 +0000342 ldr r2, _armboot_start
343 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
Wolfgang Denk951a9542006-03-06 23:18:48 +0100344 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
wdenk384ae022002-11-05 00:17:55 +0000345 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
346 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
wdenkc6097192002-11-03 00:24:07 +0000347
348 add r5, sp, #S_SP
349 mov r1, lr
wdenk384ae022002-11-05 00:17:55 +0000350 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
wdenkc6097192002-11-03 00:24:07 +0000351 mov r0, sp
352 .endm
353
354
wdenk384ae022002-11-05 00:17:55 +0000355 /* use irq_save_user_regs / irq_restore_user_regs for */
356 /* IRQ/FIQ handling */
wdenkc6097192002-11-03 00:24:07 +0000357
358 .macro irq_save_user_regs
359 sub sp, sp, #S_FRAME_SIZE
wdenk384ae022002-11-05 00:17:55 +0000360 stmia sp, {r0 - r12} /* Calling r0-r12 */
361 add r8, sp, #S_PC
362 stmdb r8, {sp, lr}^ /* Calling SP, LR */
363 str lr, [r8, #0] /* Save calling PC */
364 mrs r6, spsr
365 str r6, [r8, #4] /* Save CPSR */
366 str r0, [r8, #8] /* Save OLD_R0 */
wdenkc6097192002-11-03 00:24:07 +0000367 mov r0, sp
368 .endm
369
370 .macro irq_restore_user_regs
371 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
372 mov r0, r0
373 ldr lr, [sp, #S_PC] @ Get PC
374 add sp, sp, #S_FRAME_SIZE
375 subs pc, lr, #4 @ return & move spsr_svc into cpsr
376 .endm
377
378 .macro get_bad_stack
wdenkf6e20fc2004-02-08 19:38:38 +0000379 ldr r13, _armboot_start @ setup our mode stack
380 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
381 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
wdenkc6097192002-11-03 00:24:07 +0000382
383 str lr, [r13] @ save caller lr / spsr
384 mrs lr, spsr
wdenk384ae022002-11-05 00:17:55 +0000385 str lr, [r13, #4]
wdenkc6097192002-11-03 00:24:07 +0000386
387 mov r13, #MODE_SVC @ prepare SVC-Mode
388 msr spsr_c, r13
389 mov lr, pc
390 movs pc, lr
391 .endm
392
393 .macro get_irq_stack @ setup IRQ stack
394 ldr sp, IRQ_STACK_START
395 .endm
396
397 .macro get_fiq_stack @ setup FIQ stack
398 ldr sp, FIQ_STACK_START
399 .endm
400
401
402/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000403/* */
404/* exception handlers */
405/* */
wdenkc6097192002-11-03 00:24:07 +0000406/****************************************************************************/
407
wdenk384ae022002-11-05 00:17:55 +0000408 .align 5
wdenkc6097192002-11-03 00:24:07 +0000409undefined_instruction:
410 get_bad_stack
411 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000412 bl do_undefined_instruction
wdenkc6097192002-11-03 00:24:07 +0000413
414 .align 5
415software_interrupt:
416 get_bad_stack
417 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000418 bl do_software_interrupt
wdenkc6097192002-11-03 00:24:07 +0000419
420 .align 5
421prefetch_abort:
422 get_bad_stack
423 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000424 bl do_prefetch_abort
wdenkc6097192002-11-03 00:24:07 +0000425
426 .align 5
427data_abort:
428 get_bad_stack
429 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000430 bl do_data_abort
wdenkc6097192002-11-03 00:24:07 +0000431
432 .align 5
433not_used:
434 get_bad_stack
435 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000436 bl do_not_used
wdenkc6097192002-11-03 00:24:07 +0000437
438#ifdef CONFIG_USE_IRQ
439
440 .align 5
441irq:
442 get_irq_stack
443 irq_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000444 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000445 irq_restore_user_regs
446
447 .align 5
448fiq:
449 get_fiq_stack
450 irq_save_user_regs /* someone ought to write a more */
wdenk384ae022002-11-05 00:17:55 +0000451 bl do_fiq /* effiction fiq_save_user_regs */
wdenkc6097192002-11-03 00:24:07 +0000452 irq_restore_user_regs
453
454#else
455
456 .align 5
457irq:
458 get_bad_stack
459 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000460 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000461
462 .align 5
463fiq:
464 get_bad_stack
465 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000466 bl do_fiq
wdenkc6097192002-11-03 00:24:07 +0000467
468#endif
469
wdenk1cb8e982003-03-06 21:55:29 +0000470/****************************************************************************/
Wolfgang Denk951a9542006-03-06 23:18:48 +0100471/* */
wdenk1cb8e982003-03-06 21:55:29 +0000472/* Reset function: the PXA250 doesn't have a reset function, so we have to */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100473/* perform a watchdog timeout for a soft reset. */
474/* */
wdenk1cb8e982003-03-06 21:55:29 +0000475/****************************************************************************/
476
wdenkc6097192002-11-03 00:24:07 +0000477 .align 5
478.globl reset_cpu
wdenk1cb8e982003-03-06 21:55:29 +0000479
Wolfgang Denk951a9542006-03-06 23:18:48 +0100480 /* FIXME: this code is PXA250 specific. How is this handled on */
481 /* other XScale processors? */
wdenk1cb8e982003-03-06 21:55:29 +0000482
wdenkc6097192002-11-03 00:24:07 +0000483reset_cpu:
wdenk1cb8e982003-03-06 21:55:29 +0000484
wdenk384ae022002-11-05 00:17:55 +0000485 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
wdenkc6097192002-11-03 00:24:07 +0000486
wdenk384ae022002-11-05 00:17:55 +0000487 ldr r0, OSTIMER_BASE
488 ldr r1, [r0, #OWER]
Wolfgang Denk951a9542006-03-06 23:18:48 +0100489 orr r1, r1, #0x0001 /* bit0: WME */
wdenk384ae022002-11-05 00:17:55 +0000490 str r1, [r0, #OWER]
491
492 /* OS timer does only wrap every 1165 seconds, so we have to set */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100493 /* the match register as well. */
wdenk384ae022002-11-05 00:17:55 +0000494
Wolfgang Denk951a9542006-03-06 23:18:48 +0100495 ldr r1, [r0, #OSCR] /* read OS timer */
wdenk384ae022002-11-05 00:17:55 +0000496 add r1, r1, #0x800 /* let OSMR3 match after */
497 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
498 str r1, [r0, #OSMR3]
499
500reset_endless:
501
502 b reset_endless