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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ce6d99a056ebc9ad329521ca3660f6cb298a7666 / . / arch / sandbox / dts / test.dts
blob: 9ced5beee8930299249051187494c46462288594 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassce6d99a2018-12-10 10:37:33 -0700[diff] [blame^]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
50 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]79 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]80 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]81 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]82 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]83 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]84 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]85 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
86 <0>, <&gpio_a 12>;
87 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
88 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
89 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]90 };
91
92 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]93 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]94 compatible = "not,compatible";
95 };
96
97 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]98 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]99 };
100
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]101 backlight: backlight {
102 compatible = "pwm-backlight";
103 enable-gpios = <&gpio_a 1>;
104 power-supply = <&ldo_1>;
105 pwms = <&pwm 0 1000>;
106 default-brightness-level = <5>;
107 brightness-levels = <0 16 32 64 128 170 202 234 255>;
108 };
109
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]110 bind-test {
111 bind-test-child1 {
112 compatible = "sandbox,phy";
113 #phy-cells = <1>;
114 };
115
116 bind-test-child2 {
117 compatible = "simple-bus";
118 };
119 };
120
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]121 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]122 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]123 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]124 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]125 ping-add = <3>;
126 };
127
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]128 phy_provider0: gen_phy@0 {
129 compatible = "sandbox,phy";
130 #phy-cells = <1>;
131 };
132
133 phy_provider1: gen_phy@1 {
134 compatible = "sandbox,phy";
135 #phy-cells = <0>;
136 broken;
137 };
138
139 gen_phy_user: gen_phy_user {
140 compatible = "simple-bus";
141 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
142 phy-names = "phy1", "phy2", "phy3";
143 };
144
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]145 some-bus {
146 #address-cells = <1>;
147 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]148 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]149 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]150 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]151 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]152 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]153 compatible = "denx,u-boot-fdt-test";
154 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]155 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]156 ping-add = <5>;
157 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]158 c-test@0 {
159 compatible = "denx,u-boot-fdt-test";
160 reg = <0>;
161 ping-expect = <6>;
162 ping-add = <6>;
163 };
164 c-test@1 {
165 compatible = "denx,u-boot-fdt-test";
166 reg = <1>;
167 ping-expect = <7>;
168 ping-add = <7>;
169 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]170 };
171
172 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]173 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]174 ping-expect = <6>;
175 ping-add = <6>;
176 compatible = "google,another-fdt-test";
177 };
178
179 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]180 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]181 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]182 ping-add = <6>;
183 compatible = "google,another-fdt-test";
184 };
185
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]186 f-test {
187 compatible = "denx,u-boot-fdt-test";
188 };
189
190 g-test {
191 compatible = "denx,u-boot-fdt-test";
192 };
193
Bin Meng2786cd72018-10-10 22:07:01 -0700[diff] [blame]194 h-test {
195 compatible = "denx,u-boot-fdt-test1";
196 };
197
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]198 clocks {
199 clk_fixed: clk-fixed {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <1234>;
203 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]204 };
205
206 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]207 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]208 #clock-cells = <1>;
209 };
210
211 clk-test {
212 compatible = "sandbox,clk-test";
213 clocks = <&clk_fixed>,
214 <&clk_sandbox 1>,
215 <&clk_sandbox 0>;
216 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]217 };
218
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]219 eth@10002000 {
220 compatible = "sandbox,eth";
221 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]222 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]223 };
224
225 eth_5: eth@10003000 {
226 compatible = "sandbox,eth";
227 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]228 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]229 };
230
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]231 eth_3: sbe5 {
232 compatible = "sandbox,eth";
233 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]234 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]235 };
236
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]237 eth@10004000 {
238 compatible = "sandbox,eth";
239 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]240 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]241 };
242
Rajan Vaja31b82172018-09-19 03:43:46 -0700[diff] [blame]243 firmware {
244 sandbox_firmware: sandbox-firmware {
245 compatible = "sandbox,firmware";
246 };
247 };
248
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]249 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]250 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]251 gpio-controller;
252 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]253 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]254 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]255 };
256
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]257 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]258 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]259 gpio-controller;
260 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]261 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]262 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]263 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]264
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]265 i2c@0 {
266 #address-cells = <1>;
267 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]268 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]269 compatible = "sandbox,i2c";
270 clock-frequency = <100000>;
271 eeprom@2c {
272 reg = <0x2c>;
273 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]274 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]275 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]276
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]277 rtc_0: rtc@43 {
278 reg = <0x43>;
279 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]280 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]281 };
282
283 rtc_1: rtc@61 {
284 reg = <0x61>;
285 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]286 sandbox,emul = <&emul1>;
287 };
288
289 i2c_emul: emul {
290 reg = <0xff>;
291 compatible = "sandbox,i2c-emul-parent";
292 emul_eeprom: emul-eeprom {
293 compatible = "sandbox,i2c-eeprom";
294 sandbox,filename = "i2c.bin";
295 sandbox,size = <256>;
296 };
297 emul0: emul0 {
298 compatible = "sandbox,i2c-rtc";
299 };
300 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]301 compatible = "sandbox,i2c-rtc";
302 };
303 };
304
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]305 sandbox_pmic: sandbox_pmic {
306 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]307 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]308 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]309
310 mc34708: pmic@41 {
311 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]312 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]313 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]314 };
315
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]316 adc@0 {
317 compatible = "sandbox,adc";
318 vdd-supply = <&buck2>;
319 vss-microvolts = <0>;
320 };
321
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]322 lcd {
323 u-boot,dm-pre-reloc;
324 compatible = "sandbox,lcd-sdl";
325 xres = <1366>;
326 yres = <768>;
327 };
328
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]329 leds {
330 compatible = "gpio-leds";
331
332 iracibble {
333 gpios = <&gpio_a 1 0>;
334 label = "sandbox:red";
335 };
336
337 martinet {
338 gpios = <&gpio_a 2 0>;
339 label = "sandbox:green";
340 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]341
342 default_on {
343 gpios = <&gpio_a 5 0>;
344 label = "sandbox:default_on";
345 default-state = "on";
346 };
347
348 default_off {
349 gpios = <&gpio_a 6 0>;
350 label = "sandbox:default_off";
351 default-state = "off";
352 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]353 };
354
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]355 mbox: mbox {
356 compatible = "sandbox,mbox";
357 #mbox-cells = <1>;
358 };
359
360 mbox-test {
361 compatible = "sandbox,mbox-test";
362 mboxes = <&mbox 100>, <&mbox 1>;
363 mbox-names = "other", "test";
364 };
365
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]366 cpu-test1 {
367 compatible = "sandbox,cpu_sandbox";
Bin Meng25d0fe72018-10-14 01:07:20 -0700[diff] [blame]368 u-boot,dm-pre-reloc;
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]369 };
370
371 cpu-test2 {
372 compatible = "sandbox,cpu_sandbox";
Bin Meng25d0fe72018-10-14 01:07:20 -0700[diff] [blame]373 u-boot,dm-pre-reloc;
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]374 };
375
376 cpu-test3 {
377 compatible = "sandbox,cpu_sandbox";
Bin Meng25d0fe72018-10-14 01:07:20 -0700[diff] [blame]378 u-boot,dm-pre-reloc;
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]379 };
380
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]381 misc-test {
382 compatible = "sandbox,misc_sandbox";
383 };
384
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]385 mmc2 {
386 compatible = "sandbox,mmc";
387 };
388
389 mmc1 {
390 compatible = "sandbox,mmc";
391 };
392
393 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]394 compatible = "sandbox,mmc";
395 };
396
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]397 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]398 compatible = "sandbox,pci";
399 device_type = "pci";
400 #address-cells = <3>;
401 #size-cells = <2>;
402 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
403 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]404 pci@0,0 {
405 compatible = "pci-generic";
406 reg = <0x0000 0 0 0 0>;
407 emul@0,0 {
408 compatible = "sandbox,swap-case";
409 };
410 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]411 pci@1f,0 {
412 compatible = "pci-generic";
413 reg = <0xf800 0 0 0 0>;
414 emul@1f,0 {
415 compatible = "sandbox,swap-case";
416 };
417 };
418 };
419
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]420 pci1: pci-controller1 {
421 compatible = "sandbox,pci";
422 device_type = "pci";
423 #address-cells = <3>;
424 #size-cells = <2>;
425 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
426 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]427 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200[diff] [blame]428 0x0c 0x00 0x1234 0x5678
429 0x10 0x00 0x1234 0x5678>;
430 pci@10,0 {
431 reg = <0x8000 0 0 0 0>;
432 };
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]433 };
434
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]435 pci2: pci-controller2 {
436 compatible = "sandbox,pci";
437 device_type = "pci";
438 #address-cells = <3>;
439 #size-cells = <2>;
440 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
441 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
442 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
443 pci@1f,0 {
444 compatible = "pci-generic";
445 reg = <0xf800 0 0 0 0>;
446 emul@1f,0 {
447 compatible = "sandbox,swap-case";
448 };
449 };
450 };
451
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]452 probing {
453 compatible = "simple-bus";
454 test1 {
455 compatible = "denx,u-boot-probe-test";
456 };
457
458 test2 {
459 compatible = "denx,u-boot-probe-test";
460 };
461
462 test3 {
463 compatible = "denx,u-boot-probe-test";
464 };
465
466 test4 {
467 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]468 first-syscon = <&syscon0>;
469 second-sys-ctrl = <&another_system_controller>;
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]470 };
471 };
472
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]473 pwrdom: power-domain {
474 compatible = "sandbox,power-domain";
475 #power-domain-cells = <1>;
476 };
477
478 power-domain-test {
479 compatible = "sandbox,power-domain-test";
480 power-domains = <&pwrdom 2>;
481 };
482
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]483 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]484 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]485 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]486 };
487
488 pwm2 {
489 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]490 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]491 };
492
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]493 ram {
494 compatible = "sandbox,ram";
495 };
496
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]497 reset@0 {
498 compatible = "sandbox,warm-reset";
499 };
500
501 reset@1 {
502 compatible = "sandbox,reset";
503 };
504
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]505 resetc: reset-ctl {
506 compatible = "sandbox,reset-ctl";
507 #reset-cells = <1>;
508 };
509
510 reset-ctl-test {
511 compatible = "sandbox,reset-ctl-test";
512 resets = <&resetc 100>, <&resetc 2>;
513 reset-names = "other", "test";
514 };
515
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]516 rproc_1: rproc@1 {
517 compatible = "sandbox,test-processor";
518 remoteproc-name = "remoteproc-test-dev1";
519 };
520
521 rproc_2: rproc@2 {
522 compatible = "sandbox,test-processor";
523 internal-memory-mapped;
524 remoteproc-name = "remoteproc-test-dev2";
525 };
526
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]527 panel {
528 compatible = "simple-panel";
529 backlight = <&backlight 0 100>;
530 };
531
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]532 smem@0 {
533 compatible = "sandbox,smem";
534 };
535
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]536 spi@0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]539 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]540 compatible = "sandbox,spi";
541 cs-gpios = <0>, <&gpio_a 0>;
542 spi.bin@0 {
543 reg = <0>;
544 compatible = "spansion,m25p16", "spi-flash";
545 spi-max-frequency = <40000000>;
546 sandbox,filename = "spi.bin";
547 };
548 };
549
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]550 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]551 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200[diff] [blame]552 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]553 };
554
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]555 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]556 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]557 reg = <0x20 5
558 0x28 6
559 0x30 7
560 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]561 };
562
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]563 syscon@2 {
564 compatible = "simple-mfd", "syscon";
565 reg = <0x40 5
566 0x48 6
567 0x50 7
568 0x58 8>;
569 };
570
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]571 timer {
572 compatible = "sandbox,timer";
573 clock-frequency = <1000000>;
574 };
575
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]576 tpm2 {
577 compatible = "sandbox,tpm2";
578 };
579
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]580 uart0: serial {
581 compatible = "sandbox,serial";
582 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]583 };
584
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]585 usb_0: usb@0 {
586 compatible = "sandbox,usb";
587 status = "disabled";
588 hub {
589 compatible = "sandbox,usb-hub";
590 #address-cells = <1>;
591 #size-cells = <0>;
592 flash-stick {
593 reg = <0>;
594 compatible = "sandbox,usb-flash";
595 };
596 };
597 };
598
599 usb_1: usb@1 {
600 compatible = "sandbox,usb";
601 hub {
602 compatible = "usb-hub";
603 usb,device-class = <9>;
604 hub-emul {
605 compatible = "sandbox,usb-hub";
606 #address-cells = <1>;
607 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]608 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]609 reg = <0>;
610 compatible = "sandbox,usb-flash";
611 sandbox,filepath = "testflash.bin";
612 };
613
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]614 flash-stick@1 {
615 reg = <1>;
616 compatible = "sandbox,usb-flash";
617 sandbox,filepath = "testflash1.bin";
618 };
619
620 flash-stick@2 {
621 reg = <2>;
622 compatible = "sandbox,usb-flash";
623 sandbox,filepath = "testflash2.bin";
624 };
625
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]626 keyb@3 {
627 reg = <3>;
628 compatible = "sandbox,usb-keyb";
629 };
630
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]631 };
632 };
633 };
634
635 usb_2: usb@2 {
636 compatible = "sandbox,usb";
637 status = "disabled";
638 };
639
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]640 spmi: spmi@0 {
641 compatible = "sandbox,spmi";
642 #address-cells = <0x1>;
643 #size-cells = <0x1>;
644 pm8916@0 {
645 compatible = "qcom,spmi-pmic";
646 reg = <0x0 0x1>;
647 #address-cells = <0x1>;
648 #size-cells = <0x1>;
649
650 spmi_gpios: gpios@c000 {
651 compatible = "qcom,pm8916-gpio";
652 reg = <0xc000 0x400>;
653 gpio-controller;
654 gpio-count = <4>;
655 #gpio-cells = <2>;
656 gpio-bank-name="spmi";
657 };
658 };
659 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]660
661 wdt0: wdt@0 {
662 compatible = "sandbox,wdt";
663 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]664
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]665 axi: axi@0 {
666 compatible = "sandbox,axi";
667 #address-cells = <0x1>;
668 #size-cells = <0x1>;
669 store@0 {
670 compatible = "sandbox,sandbox_store";
671 reg = <0x0 0x400>;
672 };
673 };
674
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]675 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]676 #address-cells = <1>;
677 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]678 chosen-test {
679 compatible = "denx,u-boot-fdt-test";
680 reg = <9 1>;
681 };
682 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]683
684 translation-test@8000 {
685 compatible = "simple-bus";
686 reg = <0x8000 0x4000>;
687
688 #address-cells = <0x2>;
689 #size-cells = <0x1>;
690
691 ranges = <0 0x0 0x8000 0x1000
692 1 0x100 0x9000 0x1000
693 2 0x200 0xA000 0x1000
694 3 0x300 0xB000 0x1000
695 >;
696
697 dev@0,0 {
698 compatible = "denx,u-boot-fdt-dummy";
699 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100[diff] [blame]700 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]701 };
702
703 dev@1,100 {
704 compatible = "denx,u-boot-fdt-dummy";
705 reg = <1 0x100 0x1000>;
706
707 };
708
709 dev@2,200 {
710 compatible = "denx,u-boot-fdt-dummy";
711 reg = <2 0x200 0x1000>;
712 };
713
714
715 noxlatebus@3,300 {
716 compatible = "simple-bus";
717 reg = <3 0x300 0x1000>;
718
719 #address-cells = <0x1>;
720 #size-cells = <0x0>;
721
722 dev@42 {
723 compatible = "denx,u-boot-fdt-dummy";
724 reg = <0x42>;
725 };
726 };
727 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]728
729 osd {
730 compatible = "sandbox,sandbox_osd";
731 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400[diff] [blame]732
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]733 board {
734 compatible = "sandbox,board_sandbox";
735 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200[diff] [blame]736
737 sandbox_tee {
738 compatible = "sandbox,tee";
739 };
Bin Meng4f89d492018-10-15 02:21:26 -0700[diff] [blame]740
741 sandbox_virtio1 {
742 compatible = "sandbox,virtio1";
743 };
744
745 sandbox_virtio2 {
746 compatible = "sandbox,virtio2";
747 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200[diff] [blame]748
749 pinctrl {
750 compatible = "sandbox,pinctrl";
751 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +0100[diff] [blame]752
753 hwspinlock@0 {
754 compatible = "sandbox,hwspinlock";
755 };
Grygorii Strashkob3309912018-11-28 19:17:51 +0100[diff] [blame]756
757 dma: dma {
758 compatible = "sandbox,dma";
759 #dma-cells = <1>;
760
761 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
762 dma-names = "m2m", "tx0", "rx0";
763 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]764};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]765
766#include "sandbox_pmic.dtsi"