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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e8d5291824e27575fe71222f683579325221e0cb / . / arch / sandbox / dts / test.dts
blob: 06d0e8ce8506ae28add3fe8064c52b3583a409b9 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]17 pci0 = &pci;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]18 remoteproc1 = &rproc_1;
19 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]20 rtc0 = &rtc_0;
21 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]22 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]23 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]24 testbus3 = "/some-bus";
25 testfdt0 = "/some-bus/c-test@0";
26 testfdt1 = "/some-bus/c-test@1";
27 testfdt3 = "/b-test";
28 testfdt5 = "/some-bus/c-test@5";
29 testfdt8 = "/a-test";
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame^]30 fdt_dummy0 = "/translation-test@8000/dev@0,0";
31 fdt_dummy1 = "/translation-test@8000/dev@1,100";
32 fdt_dummy2 = "/translation-test@8000/dev@2,200";
33 fdt_dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]34 usb0 = &usb_0;
35 usb1 = &usb_1;
36 usb2 = &usb_2;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]37 };
38
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]39 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]40 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]41 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]42 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]43 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]44 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]45 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
46 <0>, <&gpio_a 12>;
47 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
48 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
49 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]50 };
51
52 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]53 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]54 compatible = "not,compatible";
55 };
56
57 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]58 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]59 };
60
61 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]62 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]63 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]64 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]65 ping-add = <3>;
66 };
67
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]68 phy_provider0: gen_phy@0 {
69 compatible = "sandbox,phy";
70 #phy-cells = <1>;
71 };
72
73 phy_provider1: gen_phy@1 {
74 compatible = "sandbox,phy";
75 #phy-cells = <0>;
76 broken;
77 };
78
79 gen_phy_user: gen_phy_user {
80 compatible = "simple-bus";
81 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
82 phy-names = "phy1", "phy2", "phy3";
83 };
84
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]85 some-bus {
86 #address-cells = <1>;
87 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]88 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]89 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]90 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]91 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]92 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]93 compatible = "denx,u-boot-fdt-test";
94 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]95 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]96 ping-add = <5>;
97 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]98 c-test@0 {
99 compatible = "denx,u-boot-fdt-test";
100 reg = <0>;
101 ping-expect = <6>;
102 ping-add = <6>;
103 };
104 c-test@1 {
105 compatible = "denx,u-boot-fdt-test";
106 reg = <1>;
107 ping-expect = <7>;
108 ping-add = <7>;
109 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]110 };
111
112 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]113 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]114 ping-expect = <6>;
115 ping-add = <6>;
116 compatible = "google,another-fdt-test";
117 };
118
119 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]120 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]121 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]122 ping-add = <6>;
123 compatible = "google,another-fdt-test";
124 };
125
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]126 f-test {
127 compatible = "denx,u-boot-fdt-test";
128 };
129
130 g-test {
131 compatible = "denx,u-boot-fdt-test";
132 };
133
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]134 clocks {
135 clk_fixed: clk-fixed {
136 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 clock-frequency = <1234>;
139 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]140 };
141
142 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]143 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]144 #clock-cells = <1>;
145 };
146
147 clk-test {
148 compatible = "sandbox,clk-test";
149 clocks = <&clk_fixed>,
150 <&clk_sandbox 1>,
151 <&clk_sandbox 0>;
152 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]153 };
154
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]155 eth@10002000 {
156 compatible = "sandbox,eth";
157 reg = <0x10002000 0x1000>;
158 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
159 };
160
161 eth_5: eth@10003000 {
162 compatible = "sandbox,eth";
163 reg = <0x10003000 0x1000>;
164 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
165 };
166
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]167 eth_3: sbe5 {
168 compatible = "sandbox,eth";
169 reg = <0x10005000 0x1000>;
170 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>;
171 };
172
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]173 eth@10004000 {
174 compatible = "sandbox,eth";
175 reg = <0x10004000 0x1000>;
176 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
177 };
178
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]179 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]180 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]181 gpio-controller;
182 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]183 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]184 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]185 };
186
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]187 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]188 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]189 gpio-controller;
190 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]191 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]192 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]193 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]194
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]195 i2c@0 {
196 #address-cells = <1>;
197 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]198 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]199 compatible = "sandbox,i2c";
200 clock-frequency = <100000>;
201 eeprom@2c {
202 reg = <0x2c>;
203 compatible = "i2c-eeprom";
204 emul {
205 compatible = "sandbox,i2c-eeprom";
206 sandbox,filename = "i2c.bin";
207 sandbox,size = <256>;
208 };
209 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]210
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]211 rtc_0: rtc@43 {
212 reg = <0x43>;
213 compatible = "sandbox-rtc";
214 emul {
215 compatible = "sandbox,i2c-rtc";
216 };
217 };
218
219 rtc_1: rtc@61 {
220 reg = <0x61>;
221 compatible = "sandbox-rtc";
222 emul {
223 compatible = "sandbox,i2c-rtc";
224 };
225 };
226
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]227 sandbox_pmic: sandbox_pmic {
228 reg = <0x40>;
229 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]230 };
231
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]232 adc@0 {
233 compatible = "sandbox,adc";
234 vdd-supply = <&buck2>;
235 vss-microvolts = <0>;
236 };
237
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]238 lcd {
239 u-boot,dm-pre-reloc;
240 compatible = "sandbox,lcd-sdl";
241 xres = <1366>;
242 yres = <768>;
243 };
244
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]245 leds {
246 compatible = "gpio-leds";
247
248 iracibble {
249 gpios = <&gpio_a 1 0>;
250 label = "sandbox:red";
251 };
252
253 martinet {
254 gpios = <&gpio_a 2 0>;
255 label = "sandbox:green";
256 };
257 };
258
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]259 mbox: mbox {
260 compatible = "sandbox,mbox";
261 #mbox-cells = <1>;
262 };
263
264 mbox-test {
265 compatible = "sandbox,mbox-test";
266 mboxes = <&mbox 100>, <&mbox 1>;
267 mbox-names = "other", "test";
268 };
269
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]270 mmc2 {
271 compatible = "sandbox,mmc";
272 };
273
274 mmc1 {
275 compatible = "sandbox,mmc";
276 };
277
278 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]279 compatible = "sandbox,mmc";
280 };
281
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]282 pci: pci-controller {
283 compatible = "sandbox,pci";
284 device_type = "pci";
285 #address-cells = <3>;
286 #size-cells = <2>;
287 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
288 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
289 pci@1f,0 {
290 compatible = "pci-generic";
291 reg = <0xf800 0 0 0 0>;
292 emul@1f,0 {
293 compatible = "sandbox,swap-case";
294 };
295 };
296 };
297
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]298 probing {
299 compatible = "simple-bus";
300 test1 {
301 compatible = "denx,u-boot-probe-test";
302 };
303
304 test2 {
305 compatible = "denx,u-boot-probe-test";
306 };
307
308 test3 {
309 compatible = "denx,u-boot-probe-test";
310 };
311
312 test4 {
313 compatible = "denx,u-boot-probe-test";
314 };
315 };
316
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]317 pwrdom: power-domain {
318 compatible = "sandbox,power-domain";
319 #power-domain-cells = <1>;
320 };
321
322 power-domain-test {
323 compatible = "sandbox,power-domain-test";
324 power-domains = <&pwrdom 2>;
325 };
326
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]327 pwm {
328 compatible = "sandbox,pwm";
329 };
330
331 pwm2 {
332 compatible = "sandbox,pwm";
333 };
334
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]335 ram {
336 compatible = "sandbox,ram";
337 };
338
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]339 reset@0 {
340 compatible = "sandbox,warm-reset";
341 };
342
343 reset@1 {
344 compatible = "sandbox,reset";
345 };
346
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]347 resetc: reset-ctl {
348 compatible = "sandbox,reset-ctl";
349 #reset-cells = <1>;
350 };
351
352 reset-ctl-test {
353 compatible = "sandbox,reset-ctl-test";
354 resets = <&resetc 100>, <&resetc 2>;
355 reset-names = "other", "test";
356 };
357
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]358 rproc_1: rproc@1 {
359 compatible = "sandbox,test-processor";
360 remoteproc-name = "remoteproc-test-dev1";
361 };
362
363 rproc_2: rproc@2 {
364 compatible = "sandbox,test-processor";
365 internal-memory-mapped;
366 remoteproc-name = "remoteproc-test-dev2";
367 };
368
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]369 spi@0 {
370 #address-cells = <1>;
371 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]372 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]373 compatible = "sandbox,spi";
374 cs-gpios = <0>, <&gpio_a 0>;
375 spi.bin@0 {
376 reg = <0>;
377 compatible = "spansion,m25p16", "spi-flash";
378 spi-max-frequency = <40000000>;
379 sandbox,filename = "spi.bin";
380 };
381 };
382
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]383 syscon@0 {
384 compatible = "sandbox,syscon0";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]385 reg = <0x10 4>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]386 };
387
388 syscon@1 {
389 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]390 reg = <0x20 5
391 0x28 6
392 0x30 7
393 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]394 };
395
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]396 timer {
397 compatible = "sandbox,timer";
398 clock-frequency = <1000000>;
399 };
400
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]401 uart0: serial {
402 compatible = "sandbox,serial";
403 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]404 };
405
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]406 usb_0: usb@0 {
407 compatible = "sandbox,usb";
408 status = "disabled";
409 hub {
410 compatible = "sandbox,usb-hub";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 flash-stick {
414 reg = <0>;
415 compatible = "sandbox,usb-flash";
416 };
417 };
418 };
419
420 usb_1: usb@1 {
421 compatible = "sandbox,usb";
422 hub {
423 compatible = "usb-hub";
424 usb,device-class = <9>;
425 hub-emul {
426 compatible = "sandbox,usb-hub";
427 #address-cells = <1>;
428 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]429 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]430 reg = <0>;
431 compatible = "sandbox,usb-flash";
432 sandbox,filepath = "testflash.bin";
433 };
434
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]435 flash-stick@1 {
436 reg = <1>;
437 compatible = "sandbox,usb-flash";
438 sandbox,filepath = "testflash1.bin";
439 };
440
441 flash-stick@2 {
442 reg = <2>;
443 compatible = "sandbox,usb-flash";
444 sandbox,filepath = "testflash2.bin";
445 };
446
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]447 keyb@3 {
448 reg = <3>;
449 compatible = "sandbox,usb-keyb";
450 };
451
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]452 };
453 };
454 };
455
456 usb_2: usb@2 {
457 compatible = "sandbox,usb";
458 status = "disabled";
459 };
460
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]461 spmi: spmi@0 {
462 compatible = "sandbox,spmi";
463 #address-cells = <0x1>;
464 #size-cells = <0x1>;
465 pm8916@0 {
466 compatible = "qcom,spmi-pmic";
467 reg = <0x0 0x1>;
468 #address-cells = <0x1>;
469 #size-cells = <0x1>;
470
471 spmi_gpios: gpios@c000 {
472 compatible = "qcom,pm8916-gpio";
473 reg = <0xc000 0x400>;
474 gpio-controller;
475 gpio-count = <4>;
476 #gpio-cells = <2>;
477 gpio-bank-name="spmi";
478 };
479 };
480 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]481
482 wdt0: wdt@0 {
483 compatible = "sandbox,wdt";
484 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]485
486 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]487 #address-cells = <1>;
488 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]489 chosen-test {
490 compatible = "denx,u-boot-fdt-test";
491 reg = <9 1>;
492 };
493 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame^]494
495 translation-test@8000 {
496 compatible = "simple-bus";
497 reg = <0x8000 0x4000>;
498
499 #address-cells = <0x2>;
500 #size-cells = <0x1>;
501
502 ranges = <0 0x0 0x8000 0x1000
503 1 0x100 0x9000 0x1000
504 2 0x200 0xA000 0x1000
505 3 0x300 0xB000 0x1000
506 >;
507
508 dev@0,0 {
509 compatible = "denx,u-boot-fdt-dummy";
510 reg = <0 0x0 0x1000>;
511 };
512
513 dev@1,100 {
514 compatible = "denx,u-boot-fdt-dummy";
515 reg = <1 0x100 0x1000>;
516
517 };
518
519 dev@2,200 {
520 compatible = "denx,u-boot-fdt-dummy";
521 reg = <2 0x200 0x1000>;
522 };
523
524
525 noxlatebus@3,300 {
526 compatible = "simple-bus";
527 reg = <3 0x300 0x1000>;
528
529 #address-cells = <0x1>;
530 #size-cells = <0x0>;
531
532 dev@42 {
533 compatible = "denx,u-boot-fdt-dummy";
534 reg = <0x42>;
535 };
536 };
537 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]538};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]539
540#include "sandbox_pmic.dtsi"