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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / dee4d752be4cbad2216f9285470588004c5d154e / . / arch / sandbox / dts / test.dts
blob: 0bce6d01af7564aa51c7910ead74d79b6f8512e5 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame^]17 pci0 = &pci0;
18 pci1 = &pci1;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]19 remoteproc1 = &rproc_1;
20 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]21 rtc0 = &rtc_0;
22 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]23 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]24 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]25 testbus3 = "/some-bus";
26 testfdt0 = "/some-bus/c-test@0";
27 testfdt1 = "/some-bus/c-test@1";
28 testfdt3 = "/b-test";
29 testfdt5 = "/some-bus/c-test@5";
30 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]31 fdt-dummy0 = "/translation-test@8000/dev@0,0";
32 fdt-dummy1 = "/translation-test@8000/dev@1,100";
33 fdt-dummy2 = "/translation-test@8000/dev@2,200";
34 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]35 usb0 = &usb_0;
36 usb1 = &usb_1;
37 usb2 = &usb_2;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]38 };
39
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]40 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]41 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]42 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]43 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]44 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]45 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]46 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
47 <0>, <&gpio_a 12>;
48 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
49 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
50 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]51 };
52
53 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]54 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]55 compatible = "not,compatible";
56 };
57
58 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]59 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]60 };
61
62 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]63 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]64 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]65 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]66 ping-add = <3>;
67 };
68
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]69 phy_provider0: gen_phy@0 {
70 compatible = "sandbox,phy";
71 #phy-cells = <1>;
72 };
73
74 phy_provider1: gen_phy@1 {
75 compatible = "sandbox,phy";
76 #phy-cells = <0>;
77 broken;
78 };
79
80 gen_phy_user: gen_phy_user {
81 compatible = "simple-bus";
82 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
83 phy-names = "phy1", "phy2", "phy3";
84 };
85
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]86 some-bus {
87 #address-cells = <1>;
88 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]89 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]90 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]91 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]92 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]93 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]94 compatible = "denx,u-boot-fdt-test";
95 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]96 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]97 ping-add = <5>;
98 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]99 c-test@0 {
100 compatible = "denx,u-boot-fdt-test";
101 reg = <0>;
102 ping-expect = <6>;
103 ping-add = <6>;
104 };
105 c-test@1 {
106 compatible = "denx,u-boot-fdt-test";
107 reg = <1>;
108 ping-expect = <7>;
109 ping-add = <7>;
110 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]111 };
112
113 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]114 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]115 ping-expect = <6>;
116 ping-add = <6>;
117 compatible = "google,another-fdt-test";
118 };
119
120 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]121 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]122 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]123 ping-add = <6>;
124 compatible = "google,another-fdt-test";
125 };
126
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]127 f-test {
128 compatible = "denx,u-boot-fdt-test";
129 };
130
131 g-test {
132 compatible = "denx,u-boot-fdt-test";
133 };
134
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]135 clocks {
136 clk_fixed: clk-fixed {
137 compatible = "fixed-clock";
138 #clock-cells = <0>;
139 clock-frequency = <1234>;
140 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]141 };
142
143 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]144 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]145 #clock-cells = <1>;
146 };
147
148 clk-test {
149 compatible = "sandbox,clk-test";
150 clocks = <&clk_fixed>,
151 <&clk_sandbox 1>,
152 <&clk_sandbox 0>;
153 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]154 };
155
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]156 eth@10002000 {
157 compatible = "sandbox,eth";
158 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]159 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]160 };
161
162 eth_5: eth@10003000 {
163 compatible = "sandbox,eth";
164 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]165 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]166 };
167
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]168 eth_3: sbe5 {
169 compatible = "sandbox,eth";
170 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]171 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]172 };
173
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]174 eth@10004000 {
175 compatible = "sandbox,eth";
176 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]177 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]178 };
179
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]180 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]181 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]182 gpio-controller;
183 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]184 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]185 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]186 };
187
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]188 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]189 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]190 gpio-controller;
191 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]192 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]193 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]194 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]195
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]196 i2c@0 {
197 #address-cells = <1>;
198 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]199 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]200 compatible = "sandbox,i2c";
201 clock-frequency = <100000>;
202 eeprom@2c {
203 reg = <0x2c>;
204 compatible = "i2c-eeprom";
205 emul {
206 compatible = "sandbox,i2c-eeprom";
207 sandbox,filename = "i2c.bin";
208 sandbox,size = <256>;
209 };
210 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]211
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]212 rtc_0: rtc@43 {
213 reg = <0x43>;
214 compatible = "sandbox-rtc";
215 emul {
216 compatible = "sandbox,i2c-rtc";
217 };
218 };
219
220 rtc_1: rtc@61 {
221 reg = <0x61>;
222 compatible = "sandbox-rtc";
223 emul {
224 compatible = "sandbox,i2c-rtc";
225 };
226 };
227
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]228 sandbox_pmic: sandbox_pmic {
229 reg = <0x40>;
230 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]231
232 mc34708: pmic@41 {
233 reg = <0x41>;
234 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]235 };
236
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]237 adc@0 {
238 compatible = "sandbox,adc";
239 vdd-supply = <&buck2>;
240 vss-microvolts = <0>;
241 };
242
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]243 lcd {
244 u-boot,dm-pre-reloc;
245 compatible = "sandbox,lcd-sdl";
246 xres = <1366>;
247 yres = <768>;
248 };
249
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]250 leds {
251 compatible = "gpio-leds";
252
253 iracibble {
254 gpios = <&gpio_a 1 0>;
255 label = "sandbox:red";
256 };
257
258 martinet {
259 gpios = <&gpio_a 2 0>;
260 label = "sandbox:green";
261 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]262
263 default_on {
264 gpios = <&gpio_a 5 0>;
265 label = "sandbox:default_on";
266 default-state = "on";
267 };
268
269 default_off {
270 gpios = <&gpio_a 6 0>;
271 label = "sandbox:default_off";
272 default-state = "off";
273 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]274 };
275
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]276 mbox: mbox {
277 compatible = "sandbox,mbox";
278 #mbox-cells = <1>;
279 };
280
281 mbox-test {
282 compatible = "sandbox,mbox-test";
283 mboxes = <&mbox 100>, <&mbox 1>;
284 mbox-names = "other", "test";
285 };
286
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]287 mmc2 {
288 compatible = "sandbox,mmc";
289 };
290
291 mmc1 {
292 compatible = "sandbox,mmc";
293 };
294
295 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]296 compatible = "sandbox,mmc";
297 };
298
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame^]299 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]300 compatible = "sandbox,pci";
301 device_type = "pci";
302 #address-cells = <3>;
303 #size-cells = <2>;
304 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
305 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]306 pci@0,0 {
307 compatible = "pci-generic";
308 reg = <0x0000 0 0 0 0>;
309 emul@0,0 {
310 compatible = "sandbox,swap-case";
311 };
312 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]313 pci@1f,0 {
314 compatible = "pci-generic";
315 reg = <0xf800 0 0 0 0>;
316 emul@1f,0 {
317 compatible = "sandbox,swap-case";
318 };
319 };
320 };
321
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame^]322 pci1: pci-controller1 {
323 compatible = "sandbox,pci";
324 device_type = "pci";
325 #address-cells = <3>;
326 #size-cells = <2>;
327 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
328 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
329 pci@8,0 {
330 compatible = "pci-generic";
331 reg = <0x4000 0 0 0 0>;
332 emul@8,0 {
333 compatible = "sandbox,swap-case";
334 };
335 };
336 pci@c,0 {
337 compatible = "pci-generic";
338 reg = <0x6000 0 0 0 0>;
339 emul@c,0 {
340 compatible = "sandbox,swap-case";
341 };
342 };
343 };
344
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]345 probing {
346 compatible = "simple-bus";
347 test1 {
348 compatible = "denx,u-boot-probe-test";
349 };
350
351 test2 {
352 compatible = "denx,u-boot-probe-test";
353 };
354
355 test3 {
356 compatible = "denx,u-boot-probe-test";
357 };
358
359 test4 {
360 compatible = "denx,u-boot-probe-test";
361 };
362 };
363
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]364 pwrdom: power-domain {
365 compatible = "sandbox,power-domain";
366 #power-domain-cells = <1>;
367 };
368
369 power-domain-test {
370 compatible = "sandbox,power-domain-test";
371 power-domains = <&pwrdom 2>;
372 };
373
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]374 pwm {
375 compatible = "sandbox,pwm";
376 };
377
378 pwm2 {
379 compatible = "sandbox,pwm";
380 };
381
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]382 ram {
383 compatible = "sandbox,ram";
384 };
385
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]386 reset@0 {
387 compatible = "sandbox,warm-reset";
388 };
389
390 reset@1 {
391 compatible = "sandbox,reset";
392 };
393
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]394 resetc: reset-ctl {
395 compatible = "sandbox,reset-ctl";
396 #reset-cells = <1>;
397 };
398
399 reset-ctl-test {
400 compatible = "sandbox,reset-ctl-test";
401 resets = <&resetc 100>, <&resetc 2>;
402 reset-names = "other", "test";
403 };
404
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]405 rproc_1: rproc@1 {
406 compatible = "sandbox,test-processor";
407 remoteproc-name = "remoteproc-test-dev1";
408 };
409
410 rproc_2: rproc@2 {
411 compatible = "sandbox,test-processor";
412 internal-memory-mapped;
413 remoteproc-name = "remoteproc-test-dev2";
414 };
415
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]416 smem@0 {
417 compatible = "sandbox,smem";
418 };
419
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]420 spi@0 {
421 #address-cells = <1>;
422 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]423 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]424 compatible = "sandbox,spi";
425 cs-gpios = <0>, <&gpio_a 0>;
426 spi.bin@0 {
427 reg = <0>;
428 compatible = "spansion,m25p16", "spi-flash";
429 spi-max-frequency = <40000000>;
430 sandbox,filename = "spi.bin";
431 };
432 };
433
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]434 syscon@0 {
435 compatible = "sandbox,syscon0";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]436 reg = <0x10 4>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]437 };
438
439 syscon@1 {
440 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]441 reg = <0x20 5
442 0x28 6
443 0x30 7
444 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]445 };
446
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]447 syscon@2 {
448 compatible = "simple-mfd", "syscon";
449 reg = <0x40 5
450 0x48 6
451 0x50 7
452 0x58 8>;
453 };
454
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]455 timer {
456 compatible = "sandbox,timer";
457 clock-frequency = <1000000>;
458 };
459
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]460 tpm2 {
461 compatible = "sandbox,tpm2";
462 };
463
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]464 uart0: serial {
465 compatible = "sandbox,serial";
466 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]467 };
468
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]469 usb_0: usb@0 {
470 compatible = "sandbox,usb";
471 status = "disabled";
472 hub {
473 compatible = "sandbox,usb-hub";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 flash-stick {
477 reg = <0>;
478 compatible = "sandbox,usb-flash";
479 };
480 };
481 };
482
483 usb_1: usb@1 {
484 compatible = "sandbox,usb";
485 hub {
486 compatible = "usb-hub";
487 usb,device-class = <9>;
488 hub-emul {
489 compatible = "sandbox,usb-hub";
490 #address-cells = <1>;
491 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]492 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]493 reg = <0>;
494 compatible = "sandbox,usb-flash";
495 sandbox,filepath = "testflash.bin";
496 };
497
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]498 flash-stick@1 {
499 reg = <1>;
500 compatible = "sandbox,usb-flash";
501 sandbox,filepath = "testflash1.bin";
502 };
503
504 flash-stick@2 {
505 reg = <2>;
506 compatible = "sandbox,usb-flash";
507 sandbox,filepath = "testflash2.bin";
508 };
509
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]510 keyb@3 {
511 reg = <3>;
512 compatible = "sandbox,usb-keyb";
513 };
514
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]515 };
516 };
517 };
518
519 usb_2: usb@2 {
520 compatible = "sandbox,usb";
521 status = "disabled";
522 };
523
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]524 spmi: spmi@0 {
525 compatible = "sandbox,spmi";
526 #address-cells = <0x1>;
527 #size-cells = <0x1>;
528 pm8916@0 {
529 compatible = "qcom,spmi-pmic";
530 reg = <0x0 0x1>;
531 #address-cells = <0x1>;
532 #size-cells = <0x1>;
533
534 spmi_gpios: gpios@c000 {
535 compatible = "qcom,pm8916-gpio";
536 reg = <0xc000 0x400>;
537 gpio-controller;
538 gpio-count = <4>;
539 #gpio-cells = <2>;
540 gpio-bank-name="spmi";
541 };
542 };
543 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]544
545 wdt0: wdt@0 {
546 compatible = "sandbox,wdt";
547 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]548
549 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]550 #address-cells = <1>;
551 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]552 chosen-test {
553 compatible = "denx,u-boot-fdt-test";
554 reg = <9 1>;
555 };
556 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]557
558 translation-test@8000 {
559 compatible = "simple-bus";
560 reg = <0x8000 0x4000>;
561
562 #address-cells = <0x2>;
563 #size-cells = <0x1>;
564
565 ranges = <0 0x0 0x8000 0x1000
566 1 0x100 0x9000 0x1000
567 2 0x200 0xA000 0x1000
568 3 0x300 0xB000 0x1000
569 >;
570
571 dev@0,0 {
572 compatible = "denx,u-boot-fdt-dummy";
573 reg = <0 0x0 0x1000>;
574 };
575
576 dev@1,100 {
577 compatible = "denx,u-boot-fdt-dummy";
578 reg = <1 0x100 0x1000>;
579
580 };
581
582 dev@2,200 {
583 compatible = "denx,u-boot-fdt-dummy";
584 reg = <2 0x200 0x1000>;
585 };
586
587
588 noxlatebus@3,300 {
589 compatible = "simple-bus";
590 reg = <3 0x300 0x1000>;
591
592 #address-cells = <0x1>;
593 #size-cells = <0x0>;
594
595 dev@42 {
596 compatible = "denx,u-boot-fdt-dummy";
597 reg = <0x42>;
598 };
599 };
600 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]601};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]602
603#include "sandbox_pmic.dtsi"