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Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goede44d8ae52015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbell2c7e3b92014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergera26cd042015-05-12 14:46:23 -050021 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010022
Ian Campbellc3be2792014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbellc3be2792014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbellc3be2792014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080038 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020040 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020041 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080042 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010043
Ian Campbellc3be2792014-10-24 21:20:45 +010044config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010045 bool "sun7i (Allwinner A20)"
46 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020049 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010050 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020051 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010052
Hans de Goede5e6bacd2015-04-06 20:55:39 +020053config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010054 bool "sun8i (Allwinner A23)"
55 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080056 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020058 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010059 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080060 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010061
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053062config MACH_SUN8I_A33
63 bool "sun8i (Allwinner A33)"
64 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053067 select SUNXI_GEN_SUN6I
68 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080069 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053070
Jens Kuske1c27b7d2015-11-17 15:12:58 +010071config MACH_SUN8I_H3
72 bool "sun8i (Allwinner H3)"
73 select CPU_V7
74 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +010075 select SUPPORT_SPL
Jens Kuske1c27b7d2015-11-17 15:12:58 +010076
Hans de Goede1871a8c2015-01-13 19:25:06 +010077config MACH_SUN9I
78 bool "sun9i (Allwinner A80)"
79 select CPU_V7
80 select SUNXI_GEN_SUN6I
81
Ian Campbell2c7e3b92014-10-24 21:20:44 +010082endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +080083
Hans de Goede5e6bacd2015-04-06 20:55:39 +020084# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
85config MACH_SUN8I
86 bool
Jens Kuske1c27b7d2015-11-17 15:12:58 +010087 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3
Hans de Goede5e6bacd2015-04-06 20:55:39 +020088
89
Hans de Goede37781a12014-11-15 19:46:39 +010090config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +010091 int "sunxi dram clock speed"
92 default 312 if MACH_SUN6I || MACH_SUN8I
93 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010094 ---help---
95 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +010096 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +010097
Siarhei Siamashka47e35012015-02-01 00:27:06 +020098if MACH_SUN5I || MACH_SUN7I
99config DRAM_MBUS_CLK
100 int "sunxi mbus clock speed"
101 default 300
102 ---help---
103 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
104
105endif
106
Hans de Goede37781a12014-11-15 19:46:39 +0100107config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100108 int "sunxi dram zq value"
109 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
110 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100111 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100112 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100113
Hans de Goede8975cdf2015-05-13 15:00:46 +0200114config DRAM_ODT_EN
115 bool "sunxi dram odt enable"
116 default n if !MACH_SUN8I_A23
117 default y if MACH_SUN8I_A23
118 ---help---
119 Select this to enable dram odt (on die termination).
120
Hans de Goede8ffc4872015-01-17 14:24:55 +0100121if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
122config DRAM_EMR1
123 int "sunxi dram emr1 value"
124 default 0 if MACH_SUN4I
125 default 4 if MACH_SUN5I || MACH_SUN7I
126 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100127 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200128
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200129config DRAM_TPR3
130 hex "sunxi dram tpr3 value"
131 default 0
132 ---help---
133 Set the dram controller tpr3 parameter. This parameter configures
134 the delay on the command lane and also phase shifts, which are
135 applied for sampling incoming read data. The default value 0
136 means that no phase/delay adjustments are necessary. Properly
137 configuring this parameter increases reliability at high DRAM
138 clock speeds.
139
140config DRAM_DQS_GATING_DELAY
141 hex "sunxi dram dqs_gating_delay value"
142 default 0
143 ---help---
144 Set the dram controller dqs_gating_delay parmeter. Each byte
145 encodes the DQS gating delay for each byte lane. The delay
146 granularity is 1/4 cycle. For example, the value 0x05060606
147 means that the delay is 5 quarter-cycles for one lane (1.25
148 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
149 The default value 0 means autodetection. The results of hardware
150 autodetection are not very reliable and depend on the chip
151 temperature (sometimes producing different results on cold start
152 and warm reboot). But the accuracy of hardware autodetection
153 is usually good enough, unless running at really high DRAM
154 clocks speeds (up to 600MHz). If unsure, keep as 0.
155
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200156choice
157 prompt "sunxi dram timings"
158 default DRAM_TIMINGS_VENDOR_MAGIC
159 ---help---
160 Select the timings of the DDR3 chips.
161
162config DRAM_TIMINGS_VENDOR_MAGIC
163 bool "Magic vendor timings from Android"
164 ---help---
165 The same DRAM timings as in the Allwinner boot0 bootloader.
166
167config DRAM_TIMINGS_DDR3_1066F_1333H
168 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
169 ---help---
170 Use the timings of the standard JEDEC DDR3-1066F speed bin for
171 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
172 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
173 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
174 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
175 that down binning to DDR3-1066F is supported (because DDR3-1066F
176 uses a bit faster timings than DDR3-1333H).
177
178config DRAM_TIMINGS_DDR3_800E_1066G_1333J
179 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
180 ---help---
181 Use the timings of the slowest possible JEDEC speed bin for the
182 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
183 DDR3-800E, DDR3-1066G or DDR3-1333J.
184
185endchoice
186
Hans de Goede37781a12014-11-15 19:46:39 +0100187endif
188
Hans de Goede8975cdf2015-05-13 15:00:46 +0200189if MACH_SUN8I_A23
190config DRAM_ODT_CORRECTION
191 int "sunxi dram odt correction value"
192 default 0
193 ---help---
194 Set the dram odt correction value (range -255 - 255). In allwinner
195 fex files, this option is found in bits 8-15 of the u32 odt_en variable
196 in the [dram] section. When bit 31 of the odt_en variable is set
197 then the correction is negative. Usually the value for this is 0.
198endif
199
Iain Patone71b4222015-03-28 10:26:38 +0000200config SYS_CLK_FREQ
201 default 912000000 if MACH_SUN7I
202 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
203
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800204config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100205 default "sun4i" if MACH_SUN4I
206 default "sun5i" if MACH_SUN5I
207 default "sun6i" if MACH_SUN6I
208 default "sun7i" if MACH_SUN7I
209 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100210 default "sun9i" if MACH_SUN9I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200211
Masahiro Yamadadd840582014-07-30 14:08:14 +0900212config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900213 default "sunxi"
214
215config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900216 default "sunxi"
217
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200218config UART0_PORT_F
219 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200220 default n
221 ---help---
222 Repurpose the SD card slot for getting access to the UART0 serial
223 console. Primarily useful only for low level u-boot debugging on
224 tablets, where normal UART0 is difficult to access and requires
225 device disassembly and/or soldering. As the SD card can't be used
226 at the same time, the system can be only booted in the FEL mode.
227 Only enable this if you really know what you are doing.
228
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200229config OLD_SUNXI_KERNEL_COMPAT
230 boolean "Enable workarounds for booting old kernels"
231 default n
232 ---help---
233 Set this to enable various workarounds for old kernels, this results in
234 sub-optimal settings for newer kernels, only enable if needed.
235
Maxime Ripard44c79872015-10-15 22:04:07 +0200236config MMC
237 depends on !UART0_PORT_F
238 default y if ARCH_SUNXI
239
Hans de Goedecd821132014-10-02 20:29:26 +0200240config MMC0_CD_PIN
241 string "Card detect pin for mmc0"
242 default ""
243 ---help---
244 Set the card detect pin for mmc0, leave empty to not use cd. This
245 takes a string in the format understood by sunxi_name_to_gpio, e.g.
246 PH1 for pin 1 of port H.
247
248config MMC1_CD_PIN
249 string "Card detect pin for mmc1"
250 default ""
251 ---help---
252 See MMC0_CD_PIN help text.
253
254config MMC2_CD_PIN
255 string "Card detect pin for mmc2"
256 default ""
257 ---help---
258 See MMC0_CD_PIN help text.
259
260config MMC3_CD_PIN
261 string "Card detect pin for mmc3"
262 default ""
263 ---help---
264 See MMC0_CD_PIN help text.
265
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100266config MMC1_PINS
267 string "Pins for mmc1"
268 default ""
269 ---help---
270 Set the pins used for mmc1, when applicable. This takes a string in the
271 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
272
273config MMC2_PINS
274 string "Pins for mmc2"
275 default ""
276 ---help---
277 See MMC1_PINS help text.
278
279config MMC3_PINS
280 string "Pins for mmc3"
281 default ""
282 ---help---
283 See MMC1_PINS help text.
284
Hans de Goede2ccfac02014-10-02 20:43:50 +0200285config MMC_SUNXI_SLOT_EXTRA
286 int "mmc extra slot number"
287 default -1
288 ---help---
289 sunxi builds always enable mmc0, some boards also have a second sdcard
290 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
291 support for this.
292
Hans de Goede4458b7a2015-01-07 15:26:06 +0100293config USB0_VBUS_PIN
294 string "Vbus enable pin for usb0 (otg)"
295 default ""
296 ---help---
297 Set the Vbus enable pin for usb0 (otg). This takes a string in the
298 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
299
Hans de Goede52defe82015-02-16 22:13:43 +0100300config USB0_VBUS_DET
301 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100302 default ""
303 ---help---
304 Set the Vbus detect pin for usb0 (otg). This takes a string in the
305 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
306
Hans de Goede48c06c92015-06-14 17:29:53 +0200307config USB0_ID_DET
308 string "ID detect pin for usb0 (otg)"
309 default ""
310 ---help---
311 Set the ID detect pin for usb0 (otg). This takes a string in the
312 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
313
Hans de Goede115200c2014-11-07 16:09:00 +0100314config USB1_VBUS_PIN
315 string "Vbus enable pin for usb1 (ehci0)"
316 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100317 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100318 ---help---
319 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
320 a string in the format understood by sunxi_name_to_gpio, e.g.
321 PH1 for pin 1 of port H.
322
323config USB2_VBUS_PIN
324 string "Vbus enable pin for usb2 (ehci1)"
325 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100326 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100327 ---help---
328 See USB1_VBUS_PIN help text.
329
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200330config I2C0_ENABLE
331 bool "Enable I2C/TWI controller 0"
332 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
333 default n if MACH_SUN6I || MACH_SUN8I
334 ---help---
335 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
336 its clock and setting up the bus. This is especially useful on devices
337 with slaves connected to the bus or with pins exposed through e.g. an
338 expansion port/header.
339
340config I2C1_ENABLE
341 bool "Enable I2C/TWI controller 1"
342 default n
343 ---help---
344 See I2C0_ENABLE help text.
345
346config I2C2_ENABLE
347 bool "Enable I2C/TWI controller 2"
348 default n
349 ---help---
350 See I2C0_ENABLE help text.
351
352if MACH_SUN6I || MACH_SUN7I
353config I2C3_ENABLE
354 bool "Enable I2C/TWI controller 3"
355 default n
356 ---help---
357 See I2C0_ENABLE help text.
358endif
359
360if MACH_SUN7I
361config I2C4_ENABLE
362 bool "Enable I2C/TWI controller 4"
363 default n
364 ---help---
365 See I2C0_ENABLE help text.
366endif
367
Hans de Goede2fcf0332015-04-25 17:25:14 +0200368config AXP_GPIO
369 boolean "Enable support for gpio-s on axp PMICs"
370 default n
371 ---help---
372 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
373
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200374config VIDEO
Hans de Goede2dae8002014-12-21 16:28:32 +0100375 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200376 default y
377 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100378 Say Y here to add support for using a cfb console on the HDMI, LCD
379 or VGA output found on most sunxi devices. See doc/README.video for
380 info on how to select the video output and mode.
381
Hans de Goede2fbf0912014-12-23 23:04:35 +0100382config VIDEO_HDMI
383 boolean "HDMI output support"
384 depends on VIDEO && !MACH_SUN8I
385 default y
386 ---help---
387 Say Y here to add support for outputting video over HDMI.
388
Hans de Goeded9786d22014-12-25 13:58:06 +0100389config VIDEO_VGA
390 boolean "VGA output support"
391 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
392 default n
393 ---help---
394 Say Y here to add support for outputting video over VGA.
395
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100396config VIDEO_VGA_VIA_LCD
397 boolean "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800398 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100399 default n
400 ---help---
401 Say Y here to add support for external DACs connected to the parallel
402 LCD interface driving a VGA connector, such as found on the
403 Olimex A13 boards.
404
Hans de Goedefb75d972015-01-25 15:33:07 +0100405config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
406 boolean "Force sync active high for VGA via LCD controller support"
407 depends on VIDEO_VGA_VIA_LCD
408 default n
409 ---help---
410 Say Y here if you've a board which uses opendrain drivers for the vga
411 hsync and vsync signals. Opendrain drivers cannot generate steep enough
412 positive edges for a stable video output, so on boards with opendrain
413 drivers the sync signals must always be active high.
414
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800415config VIDEO_VGA_EXTERNAL_DAC_EN
416 string "LCD panel power enable pin"
417 depends on VIDEO_VGA_VIA_LCD
418 default ""
419 ---help---
420 Set the enable pin for the external VGA DAC. This takes a string in the
421 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
422
Hans de Goede39920c82015-08-03 19:20:26 +0200423config VIDEO_COMPOSITE
424 boolean "Composite video output support"
425 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
426 default n
427 ---help---
428 Say Y here to add support for outputting composite video.
429
Hans de Goede2dae8002014-12-21 16:28:32 +0100430config VIDEO_LCD_MODE
431 string "LCD panel timing details"
432 depends on VIDEO
433 default ""
434 ---help---
435 LCD panel timing details string, leave empty if there is no LCD panel.
436 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
437 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200438 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100439
Hans de Goede65150322015-01-13 13:21:46 +0100440config VIDEO_LCD_DCLK_PHASE
441 int "LCD panel display clock phase"
442 depends on VIDEO
443 default 1
444 ---help---
445 Select LCD panel display clock phase shift, range 0-3.
446
Hans de Goede2dae8002014-12-21 16:28:32 +0100447config VIDEO_LCD_POWER
448 string "LCD panel power enable pin"
449 depends on VIDEO
450 default ""
451 ---help---
452 Set the power enable pin for the LCD panel. This takes a string in the
453 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
454
Hans de Goede242e3d82015-02-16 17:26:41 +0100455config VIDEO_LCD_RESET
456 string "LCD panel reset pin"
457 depends on VIDEO
458 default ""
459 ---help---
460 Set the reset pin for the LCD panel. This takes a string in the format
461 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
462
Hans de Goede2dae8002014-12-21 16:28:32 +0100463config VIDEO_LCD_BL_EN
464 string "LCD panel backlight enable pin"
465 depends on VIDEO
466 default ""
467 ---help---
468 Set the backlight enable pin for the LCD panel. This takes a string in the
469 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
470 port H.
471
472config VIDEO_LCD_BL_PWM
473 string "LCD panel backlight pwm pin"
474 depends on VIDEO
475 default ""
476 ---help---
477 Set the backlight pwm pin for the LCD panel. This takes a string in the
478 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200479
Hans de Goedea7403ae2015-01-22 21:02:42 +0100480config VIDEO_LCD_BL_PWM_ACTIVE_LOW
481 bool "LCD panel backlight pwm is inverted"
482 depends on VIDEO
483 default y
484 ---help---
485 Set this if the backlight pwm output is active low.
486
Hans de Goede55410082015-02-16 17:23:25 +0100487config VIDEO_LCD_PANEL_I2C
488 bool "LCD panel needs to be configured via i2c"
489 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100490 default n
Hans de Goede55410082015-02-16 17:23:25 +0100491 ---help---
492 Say y here if the LCD panel needs to be configured via i2c. This
493 will add a bitbang i2c controller using gpios to talk to the LCD.
494
495config VIDEO_LCD_PANEL_I2C_SDA
496 string "LCD panel i2c interface SDA pin"
497 depends on VIDEO_LCD_PANEL_I2C
498 default "PG12"
499 ---help---
500 Set the SDA pin for the LCD i2c interface. This takes a string in the
501 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
502
503config VIDEO_LCD_PANEL_I2C_SCL
504 string "LCD panel i2c interface SCL pin"
505 depends on VIDEO_LCD_PANEL_I2C
506 default "PG10"
507 ---help---
508 Set the SCL pin for the LCD i2c interface. This takes a string in the
509 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
510
Hans de Goede213480e2015-01-01 22:04:34 +0100511
512# Note only one of these may be selected at a time! But hidden choices are
513# not supported by Kconfig
514config VIDEO_LCD_IF_PARALLEL
515 bool
516
517config VIDEO_LCD_IF_LVDS
518 bool
519
520
521choice
522 prompt "LCD panel support"
523 depends on VIDEO
524 ---help---
525 Select which type of LCD panel to support.
526
527config VIDEO_LCD_PANEL_PARALLEL
528 bool "Generic parallel interface LCD panel"
529 select VIDEO_LCD_IF_PARALLEL
530
531config VIDEO_LCD_PANEL_LVDS
532 bool "Generic lvds interface LCD panel"
533 select VIDEO_LCD_IF_LVDS
534
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200535config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
536 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
537 select VIDEO_LCD_SSD2828
538 select VIDEO_LCD_IF_PARALLEL
539 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200540 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
541
542config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
543 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
544 select VIDEO_LCD_ANX9804
545 select VIDEO_LCD_IF_PARALLEL
546 select VIDEO_LCD_PANEL_I2C
547 ---help---
548 Select this for eDP LCD panels with 4 lanes running at 1.62G,
549 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200550
Hans de Goede27515b22015-01-20 09:23:36 +0100551config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
552 bool "Hitachi tx18d42vm LCD panel"
553 select VIDEO_LCD_HITACHI_TX18D42VM
554 select VIDEO_LCD_IF_LVDS
555 ---help---
556 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
557
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100558config VIDEO_LCD_TL059WV5C0
559 bool "tl059wv5c0 LCD panel"
560 select VIDEO_LCD_PANEL_I2C
561 select VIDEO_LCD_IF_PARALLEL
562 ---help---
563 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
564 Aigo M60/M608/M606 tablets.
565
Hans de Goede213480e2015-01-01 22:04:34 +0100566endchoice
567
568
Hans de Goedec13f60d2015-01-25 12:10:48 +0100569config GMAC_TX_DELAY
570 int "GMAC Transmit Clock Delay Chain"
571 default 0
572 ---help---
573 Set the GMAC Transmit Clock Delay Chain value.
574
Hans de Goedeff42d102015-09-13 13:02:48 +0200575config SPL_STACK_R_ADDR
576 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
577 default 0x2fe00000 if MACH_SUN9I
578
Masahiro Yamadadd840582014-07-30 14:08:14 +0900579endif