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Dirk Behmead9bc8e2009-01-28 21:39:58 +01001/*
Tom Rini673283f2011-11-18 12:48:09 +00002 * (C) Copyright 2004-2011
Dirk Behmead9bc8e2009-01-28 21:39:58 +01003 * Texas Instruments, <www.ti.com>
4 *
5 * Author :
6 * Manikandan Pillai <mani.pillai@ti.com>
7 *
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#include <common.h>
Ben Warren736fead2009-07-20 22:01:11 -070031#include <netdev.h>
Dirk Behmead9bc8e2009-01-28 21:39:58 +010032#include <asm/io.h>
33#include <asm/arch/mem.h>
34#include <asm/arch/mux.h>
35#include <asm/arch/sys_proto.h>
Vaibhav Hiremathdcc4f382011-09-03 21:42:35 -040036#include <asm/arch/mmc_host_def.h>
Sanjeev Premi84c3b632011-09-08 10:51:01 -040037#include <asm/gpio.h>
Dirk Behmead9bc8e2009-01-28 21:39:58 +010038#include <i2c.h>
39#include <asm/mach-types.h>
Tom Rini673283f2011-11-18 12:48:09 +000040#include <linux/mtd/nand.h>
Dirk Behmead9bc8e2009-01-28 21:39:58 +010041#include "evm.h"
42
Sriramakrishnanc0682582011-07-18 09:21:55 -040043#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
44#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
45
John Rigby29565322010-12-20 18:27:51 -070046DECLARE_GLOBAL_DATA_PTR;
47
Dirk Behmeb606ef42010-12-18 07:40:28 +010048static u32 omap3_evm_version;
Ajay Kumar Guptab5abf642010-06-10 11:20:49 +053049
Dirk Behmeb606ef42010-12-18 07:40:28 +010050u32 get_omap3_evm_rev(void)
Ajay Kumar Guptab5abf642010-06-10 11:20:49 +053051{
52 return omap3_evm_version;
53}
54
55static void omap3_evm_get_revision(void)
56{
Sanjeev Premi76ee9a22010-11-04 16:02:32 -040057#if defined(CONFIG_CMD_NET)
58 /*
59 * Board revision can be ascertained only by identifying
60 * the Ethernet chipset.
61 */
Ajay Kumar Guptab5abf642010-06-10 11:20:49 +053062 unsigned int smsc_id;
63
64 /* Ethernet PHY ID is stored at ID_REV register */
65 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
66 printf("Read back SMSC id 0x%x\n", smsc_id);
67
68 switch (smsc_id) {
69 /* SMSC9115 chipset */
70 case 0x01150000:
71 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
72 break;
73 /* SMSC 9220 chipset */
74 case 0x92200000:
75 default:
76 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
77 }
Sanjeev Premi76ee9a22010-11-04 16:02:32 -040078#else
79#if defined(CONFIG_STATIC_BOARD_REV)
80 /*
81 * Look for static defintion of the board revision
82 */
83 omap3_evm_version = CONFIG_STATIC_BOARD_REV;
84#else
85 /*
86 * Fallback to the default above.
87 */
88 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
89#endif
90#endif /* CONFIG_CMD_NET */
Ajay Kumar Guptab5abf642010-06-10 11:20:49 +053091}
92
Sanjeev Premi63f42402010-11-04 16:02:29 -040093#ifdef CONFIG_USB_OMAP3
Tom Rix58911512009-04-01 22:02:20 -050094/*
Ajay Kumar Gupta944a4892010-06-10 11:20:50 +053095 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
96 */
97u8 omap3_evm_need_extvbus(void)
98{
99 u8 retval = 0;
100
101 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
102 retval = 1;
103
104 return retval;
105}
Sanjeev Premi63f42402010-11-04 16:02:29 -0400106#endif
Ajay Kumar Gupta944a4892010-06-10 11:20:50 +0530107
108/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100109 * Routine: board_init
110 * Description: Early hardware init.
Tom Rix58911512009-04-01 22:02:20 -0500111 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100112int board_init(void)
113{
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100114 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
115 /* board id for Linux */
116 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
117 /* boot param addr */
118 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
119
120 return 0;
121}
122
Tom Rini673283f2011-11-18 12:48:09 +0000123#ifdef CONFIG_SPL_BUILD
124/*
125 * Routine: get_board_mem_timings
126 * Description: If we use SPL then there is no x-loader nor config header
127 * so we have to setup the DDR timings ourself on the first bank. This
128 * provides the timing values back to the function that configures
129 * the memory.
130 */
131void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
132 u32 *mr)
133{
134 int pop_mfr, pop_id;
135
136 /*
137 * We need to identify what PoP memory is on the board so that
138 * we know what timings to use. To map the ID values please see
139 * nand_ids.c
140 */
141 identify_nand_chip(&pop_mfr, &pop_id);
142
143 if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
144 /* 256MB DDR */
145 *mcfg = HYNIX_V_MCFG_200(256 << 20);
146 *ctrla = HYNIX_V_ACTIMA_200;
147 *ctrlb = HYNIX_V_ACTIMB_200;
148 } else {
149 /* 128MB DDR */
150 *mcfg = MICRON_V_MCFG_165(128 << 20);
151 *ctrla = MICRON_V_ACTIMA_165;
152 *ctrlb = MICRON_V_ACTIMB_165;
153 }
154 *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
155 *mr = MICRON_V_MR_165;
156}
157#endif
158
Tom Rix58911512009-04-01 22:02:20 -0500159/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100160 * Routine: misc_init_r
161 * Description: Init ethernet (done here so udelay works)
Tom Rix58911512009-04-01 22:02:20 -0500162 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100163int misc_init_r(void)
164{
165
166#ifdef CONFIG_DRIVER_OMAP34XX_I2C
167 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
168#endif
169
170#if defined(CONFIG_CMD_NET)
171 setup_net_chip();
172#endif
Sanjeev Premi76ee9a22010-11-04 16:02:32 -0400173 omap3_evm_get_revision();
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100174
Sanjeev Premi6921b312011-07-18 09:20:15 -0400175#if defined(CONFIG_CMD_NET)
176 reset_net_chip();
177#endif
Dirk Behmee6a6a702009-03-12 19:30:50 +0100178 dieid_num_r();
179
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100180 return 0;
181}
182
Tom Rix58911512009-04-01 22:02:20 -0500183/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100184 * Routine: set_muxconf_regs
185 * Description: Setting up the configuration Mux registers specific to the
186 * hardware. Many pins need to be moved from protect to primary
187 * mode.
Tom Rix58911512009-04-01 22:02:20 -0500188 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100189void set_muxconf_regs(void)
190{
191 MUX_EVM();
192}
193
Sanjeev Premi5626f332011-07-18 09:23:00 -0400194#ifdef CONFIG_CMD_NET
Tom Rix58911512009-04-01 22:02:20 -0500195/*
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100196 * Routine: setup_net_chip
197 * Description: Setting up the configuration GPMC registers specific to the
198 * Ethernet hardware.
Tom Rix58911512009-04-01 22:02:20 -0500199 */
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100200static void setup_net_chip(void)
201{
Dirk Behme97a099e2009-08-08 09:30:21 +0200202 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100203
204 /* Configure GPMC registers */
Dirk Behme89411352009-08-08 09:30:22 +0200205 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
206 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
207 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
208 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
209 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
210 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
211 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100212
213 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
214 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
215 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
216 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
217 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
218 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
219 &ctrl_base->gpmc_nadv_ale);
Sanjeev Premi6921b312011-07-18 09:20:15 -0400220}
221
222/**
223 * Reset the ethernet chip.
224 */
225static void reset_net_chip(void)
226{
Sriramakrishnanc0682582011-07-18 09:21:55 -0400227 int ret;
228 int rst_gpio;
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100229
Sriramakrishnanc0682582011-07-18 09:21:55 -0400230 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
231 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
232 } else {
233 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
234 }
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100235
Sanjeev Premi84c3b632011-09-08 10:51:01 -0400236 ret = gpio_request(rst_gpio, "");
Sriramakrishnanc0682582011-07-18 09:21:55 -0400237 if (ret < 0) {
238 printf("Unable to get GPIO %d\n", rst_gpio);
239 return ;
240 }
241
242 /* Configure as output */
Sanjeev Premi84c3b632011-09-08 10:51:01 -0400243 gpio_direction_output(rst_gpio, 0);
Sriramakrishnanc0682582011-07-18 09:21:55 -0400244
245 /* Send a pulse on the GPIO pin */
Sanjeev Premi84c3b632011-09-08 10:51:01 -0400246 gpio_set_value(rst_gpio, 1);
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100247 udelay(1);
Sanjeev Premi84c3b632011-09-08 10:51:01 -0400248 gpio_set_value(rst_gpio, 0);
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100249 udelay(1);
Sanjeev Premi84c3b632011-09-08 10:51:01 -0400250 gpio_set_value(rst_gpio, 1);
Dirk Behmead9bc8e2009-01-28 21:39:58 +0100251}
Ben Warren736fead2009-07-20 22:01:11 -0700252
253int board_eth_init(bd_t *bis)
254{
255 int rc = 0;
256#ifdef CONFIG_SMC911X
Sanjeev Premi5e463a22011-09-02 05:57:16 +0000257#define STR_ENV_ETHADDR "ethaddr"
258
259 struct eth_device *dev;
260 uchar eth_addr[6];
261
Ben Warren736fead2009-07-20 22:01:11 -0700262 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
Sanjeev Premi5e463a22011-09-02 05:57:16 +0000263
264 if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
265 dev = eth_get_dev_by_index(0);
266 if (dev) {
267 eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
268 } else {
269 printf("omap3evm: Couldn't get eth device\n");
270 rc = -1;
271 }
272 }
Ben Warren736fead2009-07-20 22:01:11 -0700273#endif
274 return rc;
275}
Sanjeev Premi5626f332011-07-18 09:23:00 -0400276#endif /* CONFIG_CMD_NET */
Vaibhav Hiremathdcc4f382011-09-03 21:42:35 -0400277
Tom Rini673283f2011-11-18 12:48:09 +0000278#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
Vaibhav Hiremathdcc4f382011-09-03 21:42:35 -0400279int board_mmc_init(bd_t *bis)
280{
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000281 omap_mmc_init(0, 0, 0);
Vaibhav Hiremathdcc4f382011-09-03 21:42:35 -0400282 return 0;
283}
284#endif