Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 8e39afcd942cdc52acaec33bce6b807b0dcc8cfe / . / arch / sandbox / dts / test.dts
blob: 57e0dd766317ac87afd10b2f6355811b097cee64 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glasse6c5c942018-10-01 12:22:08 -0600[diff] [blame]45 cros_ec: cros-ec {
46 reg = <0 0>;
47 compatible = "google,cros-ec-sandbox";
48
49 /*
50 * This describes the flash memory within the EC. Note
51 * that the STM32L flash erases to 0, not 0xff.
52 */
53 flash {
54 image-pos = <0x08000000>;
55 size = <0x20000>;
56 erase-value = <0>;
57
58 /* Information for sandbox */
59 ro {
60 image-pos = <0>;
61 size = <0xf000>;
62 };
63 wp-ro {
64 image-pos = <0xf000>;
65 size = <0x1000>;
66 };
67 rw {
68 image-pos = <0x10000>;
69 size = <0x10000>;
70 };
71 };
72 };
73
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]74 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]75 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]76 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]77 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]78 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]79 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]80 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
81 <0>, <&gpio_a 12>;
82 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
83 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
84 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]85 };
86
87 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]88 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]89 compatible = "not,compatible";
90 };
91
92 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]93 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]94 };
95
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]96 backlight: backlight {
97 compatible = "pwm-backlight";
98 enable-gpios = <&gpio_a 1>;
99 power-supply = <&ldo_1>;
100 pwms = <&pwm 0 1000>;
101 default-brightness-level = <5>;
102 brightness-levels = <0 16 32 64 128 170 202 234 255>;
103 };
104
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]105 bind-test {
106 bind-test-child1 {
107 compatible = "sandbox,phy";
108 #phy-cells = <1>;
109 };
110
111 bind-test-child2 {
112 compatible = "simple-bus";
113 };
114 };
115
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]116 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]117 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]118 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]119 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]120 ping-add = <3>;
121 };
122
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]123 phy_provider0: gen_phy@0 {
124 compatible = "sandbox,phy";
125 #phy-cells = <1>;
126 };
127
128 phy_provider1: gen_phy@1 {
129 compatible = "sandbox,phy";
130 #phy-cells = <0>;
131 broken;
132 };
133
134 gen_phy_user: gen_phy_user {
135 compatible = "simple-bus";
136 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
137 phy-names = "phy1", "phy2", "phy3";
138 };
139
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]140 some-bus {
141 #address-cells = <1>;
142 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]143 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]144 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]145 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]146 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]147 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]148 compatible = "denx,u-boot-fdt-test";
149 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]150 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]151 ping-add = <5>;
152 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]153 c-test@0 {
154 compatible = "denx,u-boot-fdt-test";
155 reg = <0>;
156 ping-expect = <6>;
157 ping-add = <6>;
158 };
159 c-test@1 {
160 compatible = "denx,u-boot-fdt-test";
161 reg = <1>;
162 ping-expect = <7>;
163 ping-add = <7>;
164 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]165 };
166
167 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]168 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]169 ping-expect = <6>;
170 ping-add = <6>;
171 compatible = "google,another-fdt-test";
172 };
173
174 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]175 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]176 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]181 f-test {
182 compatible = "denx,u-boot-fdt-test";
183 };
184
185 g-test {
186 compatible = "denx,u-boot-fdt-test";
187 };
188
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]189 clocks {
190 clk_fixed: clk-fixed {
191 compatible = "fixed-clock";
192 #clock-cells = <0>;
193 clock-frequency = <1234>;
194 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]195 };
196
197 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]198 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]199 #clock-cells = <1>;
200 };
201
202 clk-test {
203 compatible = "sandbox,clk-test";
204 clocks = <&clk_fixed>,
205 <&clk_sandbox 1>,
206 <&clk_sandbox 0>;
207 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]208 };
209
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]210 eth@10002000 {
211 compatible = "sandbox,eth";
212 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]213 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]214 };
215
216 eth_5: eth@10003000 {
217 compatible = "sandbox,eth";
218 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]219 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]220 };
221
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]222 eth_3: sbe5 {
223 compatible = "sandbox,eth";
224 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]225 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]226 };
227
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]228 eth@10004000 {
229 compatible = "sandbox,eth";
230 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]231 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]232 };
233
Rajan Vaja31b82172018-09-19 03:43:46 -0700[diff] [blame]234 firmware {
235 sandbox_firmware: sandbox-firmware {
236 compatible = "sandbox,firmware";
237 };
238 };
239
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]240 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]241 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]242 gpio-controller;
243 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]244 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]245 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]246 };
247
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]248 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]249 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]250 gpio-controller;
251 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]252 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]253 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]254 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]255
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]256 i2c@0 {
257 #address-cells = <1>;
258 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]259 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]260 compatible = "sandbox,i2c";
261 clock-frequency = <100000>;
262 eeprom@2c {
263 reg = <0x2c>;
264 compatible = "i2c-eeprom";
265 emul {
266 compatible = "sandbox,i2c-eeprom";
267 sandbox,filename = "i2c.bin";
268 sandbox,size = <256>;
269 };
270 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]271
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]272 rtc_0: rtc@43 {
273 reg = <0x43>;
274 compatible = "sandbox-rtc";
275 emul {
276 compatible = "sandbox,i2c-rtc";
277 };
278 };
279
280 rtc_1: rtc@61 {
281 reg = <0x61>;
282 compatible = "sandbox-rtc";
283 emul {
284 compatible = "sandbox,i2c-rtc";
285 };
286 };
287
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]288 sandbox_pmic: sandbox_pmic {
289 reg = <0x40>;
290 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]291
292 mc34708: pmic@41 {
293 reg = <0x41>;
294 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]295 };
296
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]297 adc@0 {
298 compatible = "sandbox,adc";
299 vdd-supply = <&buck2>;
300 vss-microvolts = <0>;
301 };
302
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]303 lcd {
304 u-boot,dm-pre-reloc;
305 compatible = "sandbox,lcd-sdl";
306 xres = <1366>;
307 yres = <768>;
308 };
309
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]310 leds {
311 compatible = "gpio-leds";
312
313 iracibble {
314 gpios = <&gpio_a 1 0>;
315 label = "sandbox:red";
316 };
317
318 martinet {
319 gpios = <&gpio_a 2 0>;
320 label = "sandbox:green";
321 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]322
323 default_on {
324 gpios = <&gpio_a 5 0>;
325 label = "sandbox:default_on";
326 default-state = "on";
327 };
328
329 default_off {
330 gpios = <&gpio_a 6 0>;
331 label = "sandbox:default_off";
332 default-state = "off";
333 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]334 };
335
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]336 mbox: mbox {
337 compatible = "sandbox,mbox";
338 #mbox-cells = <1>;
339 };
340
341 mbox-test {
342 compatible = "sandbox,mbox-test";
343 mboxes = <&mbox 100>, <&mbox 1>;
344 mbox-names = "other", "test";
345 };
346
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]347 cpu-test1 {
348 compatible = "sandbox,cpu_sandbox";
349 };
350
351 cpu-test2 {
352 compatible = "sandbox,cpu_sandbox";
353 };
354
355 cpu-test3 {
356 compatible = "sandbox,cpu_sandbox";
357 };
358
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]359 misc-test {
360 compatible = "sandbox,misc_sandbox";
361 };
362
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]363 mmc2 {
364 compatible = "sandbox,mmc";
365 };
366
367 mmc1 {
368 compatible = "sandbox,mmc";
369 };
370
371 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]372 compatible = "sandbox,mmc";
373 };
374
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]375 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]376 compatible = "sandbox,pci";
377 device_type = "pci";
378 #address-cells = <3>;
379 #size-cells = <2>;
380 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
381 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]382 pci@0,0 {
383 compatible = "pci-generic";
384 reg = <0x0000 0 0 0 0>;
385 emul@0,0 {
386 compatible = "sandbox,swap-case";
387 };
388 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]389 pci@1f,0 {
390 compatible = "pci-generic";
391 reg = <0xf800 0 0 0 0>;
392 emul@1f,0 {
393 compatible = "sandbox,swap-case";
394 };
395 };
396 };
397
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]398 pci1: pci-controller1 {
399 compatible = "sandbox,pci";
400 device_type = "pci";
401 #address-cells = <3>;
402 #size-cells = <2>;
403 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
404 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]405 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200[diff] [blame]406 0x0c 0x00 0x1234 0x5678
407 0x10 0x00 0x1234 0x5678>;
408 pci@10,0 {
409 reg = <0x8000 0 0 0 0>;
410 };
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]411 };
412
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]413 pci2: pci-controller2 {
414 compatible = "sandbox,pci";
415 device_type = "pci";
416 #address-cells = <3>;
417 #size-cells = <2>;
418 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
419 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
420 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
421 pci@1f,0 {
422 compatible = "pci-generic";
423 reg = <0xf800 0 0 0 0>;
424 emul@1f,0 {
425 compatible = "sandbox,swap-case";
426 };
427 };
428 };
429
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]430 probing {
431 compatible = "simple-bus";
432 test1 {
433 compatible = "denx,u-boot-probe-test";
434 };
435
436 test2 {
437 compatible = "denx,u-boot-probe-test";
438 };
439
440 test3 {
441 compatible = "denx,u-boot-probe-test";
442 };
443
444 test4 {
445 compatible = "denx,u-boot-probe-test";
446 };
447 };
448
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]449 pwrdom: power-domain {
450 compatible = "sandbox,power-domain";
451 #power-domain-cells = <1>;
452 };
453
454 power-domain-test {
455 compatible = "sandbox,power-domain-test";
456 power-domains = <&pwrdom 2>;
457 };
458
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]459 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]460 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]461 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]462 };
463
464 pwm2 {
465 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]466 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]467 };
468
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]469 ram {
470 compatible = "sandbox,ram";
471 };
472
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]473 reset@0 {
474 compatible = "sandbox,warm-reset";
475 };
476
477 reset@1 {
478 compatible = "sandbox,reset";
479 };
480
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]481 resetc: reset-ctl {
482 compatible = "sandbox,reset-ctl";
483 #reset-cells = <1>;
484 };
485
486 reset-ctl-test {
487 compatible = "sandbox,reset-ctl-test";
488 resets = <&resetc 100>, <&resetc 2>;
489 reset-names = "other", "test";
490 };
491
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]492 rproc_1: rproc@1 {
493 compatible = "sandbox,test-processor";
494 remoteproc-name = "remoteproc-test-dev1";
495 };
496
497 rproc_2: rproc@2 {
498 compatible = "sandbox,test-processor";
499 internal-memory-mapped;
500 remoteproc-name = "remoteproc-test-dev2";
501 };
502
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]503 panel {
504 compatible = "simple-panel";
505 backlight = <&backlight 0 100>;
506 };
507
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]508 smem@0 {
509 compatible = "sandbox,smem";
510 };
511
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]512 spi@0 {
513 #address-cells = <1>;
514 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]515 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]516 compatible = "sandbox,spi";
517 cs-gpios = <0>, <&gpio_a 0>;
518 spi.bin@0 {
519 reg = <0>;
520 compatible = "spansion,m25p16", "spi-flash";
521 spi-max-frequency = <40000000>;
522 sandbox,filename = "spi.bin";
523 };
524 };
525
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]526 syscon@0 {
527 compatible = "sandbox,syscon0";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]528 reg = <0x10 4>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]529 };
530
531 syscon@1 {
532 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]533 reg = <0x20 5
534 0x28 6
535 0x30 7
536 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]537 };
538
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]539 syscon@2 {
540 compatible = "simple-mfd", "syscon";
541 reg = <0x40 5
542 0x48 6
543 0x50 7
544 0x58 8>;
545 };
546
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]547 timer {
548 compatible = "sandbox,timer";
549 clock-frequency = <1000000>;
550 };
551
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]552 tpm2 {
553 compatible = "sandbox,tpm2";
554 };
555
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]556 uart0: serial {
557 compatible = "sandbox,serial";
558 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]559 };
560
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]561 usb_0: usb@0 {
562 compatible = "sandbox,usb";
563 status = "disabled";
564 hub {
565 compatible = "sandbox,usb-hub";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 flash-stick {
569 reg = <0>;
570 compatible = "sandbox,usb-flash";
571 };
572 };
573 };
574
575 usb_1: usb@1 {
576 compatible = "sandbox,usb";
577 hub {
578 compatible = "usb-hub";
579 usb,device-class = <9>;
580 hub-emul {
581 compatible = "sandbox,usb-hub";
582 #address-cells = <1>;
583 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]584 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]585 reg = <0>;
586 compatible = "sandbox,usb-flash";
587 sandbox,filepath = "testflash.bin";
588 };
589
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]590 flash-stick@1 {
591 reg = <1>;
592 compatible = "sandbox,usb-flash";
593 sandbox,filepath = "testflash1.bin";
594 };
595
596 flash-stick@2 {
597 reg = <2>;
598 compatible = "sandbox,usb-flash";
599 sandbox,filepath = "testflash2.bin";
600 };
601
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]602 keyb@3 {
603 reg = <3>;
604 compatible = "sandbox,usb-keyb";
605 };
606
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]607 };
608 };
609 };
610
611 usb_2: usb@2 {
612 compatible = "sandbox,usb";
613 status = "disabled";
614 };
615
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]616 spmi: spmi@0 {
617 compatible = "sandbox,spmi";
618 #address-cells = <0x1>;
619 #size-cells = <0x1>;
620 pm8916@0 {
621 compatible = "qcom,spmi-pmic";
622 reg = <0x0 0x1>;
623 #address-cells = <0x1>;
624 #size-cells = <0x1>;
625
626 spmi_gpios: gpios@c000 {
627 compatible = "qcom,pm8916-gpio";
628 reg = <0xc000 0x400>;
629 gpio-controller;
630 gpio-count = <4>;
631 #gpio-cells = <2>;
632 gpio-bank-name="spmi";
633 };
634 };
635 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]636
637 wdt0: wdt@0 {
638 compatible = "sandbox,wdt";
639 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]640
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]641 axi: axi@0 {
642 compatible = "sandbox,axi";
643 #address-cells = <0x1>;
644 #size-cells = <0x1>;
645 store@0 {
646 compatible = "sandbox,sandbox_store";
647 reg = <0x0 0x400>;
648 };
649 };
650
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]651 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]652 #address-cells = <1>;
653 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]654 chosen-test {
655 compatible = "denx,u-boot-fdt-test";
656 reg = <9 1>;
657 };
658 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]659
660 translation-test@8000 {
661 compatible = "simple-bus";
662 reg = <0x8000 0x4000>;
663
664 #address-cells = <0x2>;
665 #size-cells = <0x1>;
666
667 ranges = <0 0x0 0x8000 0x1000
668 1 0x100 0x9000 0x1000
669 2 0x200 0xA000 0x1000
670 3 0x300 0xB000 0x1000
671 >;
672
673 dev@0,0 {
674 compatible = "denx,u-boot-fdt-dummy";
675 reg = <0 0x0 0x1000>;
676 };
677
678 dev@1,100 {
679 compatible = "denx,u-boot-fdt-dummy";
680 reg = <1 0x100 0x1000>;
681
682 };
683
684 dev@2,200 {
685 compatible = "denx,u-boot-fdt-dummy";
686 reg = <2 0x200 0x1000>;
687 };
688
689
690 noxlatebus@3,300 {
691 compatible = "simple-bus";
692 reg = <3 0x300 0x1000>;
693
694 #address-cells = <0x1>;
695 #size-cells = <0x0>;
696
697 dev@42 {
698 compatible = "denx,u-boot-fdt-dummy";
699 reg = <0x42>;
700 };
701 };
702 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]703
704 osd {
705 compatible = "sandbox,sandbox_osd";
706 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400[diff] [blame]707
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]708 board {
709 compatible = "sandbox,board_sandbox";
710 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200[diff] [blame]711
712 sandbox_tee {
713 compatible = "sandbox,tee";
714 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]715};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]716
717#include "sandbox_pmic.dtsi"