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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e7a52ba65be227f4fa06b851d1d92af1bef694e0 / . / arch / sandbox / dts / test.dts
blob: 751c13b51da293f670547ae75fe4a16cffd67f50 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]17 pci0 = &pci0;
18 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]19 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]20 remoteproc1 = &rproc_1;
21 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]22 rtc0 = &rtc_0;
23 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]24 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]25 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]26 testbus3 = "/some-bus";
27 testfdt0 = "/some-bus/c-test@0";
28 testfdt1 = "/some-bus/c-test@1";
29 testfdt3 = "/b-test";
30 testfdt5 = "/some-bus/c-test@5";
31 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]32 fdt-dummy0 = "/translation-test@8000/dev@0,0";
33 fdt-dummy1 = "/translation-test@8000/dev@1,100";
34 fdt-dummy2 = "/translation-test@8000/dev@2,200";
35 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]36 usb0 = &usb_0;
37 usb1 = &usb_1;
38 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]39 axi0 = &axi;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]40 };
41
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]42 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]43 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]44 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]45 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]46 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]47 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]48 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
49 <0>, <&gpio_a 12>;
50 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
51 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
52 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]53 };
54
55 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]56 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]57 compatible = "not,compatible";
58 };
59
60 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]61 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]62 };
63
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]64 bind-test {
65 bind-test-child1 {
66 compatible = "sandbox,phy";
67 #phy-cells = <1>;
68 };
69
70 bind-test-child2 {
71 compatible = "simple-bus";
72 };
73 };
74
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]75 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]76 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]77 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]78 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]79 ping-add = <3>;
80 };
81
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]82 phy_provider0: gen_phy@0 {
83 compatible = "sandbox,phy";
84 #phy-cells = <1>;
85 };
86
87 phy_provider1: gen_phy@1 {
88 compatible = "sandbox,phy";
89 #phy-cells = <0>;
90 broken;
91 };
92
93 gen_phy_user: gen_phy_user {
94 compatible = "simple-bus";
95 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
96 phy-names = "phy1", "phy2", "phy3";
97 };
98
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]99 some-bus {
100 #address-cells = <1>;
101 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]102 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]103 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]104 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]105 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]106 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]107 compatible = "denx,u-boot-fdt-test";
108 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]109 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]110 ping-add = <5>;
111 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]112 c-test@0 {
113 compatible = "denx,u-boot-fdt-test";
114 reg = <0>;
115 ping-expect = <6>;
116 ping-add = <6>;
117 };
118 c-test@1 {
119 compatible = "denx,u-boot-fdt-test";
120 reg = <1>;
121 ping-expect = <7>;
122 ping-add = <7>;
123 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]124 };
125
126 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]127 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]128 ping-expect = <6>;
129 ping-add = <6>;
130 compatible = "google,another-fdt-test";
131 };
132
133 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]134 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]135 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]136 ping-add = <6>;
137 compatible = "google,another-fdt-test";
138 };
139
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]140 f-test {
141 compatible = "denx,u-boot-fdt-test";
142 };
143
144 g-test {
145 compatible = "denx,u-boot-fdt-test";
146 };
147
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]148 clocks {
149 clk_fixed: clk-fixed {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <1234>;
153 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]154 };
155
156 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]157 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]158 #clock-cells = <1>;
159 };
160
161 clk-test {
162 compatible = "sandbox,clk-test";
163 clocks = <&clk_fixed>,
164 <&clk_sandbox 1>,
165 <&clk_sandbox 0>;
166 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]167 };
168
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]169 eth@10002000 {
170 compatible = "sandbox,eth";
171 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]172 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]173 };
174
175 eth_5: eth@10003000 {
176 compatible = "sandbox,eth";
177 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]178 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]179 };
180
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]181 eth_3: sbe5 {
182 compatible = "sandbox,eth";
183 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]184 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]185 };
186
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]187 eth@10004000 {
188 compatible = "sandbox,eth";
189 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]190 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]191 };
192
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]193 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]194 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]195 gpio-controller;
196 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]197 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]198 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]199 };
200
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]201 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]202 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]203 gpio-controller;
204 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]205 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]206 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]207 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]208
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]209 i2c@0 {
210 #address-cells = <1>;
211 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]212 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]213 compatible = "sandbox,i2c";
214 clock-frequency = <100000>;
215 eeprom@2c {
216 reg = <0x2c>;
217 compatible = "i2c-eeprom";
218 emul {
219 compatible = "sandbox,i2c-eeprom";
220 sandbox,filename = "i2c.bin";
221 sandbox,size = <256>;
222 };
223 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]224
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]225 rtc_0: rtc@43 {
226 reg = <0x43>;
227 compatible = "sandbox-rtc";
228 emul {
229 compatible = "sandbox,i2c-rtc";
230 };
231 };
232
233 rtc_1: rtc@61 {
234 reg = <0x61>;
235 compatible = "sandbox-rtc";
236 emul {
237 compatible = "sandbox,i2c-rtc";
238 };
239 };
240
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]241 sandbox_pmic: sandbox_pmic {
242 reg = <0x40>;
243 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]244
245 mc34708: pmic@41 {
246 reg = <0x41>;
247 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]248 };
249
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]250 adc@0 {
251 compatible = "sandbox,adc";
252 vdd-supply = <&buck2>;
253 vss-microvolts = <0>;
254 };
255
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]256 lcd {
257 u-boot,dm-pre-reloc;
258 compatible = "sandbox,lcd-sdl";
259 xres = <1366>;
260 yres = <768>;
261 };
262
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]263 leds {
264 compatible = "gpio-leds";
265
266 iracibble {
267 gpios = <&gpio_a 1 0>;
268 label = "sandbox:red";
269 };
270
271 martinet {
272 gpios = <&gpio_a 2 0>;
273 label = "sandbox:green";
274 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]275
276 default_on {
277 gpios = <&gpio_a 5 0>;
278 label = "sandbox:default_on";
279 default-state = "on";
280 };
281
282 default_off {
283 gpios = <&gpio_a 6 0>;
284 label = "sandbox:default_off";
285 default-state = "off";
286 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]287 };
288
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]289 mbox: mbox {
290 compatible = "sandbox,mbox";
291 #mbox-cells = <1>;
292 };
293
294 mbox-test {
295 compatible = "sandbox,mbox-test";
296 mboxes = <&mbox 100>, <&mbox 1>;
297 mbox-names = "other", "test";
298 };
299
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]300 cpu-test1 {
301 compatible = "sandbox,cpu_sandbox";
302 };
303
304 cpu-test2 {
305 compatible = "sandbox,cpu_sandbox";
306 };
307
308 cpu-test3 {
309 compatible = "sandbox,cpu_sandbox";
310 };
311
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]312 misc-test {
313 compatible = "sandbox,misc_sandbox";
314 };
315
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]316 mmc2 {
317 compatible = "sandbox,mmc";
318 };
319
320 mmc1 {
321 compatible = "sandbox,mmc";
322 };
323
324 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]325 compatible = "sandbox,mmc";
326 };
327
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]328 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]329 compatible = "sandbox,pci";
330 device_type = "pci";
331 #address-cells = <3>;
332 #size-cells = <2>;
333 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
334 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]335 pci@0,0 {
336 compatible = "pci-generic";
337 reg = <0x0000 0 0 0 0>;
338 emul@0,0 {
339 compatible = "sandbox,swap-case";
340 };
341 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]342 pci@1f,0 {
343 compatible = "pci-generic";
344 reg = <0xf800 0 0 0 0>;
345 emul@1f,0 {
346 compatible = "sandbox,swap-case";
347 };
348 };
349 };
350
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]351 pci1: pci-controller1 {
352 compatible = "sandbox,pci";
353 device_type = "pci";
354 #address-cells = <3>;
355 #size-cells = <2>;
356 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
357 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]358 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
359 0x0c 0x00 0x1234 0x5678>;
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]360 };
361
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]362 pci2: pci-controller2 {
363 compatible = "sandbox,pci";
364 device_type = "pci";
365 #address-cells = <3>;
366 #size-cells = <2>;
367 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
368 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
369 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
370 pci@1f,0 {
371 compatible = "pci-generic";
372 reg = <0xf800 0 0 0 0>;
373 emul@1f,0 {
374 compatible = "sandbox,swap-case";
375 };
376 };
377 };
378
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]379 probing {
380 compatible = "simple-bus";
381 test1 {
382 compatible = "denx,u-boot-probe-test";
383 };
384
385 test2 {
386 compatible = "denx,u-boot-probe-test";
387 };
388
389 test3 {
390 compatible = "denx,u-boot-probe-test";
391 };
392
393 test4 {
394 compatible = "denx,u-boot-probe-test";
395 };
396 };
397
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]398 pwrdom: power-domain {
399 compatible = "sandbox,power-domain";
400 #power-domain-cells = <1>;
401 };
402
403 power-domain-test {
404 compatible = "sandbox,power-domain-test";
405 power-domains = <&pwrdom 2>;
406 };
407
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]408 pwm {
409 compatible = "sandbox,pwm";
410 };
411
412 pwm2 {
413 compatible = "sandbox,pwm";
414 };
415
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]416 ram {
417 compatible = "sandbox,ram";
418 };
419
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]420 reset@0 {
421 compatible = "sandbox,warm-reset";
422 };
423
424 reset@1 {
425 compatible = "sandbox,reset";
426 };
427
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]428 resetc: reset-ctl {
429 compatible = "sandbox,reset-ctl";
430 #reset-cells = <1>;
431 };
432
433 reset-ctl-test {
434 compatible = "sandbox,reset-ctl-test";
435 resets = <&resetc 100>, <&resetc 2>;
436 reset-names = "other", "test";
437 };
438
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]439 rproc_1: rproc@1 {
440 compatible = "sandbox,test-processor";
441 remoteproc-name = "remoteproc-test-dev1";
442 };
443
444 rproc_2: rproc@2 {
445 compatible = "sandbox,test-processor";
446 internal-memory-mapped;
447 remoteproc-name = "remoteproc-test-dev2";
448 };
449
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]450 smem@0 {
451 compatible = "sandbox,smem";
452 };
453
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]454 spi@0 {
455 #address-cells = <1>;
456 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]457 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]458 compatible = "sandbox,spi";
459 cs-gpios = <0>, <&gpio_a 0>;
460 spi.bin@0 {
461 reg = <0>;
462 compatible = "spansion,m25p16", "spi-flash";
463 spi-max-frequency = <40000000>;
464 sandbox,filename = "spi.bin";
465 };
466 };
467
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]468 syscon@0 {
469 compatible = "sandbox,syscon0";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]470 reg = <0x10 4>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]471 };
472
473 syscon@1 {
474 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]475 reg = <0x20 5
476 0x28 6
477 0x30 7
478 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]479 };
480
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]481 syscon@2 {
482 compatible = "simple-mfd", "syscon";
483 reg = <0x40 5
484 0x48 6
485 0x50 7
486 0x58 8>;
487 };
488
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]489 timer {
490 compatible = "sandbox,timer";
491 clock-frequency = <1000000>;
492 };
493
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]494 tpm2 {
495 compatible = "sandbox,tpm2";
496 };
497
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]498 uart0: serial {
499 compatible = "sandbox,serial";
500 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]501 };
502
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]503 usb_0: usb@0 {
504 compatible = "sandbox,usb";
505 status = "disabled";
506 hub {
507 compatible = "sandbox,usb-hub";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 flash-stick {
511 reg = <0>;
512 compatible = "sandbox,usb-flash";
513 };
514 };
515 };
516
517 usb_1: usb@1 {
518 compatible = "sandbox,usb";
519 hub {
520 compatible = "usb-hub";
521 usb,device-class = <9>;
522 hub-emul {
523 compatible = "sandbox,usb-hub";
524 #address-cells = <1>;
525 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]526 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]527 reg = <0>;
528 compatible = "sandbox,usb-flash";
529 sandbox,filepath = "testflash.bin";
530 };
531
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]532 flash-stick@1 {
533 reg = <1>;
534 compatible = "sandbox,usb-flash";
535 sandbox,filepath = "testflash1.bin";
536 };
537
538 flash-stick@2 {
539 reg = <2>;
540 compatible = "sandbox,usb-flash";
541 sandbox,filepath = "testflash2.bin";
542 };
543
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]544 keyb@3 {
545 reg = <3>;
546 compatible = "sandbox,usb-keyb";
547 };
548
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]549 };
550 };
551 };
552
553 usb_2: usb@2 {
554 compatible = "sandbox,usb";
555 status = "disabled";
556 };
557
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]558 spmi: spmi@0 {
559 compatible = "sandbox,spmi";
560 #address-cells = <0x1>;
561 #size-cells = <0x1>;
562 pm8916@0 {
563 compatible = "qcom,spmi-pmic";
564 reg = <0x0 0x1>;
565 #address-cells = <0x1>;
566 #size-cells = <0x1>;
567
568 spmi_gpios: gpios@c000 {
569 compatible = "qcom,pm8916-gpio";
570 reg = <0xc000 0x400>;
571 gpio-controller;
572 gpio-count = <4>;
573 #gpio-cells = <2>;
574 gpio-bank-name="spmi";
575 };
576 };
577 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]578
579 wdt0: wdt@0 {
580 compatible = "sandbox,wdt";
581 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]582
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]583 axi: axi@0 {
584 compatible = "sandbox,axi";
585 #address-cells = <0x1>;
586 #size-cells = <0x1>;
587 store@0 {
588 compatible = "sandbox,sandbox_store";
589 reg = <0x0 0x400>;
590 };
591 };
592
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]593 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]594 #address-cells = <1>;
595 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]596 chosen-test {
597 compatible = "denx,u-boot-fdt-test";
598 reg = <9 1>;
599 };
600 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]601
602 translation-test@8000 {
603 compatible = "simple-bus";
604 reg = <0x8000 0x4000>;
605
606 #address-cells = <0x2>;
607 #size-cells = <0x1>;
608
609 ranges = <0 0x0 0x8000 0x1000
610 1 0x100 0x9000 0x1000
611 2 0x200 0xA000 0x1000
612 3 0x300 0xB000 0x1000
613 >;
614
615 dev@0,0 {
616 compatible = "denx,u-boot-fdt-dummy";
617 reg = <0 0x0 0x1000>;
618 };
619
620 dev@1,100 {
621 compatible = "denx,u-boot-fdt-dummy";
622 reg = <1 0x100 0x1000>;
623
624 };
625
626 dev@2,200 {
627 compatible = "denx,u-boot-fdt-dummy";
628 reg = <2 0x200 0x1000>;
629 };
630
631
632 noxlatebus@3,300 {
633 compatible = "simple-bus";
634 reg = <3 0x300 0x1000>;
635
636 #address-cells = <0x1>;
637 #size-cells = <0x0>;
638
639 dev@42 {
640 compatible = "denx,u-boot-fdt-dummy";
641 reg = <0x42>;
642 };
643 };
644 };
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]645
646 board {
647 compatible = "sandbox,board_sandbox";
648 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]649};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]650
651#include "sandbox_pmic.dtsi"