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Michal Simek185f7d92012-09-13 20:23:34 +00001/*
2 * (C) Copyright 2011 Michal Simek
3 *
4 * Michal SIMEK <monstr@monstr.eu>
5 *
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
8 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02009 * SPDX-License-Identifier: GPL-2.0+
Michal Simek185f7d92012-09-13 20:23:34 +000010 */
11
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +053012#include <clk.h>
Michal Simek185f7d92012-09-13 20:23:34 +000013#include <common.h>
Michal Simek6889ca72015-11-30 14:14:56 +010014#include <dm.h>
Michal Simek185f7d92012-09-13 20:23:34 +000015#include <net.h>
Michal Simek2fd24892014-04-25 14:17:38 +020016#include <netdev.h>
Michal Simek185f7d92012-09-13 20:23:34 +000017#include <config.h>
Michal Simekb8de29f2015-09-24 20:13:45 +020018#include <console.h>
Michal Simek185f7d92012-09-13 20:23:34 +000019#include <malloc.h>
20#include <asm/io.h>
21#include <phy.h>
22#include <miiphy.h>
Mateusz Kulikowskie7138b32016-01-23 11:54:33 +010023#include <wait_bit.h>
Michal Simek185f7d92012-09-13 20:23:34 +000024#include <watchdog.h>
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +053025#include <asm/system.h>
David Andrey01fbf312013-04-05 17:24:24 +020026#include <asm/arch/hardware.h>
Michal Simek80243522012-10-15 14:01:23 +020027#include <asm/arch/sys_proto.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090028#include <linux/errno.h>
Michal Simek185f7d92012-09-13 20:23:34 +000029
Michal Simek6889ca72015-11-30 14:14:56 +010030DECLARE_GLOBAL_DATA_PTR;
31
Michal Simek185f7d92012-09-13 20:23:34 +000032/* Bit/mask specification */
33#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
38
39#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
42
43#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
46
47/* Wrap bit, last descriptor */
48#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
Michal Simek23a598f2015-08-17 09:58:54 +020050#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
Michal Simek185f7d92012-09-13 20:23:34 +000051
Michal Simek185f7d92012-09-13 20:23:34 +000052#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
56
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053057#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
58#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
59#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
60#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
Siva Durga Prasad Paladugu4eaf8f52016-05-16 15:31:38 +053061#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053062#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
Michal Simekf17ea712015-09-08 17:20:01 +020063#ifdef CONFIG_ARM64
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053064#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
Michal Simekf17ea712015-09-08 17:20:01 +020065#else
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053066#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
Michal Simekf17ea712015-09-08 17:20:01 +020067#endif
Michal Simek185f7d92012-09-13 20:23:34 +000068
Siva Durga Prasad Paladugu8a584c82014-07-08 15:31:03 +053069#ifdef CONFIG_ARM64
70# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
71#else
72# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
73#endif
74
75#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
76 ZYNQ_GEM_NWCFG_FDEN | \
Michal Simek185f7d92012-09-13 20:23:34 +000077 ZYNQ_GEM_NWCFG_FSREM | \
78 ZYNQ_GEM_NWCFG_MDCCLKDIV)
79
80#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
81
82#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
83/* Use full configured addressable space (8 Kb) */
84#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
85/* Use full configured addressable space (4 Kb) */
86#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
87/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
88#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
89
90#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
91 ZYNQ_GEM_DMACR_RXSIZE | \
92 ZYNQ_GEM_DMACR_TXSIZE | \
93 ZYNQ_GEM_DMACR_RXBUF)
94
Michal Simeke4d23182015-08-17 09:57:46 +020095#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
96
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +053097#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
98
Michal Simekf97d7e82013-04-22 14:41:09 +020099/* Use MII register 1 (MII status register) to detect PHY */
100#define PHY_DETECT_REG 1
101
102/* Mask used to verify certain PHY features (or register contents)
103 * in the register above:
104 * 0x1000: 10Mbps full duplex support
105 * 0x0800: 10Mbps half duplex support
106 * 0x0008: Auto-negotiation support
107 */
108#define PHY_DETECT_MASK 0x1808
109
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530110/* TX BD status masks */
111#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
112#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
113#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
114
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800115/* Clock frequencies for different speeds */
116#define ZYNQ_GEM_FREQUENCY_10 2500000UL
117#define ZYNQ_GEM_FREQUENCY_100 25000000UL
118#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
119
Michal Simek185f7d92012-09-13 20:23:34 +0000120/* Device registers */
121struct zynq_gem_regs {
Michal Simek97a51a02015-10-05 11:49:43 +0200122 u32 nwctrl; /* 0x0 - Network Control reg */
123 u32 nwcfg; /* 0x4 - Network Config reg */
124 u32 nwsr; /* 0x8 - Network Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000125 u32 reserved1;
Michal Simek97a51a02015-10-05 11:49:43 +0200126 u32 dmacr; /* 0x10 - DMA Control reg */
127 u32 txsr; /* 0x14 - TX Status reg */
128 u32 rxqbase; /* 0x18 - RX Q Base address reg */
129 u32 txqbase; /* 0x1c - TX Q Base address reg */
130 u32 rxsr; /* 0x20 - RX Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000131 u32 reserved2[2];
Michal Simek97a51a02015-10-05 11:49:43 +0200132 u32 idr; /* 0x2c - Interrupt Disable reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000133 u32 reserved3;
Michal Simek97a51a02015-10-05 11:49:43 +0200134 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000135 u32 reserved4[18];
Michal Simek97a51a02015-10-05 11:49:43 +0200136 u32 hashl; /* 0x80 - Hash Low address reg */
137 u32 hashh; /* 0x84 - Hash High address reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000138#define LADDR_LOW 0
139#define LADDR_HIGH 1
Michal Simek97a51a02015-10-05 11:49:43 +0200140 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
141 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000142 u32 reserved6[18];
Michal Simek0ebf4042015-10-05 12:49:48 +0200143#define STAT_SIZE 44
144 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +0530145 u32 reserved9[20];
146 u32 pcscntrl;
147 u32 reserved7[143];
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700148 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
149 u32 reserved8[15];
150 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
Michal Simek185f7d92012-09-13 20:23:34 +0000151};
152
153/* BD descriptors */
154struct emac_bd {
155 u32 addr; /* Next descriptor pointer */
156 u32 status;
157};
158
Siva Durga Prasad Paladugueda9d302015-04-15 12:15:01 +0530159#define RX_BUF 32
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530160/* Page table entries are set to 1MB, or multiples of 1MB
161 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
162 */
163#define BD_SPACE 0x100000
164/* BD separation space */
Michal Simekff475872015-08-17 09:45:53 +0200165#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
Michal Simek185f7d92012-09-13 20:23:34 +0000166
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700167/* Setup the first free TX descriptor */
168#define TX_FREE_DESC 2
169
Michal Simek185f7d92012-09-13 20:23:34 +0000170/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
171struct zynq_gem_priv {
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530172 struct emac_bd *tx_bd;
173 struct emac_bd *rx_bd;
174 char *rxbuffers;
Michal Simek185f7d92012-09-13 20:23:34 +0000175 u32 rxbd_current;
176 u32 rx_first_buf;
177 int phyaddr;
Michal Simek05868752013-01-24 13:04:12 +0100178 int init;
Michal Simekf2fc2762015-11-30 10:24:15 +0100179 struct zynq_gem_regs *iobase;
Michal Simek16ce6de2015-10-07 16:42:56 +0200180 phy_interface_t interface;
Michal Simek185f7d92012-09-13 20:23:34 +0000181 struct phy_device *phydev;
Dan Murphy20671a92016-05-02 15:45:57 -0500182 int phy_of_handle;
Michal Simek185f7d92012-09-13 20:23:34 +0000183 struct mii_dev *bus;
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530184 struct clk clk;
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530185 bool int_pcs;
Michal Simek185f7d92012-09-13 20:23:34 +0000186};
187
Michal Simekf2fc2762015-11-30 10:24:15 +0100188static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
189 u32 op, u16 *data)
Michal Simek185f7d92012-09-13 20:23:34 +0000190{
191 u32 mgtcr;
Michal Simekf2fc2762015-11-30 10:24:15 +0100192 struct zynq_gem_regs *regs = priv->iobase;
Michal Simekb908fca2016-12-12 09:47:26 +0100193 int err;
Michal Simek185f7d92012-09-13 20:23:34 +0000194
Michal Simekb908fca2016-12-12 09:47:26 +0100195 err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
Siva Durga Prasad Paladugudea004e2017-05-30 14:28:39 +0200196 true, 20000, false);
Michal Simekb908fca2016-12-12 09:47:26 +0100197 if (err)
198 return err;
Michal Simek185f7d92012-09-13 20:23:34 +0000199
200 /* Construct mgtcr mask for the operation */
201 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
202 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
203 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
204
205 /* Write mgtcr and wait for completion */
206 writel(mgtcr, &regs->phymntnc);
207
Michal Simekb908fca2016-12-12 09:47:26 +0100208 err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
Siva Durga Prasad Paladugudea004e2017-05-30 14:28:39 +0200209 true, 20000, false);
Michal Simekb908fca2016-12-12 09:47:26 +0100210 if (err)
211 return err;
Michal Simek185f7d92012-09-13 20:23:34 +0000212
213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
214 *data = readl(&regs->phymntnc);
215
216 return 0;
217}
218
Michal Simekf2fc2762015-11-30 10:24:15 +0100219static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
220 u32 regnum, u16 *val)
Michal Simek185f7d92012-09-13 20:23:34 +0000221{
Michal Simek198e9a42015-10-07 16:34:51 +0200222 u32 ret;
223
Michal Simekf2fc2762015-11-30 10:24:15 +0100224 ret = phy_setup_op(priv, phy_addr, regnum,
225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
Michal Simek198e9a42015-10-07 16:34:51 +0200226
227 if (!ret)
228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
229 phy_addr, regnum, *val);
230
231 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000232}
233
Michal Simekf2fc2762015-11-30 10:24:15 +0100234static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
235 u32 regnum, u16 data)
Michal Simek185f7d92012-09-13 20:23:34 +0000236{
Michal Simek198e9a42015-10-07 16:34:51 +0200237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
238 regnum, data);
239
Michal Simekf2fc2762015-11-30 10:24:15 +0100240 return phy_setup_op(priv, phy_addr, regnum,
241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
Michal Simek185f7d92012-09-13 20:23:34 +0000242}
243
Michal Simek6889ca72015-11-30 14:14:56 +0100244static int phy_detection(struct udevice *dev)
Michal Simekf97d7e82013-04-22 14:41:09 +0200245{
246 int i;
247 u16 phyreg;
248 struct zynq_gem_priv *priv = dev->priv;
249
250 if (priv->phyaddr != -1) {
Michal Simekf2fc2762015-11-30 10:24:15 +0100251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
Michal Simekf97d7e82013-04-22 14:41:09 +0200252 if ((phyreg != 0xFFFF) &&
253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
254 /* Found a valid PHY address */
255 debug("Default phy address %d is valid\n",
256 priv->phyaddr);
Michal Simekb9047252015-11-30 13:38:32 +0100257 return 0;
Michal Simekf97d7e82013-04-22 14:41:09 +0200258 } else {
259 debug("PHY address is not setup correctly %d\n",
260 priv->phyaddr);
261 priv->phyaddr = -1;
262 }
263 }
264
265 debug("detecting phy address\n");
266 if (priv->phyaddr == -1) {
267 /* detect the PHY address */
268 for (i = 31; i >= 0; i--) {
Michal Simekf2fc2762015-11-30 10:24:15 +0100269 phyread(priv, i, PHY_DETECT_REG, &phyreg);
Michal Simekf97d7e82013-04-22 14:41:09 +0200270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
273 priv->phyaddr = i;
274 debug("Found valid phy address, %d\n", i);
Michal Simekb9047252015-11-30 13:38:32 +0100275 return 0;
Michal Simekf97d7e82013-04-22 14:41:09 +0200276 }
277 }
278 }
279 printf("PHY is not detected\n");
Michal Simekb9047252015-11-30 13:38:32 +0100280 return -1;
Michal Simekf97d7e82013-04-22 14:41:09 +0200281}
282
Michal Simek6889ca72015-11-30 14:14:56 +0100283static int zynq_gem_setup_mac(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000284{
285 u32 i, macaddrlow, macaddrhigh;
Michal Simek6889ca72015-11-30 14:14:56 +0100286 struct eth_pdata *pdata = dev_get_platdata(dev);
287 struct zynq_gem_priv *priv = dev_get_priv(dev);
288 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000289
290 /* Set the MAC bits [31:0] in BOT */
Michal Simek6889ca72015-11-30 14:14:56 +0100291 macaddrlow = pdata->enetaddr[0];
292 macaddrlow |= pdata->enetaddr[1] << 8;
293 macaddrlow |= pdata->enetaddr[2] << 16;
294 macaddrlow |= pdata->enetaddr[3] << 24;
Michal Simek185f7d92012-09-13 20:23:34 +0000295
296 /* Set MAC bits [47:32] in TOP */
Michal Simek6889ca72015-11-30 14:14:56 +0100297 macaddrhigh = pdata->enetaddr[4];
298 macaddrhigh |= pdata->enetaddr[5] << 8;
Michal Simek185f7d92012-09-13 20:23:34 +0000299
300 for (i = 0; i < 4; i++) {
301 writel(0, &regs->laddr[i][LADDR_LOW]);
302 writel(0, &regs->laddr[i][LADDR_HIGH]);
303 /* Do not use MATCHx register */
304 writel(0, &regs->match[i]);
305 }
306
307 writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
308 writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
309
310 return 0;
311}
312
Michal Simek6889ca72015-11-30 14:14:56 +0100313static int zynq_phy_init(struct udevice *dev)
Michal Simek68cc3bd2015-11-30 13:54:43 +0100314{
315 int ret;
Michal Simek6889ca72015-11-30 14:14:56 +0100316 struct zynq_gem_priv *priv = dev_get_priv(dev);
317 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100318 const u32 supported = SUPPORTED_10baseT_Half |
319 SUPPORTED_10baseT_Full |
320 SUPPORTED_100baseT_Half |
321 SUPPORTED_100baseT_Full |
322 SUPPORTED_1000baseT_Half |
323 SUPPORTED_1000baseT_Full;
324
Michal Simekc8e29272015-11-30 13:58:36 +0100325 /* Enable only MDIO bus */
326 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
327
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530328 if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
329 ret = phy_detection(dev);
330 if (ret) {
331 printf("GEM PHY init failed\n");
332 return ret;
333 }
Michal Simek68cc3bd2015-11-30 13:54:43 +0100334 }
335
336 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
337 priv->interface);
Michal Simek90c6f2e2015-11-30 14:03:37 +0100338 if (!priv->phydev)
339 return -ENODEV;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100340
Nathan Rossi2c2ab8d2017-03-06 00:36:23 +1000341 priv->phydev->supported &= supported | ADVERTISED_Pause |
Michal Simek68cc3bd2015-11-30 13:54:43 +0100342 ADVERTISED_Asym_Pause;
343 priv->phydev->advertising = priv->phydev->supported;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100344
Dan Murphy20671a92016-05-02 15:45:57 -0500345 if (priv->phy_of_handle > 0)
Simon Glasse160f7d2017-01-17 16:52:55 -0700346 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
Dan Murphy20671a92016-05-02 15:45:57 -0500347
Michal Simek7a673f02016-05-18 14:37:23 +0200348 return phy_config(priv->phydev);
Michal Simek68cc3bd2015-11-30 13:54:43 +0100349}
350
Michal Simek6889ca72015-11-30 14:14:56 +0100351static int zynq_gem_init(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000352{
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530353 u32 i, nwconfig;
Michal Simek55259e72016-05-18 12:37:22 +0200354 int ret;
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800355 unsigned long clk_rate = 0;
Michal Simek6889ca72015-11-30 14:14:56 +0100356 struct zynq_gem_priv *priv = dev_get_priv(dev);
357 struct zynq_gem_regs *regs = priv->iobase;
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700358 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
359 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
Michal Simek185f7d92012-09-13 20:23:34 +0000360
Michal Simek05868752013-01-24 13:04:12 +0100361 if (!priv->init) {
362 /* Disable all interrupts */
363 writel(0xFFFFFFFF, &regs->idr);
Michal Simek185f7d92012-09-13 20:23:34 +0000364
Michal Simek05868752013-01-24 13:04:12 +0100365 /* Disable the receiver & transmitter */
366 writel(0, &regs->nwctrl);
367 writel(0, &regs->txsr);
368 writel(0, &regs->rxsr);
369 writel(0, &regs->phymntnc);
Michal Simek185f7d92012-09-13 20:23:34 +0000370
Michal Simek05868752013-01-24 13:04:12 +0100371 /* Clear the Hash registers for the mac address
372 * pointed by AddressPtr
373 */
374 writel(0x0, &regs->hashl);
375 /* Write bits [63:32] in TOP */
376 writel(0x0, &regs->hashh);
Michal Simek185f7d92012-09-13 20:23:34 +0000377
Michal Simek05868752013-01-24 13:04:12 +0100378 /* Clear all counters */
Michal Simek0ebf4042015-10-05 12:49:48 +0200379 for (i = 0; i < STAT_SIZE; i++)
Michal Simek05868752013-01-24 13:04:12 +0100380 readl(&regs->stat[i]);
Michal Simek185f7d92012-09-13 20:23:34 +0000381
Michal Simek05868752013-01-24 13:04:12 +0100382 /* Setup RxBD space */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530383 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000384
Michal Simek05868752013-01-24 13:04:12 +0100385 for (i = 0; i < RX_BUF; i++) {
386 priv->rx_bd[i].status = 0xF0000000;
387 priv->rx_bd[i].addr =
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530388 ((ulong)(priv->rxbuffers) +
Michal Simek185f7d92012-09-13 20:23:34 +0000389 (i * PKTSIZE_ALIGN));
Michal Simek05868752013-01-24 13:04:12 +0100390 }
391 /* WRAP bit to last BD */
392 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
393 /* Write RxBDs to IP */
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530394 writel((ulong)priv->rx_bd, &regs->rxqbase);
Michal Simek185f7d92012-09-13 20:23:34 +0000395
Michal Simek05868752013-01-24 13:04:12 +0100396 /* Setup for DMA Configuration register */
397 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
Michal Simek185f7d92012-09-13 20:23:34 +0000398
Michal Simek05868752013-01-24 13:04:12 +0100399 /* Setup for Network Control register, MDIO, Rx and Tx enable */
Michal Simek80243522012-10-15 14:01:23 +0200400 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
Michal Simek185f7d92012-09-13 20:23:34 +0000401
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700402 /* Disable the second priority queue */
403 dummy_tx_bd->addr = 0;
404 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
405 ZYNQ_GEM_TXBUF_LAST_MASK|
406 ZYNQ_GEM_TXBUF_USED_MASK;
407
408 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
409 ZYNQ_GEM_RXBUF_NEW_MASK;
410 dummy_rx_bd->status = 0;
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700411
412 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
413 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
414
Michal Simek05868752013-01-24 13:04:12 +0100415 priv->init++;
416 }
417
Michal Simek55259e72016-05-18 12:37:22 +0200418 ret = phy_startup(priv->phydev);
419 if (ret)
420 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000421
Michal Simek64a7ead2015-11-30 13:44:49 +0100422 if (!priv->phydev->link) {
423 printf("%s: No link.\n", priv->phydev->dev->name);
Michal Simek4ed4aa22013-11-12 14:25:29 +0100424 return -1;
425 }
426
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530427 nwconfig = ZYNQ_GEM_NWCFG_INIT;
428
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530429 /*
430 * Set SGMII enable PCS selection only if internal PCS/PMA
431 * core is used and interface is SGMII.
432 */
433 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
434 priv->int_pcs) {
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530435 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
436 ZYNQ_GEM_NWCFG_PCS_SEL;
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +0530437#ifdef CONFIG_ARM64
438 writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
439 &regs->pcscntrl);
440#endif
441 }
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530442
Michal Simek64a7ead2015-11-30 13:44:49 +0100443 switch (priv->phydev->speed) {
Michal Simek80243522012-10-15 14:01:23 +0200444 case SPEED_1000:
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530445 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
Michal Simek80243522012-10-15 14:01:23 +0200446 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800447 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
Michal Simek80243522012-10-15 14:01:23 +0200448 break;
449 case SPEED_100:
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530450 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
Michal Simek242b1542015-09-08 16:55:42 +0200451 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800452 clk_rate = ZYNQ_GEM_FREQUENCY_100;
Michal Simek80243522012-10-15 14:01:23 +0200453 break;
454 case SPEED_10:
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800455 clk_rate = ZYNQ_GEM_FREQUENCY_10;
Michal Simek80243522012-10-15 14:01:23 +0200456 break;
457 }
David Andrey01fbf312013-04-05 17:24:24 +0200458
Stefan Herbrechtsmeiereff55c52017-01-17 16:27:25 +0100459 ret = clk_set_rate(&priv->clk, clk_rate);
460 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
461 dev_err(dev, "failed to set tx clock rate\n");
462 return ret;
463 }
464
465 ret = clk_enable(&priv->clk);
466 if (ret && ret != -ENOSYS) {
467 dev_err(dev, "failed to enable tx clock\n");
468 return ret;
469 }
Michal Simek80243522012-10-15 14:01:23 +0200470
471 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
472 ZYNQ_GEM_NWCTRL_TXEN_MASK);
473
Michal Simek185f7d92012-09-13 20:23:34 +0000474 return 0;
475}
476
Michal Simek6889ca72015-11-30 14:14:56 +0100477static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
Michal Simek185f7d92012-09-13 20:23:34 +0000478{
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530479 u32 addr, size;
Michal Simek6889ca72015-11-30 14:14:56 +0100480 struct zynq_gem_priv *priv = dev_get_priv(dev);
481 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek23a598f2015-08-17 09:58:54 +0200482 struct emac_bd *current_bd = &priv->tx_bd[1];
Michal Simek185f7d92012-09-13 20:23:34 +0000483
Michal Simek185f7d92012-09-13 20:23:34 +0000484 /* Setup Tx BD */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530485 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000486
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530487 priv->tx_bd->addr = (ulong)ptr;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530488 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
Michal Simek23a598f2015-08-17 09:58:54 +0200489 ZYNQ_GEM_TXBUF_LAST_MASK;
490 /* Dummy descriptor to mark it as the last in descriptor chain */
491 current_bd->addr = 0x0;
492 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
493 ZYNQ_GEM_TXBUF_LAST_MASK|
494 ZYNQ_GEM_TXBUF_USED_MASK;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530495
Michal Simek45c07742015-08-17 09:50:09 +0200496 /* setup BD */
497 writel((ulong)priv->tx_bd, &regs->txqbase);
498
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530499 addr = (ulong) ptr;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530500 addr &= ~(ARCH_DMA_MINALIGN - 1);
501 size = roundup(len, ARCH_DMA_MINALIGN);
502 flush_dcache_range(addr, addr + size);
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530503
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530504 addr = (ulong)priv->rxbuffers;
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530505 addr &= ~(ARCH_DMA_MINALIGN - 1);
506 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
507 flush_dcache_range(addr, addr + size);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530508 barrier();
Michal Simek185f7d92012-09-13 20:23:34 +0000509
510 /* Start transmit */
511 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
512
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530513 /* Read TX BD status */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530514 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
515 printf("TX buffers exhausted in mid frame\n");
Michal Simek185f7d92012-09-13 20:23:34 +0000516
Michal Simeke4d23182015-08-17 09:57:46 +0200517 return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
Mateusz Kulikowskie7138b32016-01-23 11:54:33 +0100518 true, 20000, true);
Michal Simek185f7d92012-09-13 20:23:34 +0000519}
520
521/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
Michal Simek6889ca72015-11-30 14:14:56 +0100522static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek185f7d92012-09-13 20:23:34 +0000523{
524 int frame_len;
Michal Simek9d9211a2015-12-09 14:26:48 +0100525 u32 addr;
Michal Simek6889ca72015-11-30 14:14:56 +0100526 struct zynq_gem_priv *priv = dev_get_priv(dev);
Michal Simek185f7d92012-09-13 20:23:34 +0000527 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
Michal Simek185f7d92012-09-13 20:23:34 +0000528
529 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
Michal Simek9d9211a2015-12-09 14:26:48 +0100530 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000531
532 if (!(current_bd->status &
533 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
534 printf("GEM: SOF or EOF not set for last buffer received!\n");
Michal Simek9d9211a2015-12-09 14:26:48 +0100535 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000536 }
537
538 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
Michal Simek9d9211a2015-12-09 14:26:48 +0100539 if (!frame_len) {
540 printf("%s: Zero size packet?\n", __func__);
541 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000542 }
543
Michal Simek9d9211a2015-12-09 14:26:48 +0100544 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
545 addr &= ~(ARCH_DMA_MINALIGN - 1);
546 *packetp = (uchar *)(uintptr_t)addr;
547
548 return frame_len;
549}
550
551static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
552{
553 struct zynq_gem_priv *priv = dev_get_priv(dev);
554 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
555 struct emac_bd *first_bd;
556
557 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
558 priv->rx_first_buf = priv->rxbd_current;
559 } else {
560 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
561 current_bd->status = 0xF0000000; /* FIXME */
562 }
563
564 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
565 first_bd = &priv->rx_bd[priv->rx_first_buf];
566 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
567 first_bd->status = 0xF0000000;
568 }
569
570 if ((++priv->rxbd_current) >= RX_BUF)
571 priv->rxbd_current = 0;
572
Michal Simekda872d72015-12-09 14:16:32 +0100573 return 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000574}
575
Michal Simek6889ca72015-11-30 14:14:56 +0100576static void zynq_gem_halt(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000577{
Michal Simek6889ca72015-11-30 14:14:56 +0100578 struct zynq_gem_priv *priv = dev_get_priv(dev);
579 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000580
Michal Simek80243522012-10-15 14:01:23 +0200581 clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
582 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
Michal Simek185f7d92012-09-13 20:23:34 +0000583}
584
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600585__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
586{
587 return -ENOSYS;
588}
589
590static int zynq_gem_read_rom_mac(struct udevice *dev)
591{
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600592 struct eth_pdata *pdata = dev_get_platdata(dev);
593
Olliver Schinaglb2330892017-04-03 16:18:53 +0200594 if (!pdata)
595 return -ENOSYS;
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600596
Olliver Schinaglb2330892017-04-03 16:18:53 +0200597 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600598}
599
Michal Simek6889ca72015-11-30 14:14:56 +0100600static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
601 int devad, int reg)
Michal Simek185f7d92012-09-13 20:23:34 +0000602{
Michal Simek6889ca72015-11-30 14:14:56 +0100603 struct zynq_gem_priv *priv = bus->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000604 int ret;
Michal Simek6889ca72015-11-30 14:14:56 +0100605 u16 val;
Michal Simek185f7d92012-09-13 20:23:34 +0000606
Michal Simek6889ca72015-11-30 14:14:56 +0100607 ret = phyread(priv, addr, reg, &val);
608 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
609 return val;
Michal Simek185f7d92012-09-13 20:23:34 +0000610}
611
Michal Simek6889ca72015-11-30 14:14:56 +0100612static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
613 int reg, u16 value)
Michal Simek185f7d92012-09-13 20:23:34 +0000614{
Michal Simek6889ca72015-11-30 14:14:56 +0100615 struct zynq_gem_priv *priv = bus->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000616
Michal Simek6889ca72015-11-30 14:14:56 +0100617 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
618 return phywrite(priv, addr, reg, value);
Michal Simek185f7d92012-09-13 20:23:34 +0000619}
620
Michal Simek6889ca72015-11-30 14:14:56 +0100621static int zynq_gem_probe(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000622{
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530623 void *bd_space;
Michal Simek6889ca72015-11-30 14:14:56 +0100624 struct zynq_gem_priv *priv = dev_get_priv(dev);
625 int ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000626
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530627 /* Align rxbuffers to ARCH_DMA_MINALIGN */
628 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
629 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
630
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530631 /* Align bd_space to MMU_SECTION_SHIFT */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530632 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Michal Simek9ce1edc2015-04-15 13:31:28 +0200633 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
634 BD_SPACE, DCACHE_OFF);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530635
636 /* Initialize the bd spaces for tx and rx bd's */
637 priv->tx_bd = (struct emac_bd *)bd_space;
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530638 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530639
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530640 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
641 if (ret < 0) {
642 dev_err(dev, "failed to get clock\n");
643 return -EINVAL;
644 }
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530645
Michal Simek6889ca72015-11-30 14:14:56 +0100646 priv->bus = mdio_alloc();
647 priv->bus->read = zynq_gem_miiphy_read;
648 priv->bus->write = zynq_gem_miiphy_write;
649 priv->bus->priv = priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000650
Michal Simek6516e3f2016-12-08 10:25:44 +0100651 ret = mdio_register_seq(priv->bus, dev->seq);
Michal Simekc8e29272015-11-30 13:58:36 +0100652 if (ret)
653 return ret;
654
Siva Durga Prasad Paladugue76d2dc2016-03-30 12:29:49 +0530655 return zynq_phy_init(dev);
Michal Simek185f7d92012-09-13 20:23:34 +0000656}
Michal Simek6889ca72015-11-30 14:14:56 +0100657
658static int zynq_gem_remove(struct udevice *dev)
659{
660 struct zynq_gem_priv *priv = dev_get_priv(dev);
661
662 free(priv->phydev);
663 mdio_unregister(priv->bus);
664 mdio_free(priv->bus);
665
666 return 0;
667}
668
669static const struct eth_ops zynq_gem_ops = {
670 .start = zynq_gem_init,
671 .send = zynq_gem_send,
672 .recv = zynq_gem_recv,
Michal Simek9d9211a2015-12-09 14:26:48 +0100673 .free_pkt = zynq_gem_free_pkt,
Michal Simek6889ca72015-11-30 14:14:56 +0100674 .stop = zynq_gem_halt,
675 .write_hwaddr = zynq_gem_setup_mac,
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600676 .read_rom_hwaddr = zynq_gem_read_rom_mac,
Michal Simek6889ca72015-11-30 14:14:56 +0100677};
678
679static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
680{
681 struct eth_pdata *pdata = dev_get_platdata(dev);
682 struct zynq_gem_priv *priv = dev_get_priv(dev);
Simon Glasse160f7d2017-01-17 16:52:55 -0700683 int node = dev_of_offset(dev);
Michal Simek3cdb1452015-11-30 14:17:50 +0100684 const char *phy_mode;
Michal Simek6889ca72015-11-30 14:14:56 +0100685
Simon Glassa821c4a2017-05-17 17:18:05 -0600686 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Michal Simek6889ca72015-11-30 14:14:56 +0100687 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
688 /* Hardcode for now */
Michal Simekbcdfef72015-12-09 09:29:12 +0100689 priv->phyaddr = -1;
Michal Simek6889ca72015-11-30 14:14:56 +0100690
Simon Glasse160f7d2017-01-17 16:52:55 -0700691 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
692 "phy-handle");
Dan Murphy20671a92016-05-02 15:45:57 -0500693 if (priv->phy_of_handle > 0)
694 priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
695 priv->phy_of_handle, "reg", -1);
Michal Simek6889ca72015-11-30 14:14:56 +0100696
Simon Glasse160f7d2017-01-17 16:52:55 -0700697 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
Michal Simek3cdb1452015-11-30 14:17:50 +0100698 if (phy_mode)
699 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
700 if (pdata->phy_interface == -1) {
701 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
702 return -EINVAL;
703 }
704 priv->interface = pdata->phy_interface;
705
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530706 priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
707 "is-internal-pcspma");
708
Michal Simek15a2acd2016-11-16 08:41:01 +0100709 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
Michal Simek3cdb1452015-11-30 14:17:50 +0100710 priv->phyaddr, phy_string_for_interface(priv->interface));
Michal Simek6889ca72015-11-30 14:14:56 +0100711
712 return 0;
713}
714
715static const struct udevice_id zynq_gem_ids[] = {
716 { .compatible = "cdns,zynqmp-gem" },
717 { .compatible = "cdns,zynq-gem" },
718 { .compatible = "cdns,gem" },
719 { }
720};
721
722U_BOOT_DRIVER(zynq_gem) = {
723 .name = "zynq_gem",
724 .id = UCLASS_ETH,
725 .of_match = zynq_gem_ids,
726 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
727 .probe = zynq_gem_probe,
728 .remove = zynq_gem_remove,
729 .ops = &zynq_gem_ops,
730 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
731 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
732};