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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 566ce04de4a2b4c66be8e13751dbb0bfe80117b3 / . / arch / mips / Kconfig
blob: f113b91de70857163bba8f5e8887f523162c28f7 [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]1menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]5 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +0100[diff] [blame]7config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +0100[diff] [blame]8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +0100[diff] [blame]10
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]11choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500[diff] [blame]13 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]14
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +0100[diff] [blame]21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]23
24config TARGET_MALTA
25 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +0100[diff] [blame]26 select DM
27 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +0000[diff] [blame]28 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +0100[diff] [blame^]29 select MIPS_CM
30 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +0100[diff] [blame]31 select OF_CONTROL
32 select OF_ISA_BUS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]33 select SUPPORTS_BIG_ENDIAN
34 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]35 select SUPPORTS_CPU_MIPS32_R1
36 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +0100[diff] [blame]37 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +0100[diff] [blame]38 select SUPPORTS_CPU_MIPS64_R1
39 select SUPPORTS_CPU_MIPS64_R2
40 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100[diff] [blame]41 select SWAP_IO_SPACE
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100[diff] [blame]42 select MIPS_L1_CACHE_SHIFT_6
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]43
44config TARGET_VCT
45 bool "Support vct"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]46 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]47 select SUPPORTS_CPU_MIPS32_R1
48 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]49 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]50
51config TARGET_DBAU1X00
52 bool "Support dbau1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]53 select SUPPORTS_BIG_ENDIAN
54 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]55 select SUPPORTS_CPU_MIPS32_R1
56 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]57 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]58 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]59
60config TARGET_PB1X00
61 bool "Support pb1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]62 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]63 select SUPPORTS_CPU_MIPS32_R1
64 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]65 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]66 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]67
Wills Wang1d3d0f12016-03-16 16:59:52 +0800[diff] [blame]68config ARCH_ATH79
69 bool "Support QCA/Atheros ath79"
70 select OF_CONTROL
71 select DM
72
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530[diff] [blame]73config MACH_PIC32
74 bool "Support Microchip PIC32"
75 select OF_CONTROL
76 select DM
77
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100[diff] [blame]78config TARGET_XILFPGA
79 bool "Support Imagination Xilfpga"
80 select OF_CONTROL
81 select DM
82 select DM_SERIAL
83 select DM_GPIO
84 select DM_ETH
85 select SUPPORTS_LITTLE_ENDIAN
86 select SUPPORTS_CPU_MIPS32_R1
87 select SUPPORTS_CPU_MIPS32_R2
88 select MIPS_L1_CACHE_SHIFT_4
89 help
90 This supports IMGTEC MIPSfpga platform
91
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]92endchoice
93
94source "board/dbau1x00/Kconfig"
95source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100[diff] [blame]96source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]97source "board/micronas/vct/Kconfig"
98source "board/pb1x00/Kconfig"
99source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800[diff] [blame]100source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530[diff] [blame]101source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]102
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]103if MIPS
104
105choice
106 prompt "Endianness selection"
107 help
108 Some MIPS boards can be configured for either little or big endian
109 byte order. These modes require different U-Boot images. In general there
110 is one preferred byteorder for a particular system but some systems are
111 just as commonly used in the one or the other endianness.
112
113config SYS_BIG_ENDIAN
114 bool "Big endian"
115 depends on SUPPORTS_BIG_ENDIAN
116
117config SYS_LITTLE_ENDIAN
118 bool "Little endian"
119 depends on SUPPORTS_LITTLE_ENDIAN
120
121endchoice
122
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]123choice
124 prompt "CPU selection"
125 default CPU_MIPS32_R2
126
127config CPU_MIPS32_R1
128 bool "MIPS32 Release 1"
129 depends on SUPPORTS_CPU_MIPS32_R1
130 select 32BIT
131 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]132 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]133 MIPS32 architecture.
134
135config CPU_MIPS32_R2
136 bool "MIPS32 Release 2"
137 depends on SUPPORTS_CPU_MIPS32_R2
138 select 32BIT
139 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]140 Choose this option to build an U-Boot for release 2 through 5 of the
141 MIPS32 architecture.
142
143config CPU_MIPS32_R6
144 bool "MIPS32 Release 6"
145 depends on SUPPORTS_CPU_MIPS32_R6
146 select 32BIT
147 help
148 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]149 MIPS32 architecture.
150
151config CPU_MIPS64_R1
152 bool "MIPS64 Release 1"
153 depends on SUPPORTS_CPU_MIPS64_R1
154 select 64BIT
155 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]156 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]157 MIPS64 architecture.
158
159config CPU_MIPS64_R2
160 bool "MIPS64 Release 2"
161 depends on SUPPORTS_CPU_MIPS64_R2
162 select 64BIT
163 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]164 Choose this option to build a kernel for release 2 through 5 of the
165 MIPS64 architecture.
166
167config CPU_MIPS64_R6
168 bool "MIPS64 Release 6"
169 depends on SUPPORTS_CPU_MIPS64_R6
170 select 64BIT
171 help
172 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]173 MIPS64 architecture.
174
175endchoice
176
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100[diff] [blame]177menu "OS boot interface"
178
179config MIPS_BOOT_CMDLINE_LEGACY
180 bool "Hand over legacy command line to Linux kernel"
181 default y
182 help
183 Enable this option if you want U-Boot to hand over the Yamon-style
184 command line to the kernel. All bootargs will be prepared as argc/argv
185 compatible list. The argument count (argc) is stored in register $a0.
186 The address of the argument list (argv) is stored in register $a1.
187
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100[diff] [blame]188config MIPS_BOOT_ENV_LEGACY
189 bool "Hand over legacy environment to Linux kernel"
190 default y
191 help
192 Enable this option if you want U-Boot to hand over the Yamon-style
193 environment to the kernel. Information like memory size, initrd
194 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400[diff] [blame]195 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100[diff] [blame]196
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]197config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100[diff] [blame]198 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]199 default n
200 help
201 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100[diff] [blame]202 device tree to the kernel. According to UHI register $a0 will be set
203 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100[diff] [blame]204
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100[diff] [blame]205endmenu
206
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]207config SUPPORTS_BIG_ENDIAN
208 bool
209
210config SUPPORTS_LITTLE_ENDIAN
211 bool
212
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]213config SUPPORTS_CPU_MIPS32_R1
214 bool
215
216config SUPPORTS_CPU_MIPS32_R2
217 bool
218
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]219config SUPPORTS_CPU_MIPS32_R6
220 bool
221
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]222config SUPPORTS_CPU_MIPS64_R1
223 bool
224
225config SUPPORTS_CPU_MIPS64_R2
226 bool
227
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]228config SUPPORTS_CPU_MIPS64_R6
229 bool
230
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]231config CPU_MIPS32
232 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]233 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]234
235config CPU_MIPS64
236 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100[diff] [blame]237 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100[diff] [blame]238
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100[diff] [blame]239config MIPS_TUNE_4KC
240 bool
241
242config MIPS_TUNE_14KC
243 bool
244
245config MIPS_TUNE_24KC
246 bool
247
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200[diff] [blame]248config MIPS_TUNE_34KC
249 bool
250
Marek Vasut0a0a9582016-05-06 20:10:33 +0200[diff] [blame]251config MIPS_TUNE_74KC
252 bool
253
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100[diff] [blame]254config 32BIT
255 bool
256
257config 64BIT
258 bool
259
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100[diff] [blame]260config SWAP_IO_SPACE
261 bool
262
Paul Burtondd7c7202015-01-29 01:28:02 +0000[diff] [blame]263config SYS_MIPS_CACHE_INIT_RAM_LOAD
264 bool
265
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]266config SYS_DCACHE_SIZE
267 int
268 default 0
269 help
270 The total size of the L1 Dcache, if known at compile time.
271
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]272config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100[diff] [blame]273 int
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]274 default 0
275 help
276 The size of L1 Dcache lines, if known at compile time.
277
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]278config SYS_ICACHE_SIZE
279 int
280 default 0
281 help
282 The total size of the L1 ICache, if known at compile time.
283
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]284config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]285 int
286 default 0
287 help
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]288 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]289
290config SYS_CACHE_SIZE_AUTO
291 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100[diff] [blame]292 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100[diff] [blame]293 help
294 Select this (or let it be auto-selected by not defining any cache
295 sizes) in order to allow U-Boot to automatically detect the sizes
296 of caches at runtime. This has a small cost in code size & runtime
297 so if you know the cache configuration for your system at compile
298 time it would be beneficial to configure it.
299
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100[diff] [blame]300config MIPS_L1_CACHE_SHIFT_4
301 bool
302
303config MIPS_L1_CACHE_SHIFT_5
304 bool
305
306config MIPS_L1_CACHE_SHIFT_6
307 bool
308
309config MIPS_L1_CACHE_SHIFT_7
310 bool
311
312config MIPS_L1_CACHE_SHIFT
313 int
314 default "7" if MIPS_L1_CACHE_SHIFT_7
315 default "6" if MIPS_L1_CACHE_SHIFT_6
316 default "5" if MIPS_L1_CACHE_SHIFT_5
317 default "4" if MIPS_L1_CACHE_SHIFT_4
318 default "5"
319
Paul Burton4baa0ab2016-09-21 11:18:54 +0100[diff] [blame]320config MIPS_L2_CACHE
321 bool
322 help
323 Select this if your system includes an L2 cache and you want U-Boot
324 to initialise & maintain it.
325
Paul Burton05e34252016-01-29 13:54:52 +0000[diff] [blame]326config DYNAMIC_IO_PORT_BASE
327 bool
328
Paul Burtonb2b135d2016-09-21 11:18:53 +0100[diff] [blame]329config MIPS_CM
330 bool
331 help
332 Select this if your system contains a MIPS Coherence Manager and you
333 wish U-Boot to configure it or make use of it to retrieve system
334 information such as cache configuration.
335
336config MIPS_CM_BASE
337 hex
338 default 0x1fbf8000
339 help
340 The physical base address at which to map the MIPS Coherence Manager
341 Global Configuration Registers (GCRs). This should be set such that
342 the GCRs occupy a region of the physical address space which is
343 otherwise unused, or at minimum that software doesn't need to access.
344
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100[diff] [blame]345endif
346
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]347endmenu