blob: 2f3d40c2277ed892fc3af0ed19ee4e2d1081dd24 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass6854f872014-11-14 20:56:33 -07002/*
3 * Copyright (C) 2014 Google, Inc
4 *
5 * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
6 *
7 * Modifications are:
8 * Copyright (C) 2003-2004 Linux Networx
9 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
10 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
11 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
12 * Copyright (C) 2005-2006 Tyan
13 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
14 * Copyright (C) 2005-2009 coresystems GmbH
15 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
16 *
17 * PCI Bus Services, see include/linux/pci.h for further explanation.
18 *
19 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
20 * David Mosberger-Tang
21 *
22 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
Simon Glass6854f872014-11-14 20:56:33 -070023 */
24
25#include <common.h>
26#include <bios_emul.h>
Simon Glass52f24232020-05-10 11:40:00 -060027#include <bootstage.h>
Simon Glass3f4e1e82015-11-29 13:17:57 -070028#include <dm.h>
Simon Glass6854f872014-11-14 20:56:33 -070029#include <errno.h>
Simon Glass35a3f872019-12-28 10:44:56 -070030#include <init.h>
Simon Glass6854f872014-11-14 20:56:33 -070031#include <malloc.h>
32#include <pci.h>
33#include <pci_rom.h>
34#include <vbe.h>
Simon Glassee87ee82016-10-05 20:42:17 -060035#include <video.h>
Simon Glass6854f872014-11-14 20:56:33 -070036#include <video_fb.h>
Simon Glass3cabcf92020-04-08 16:57:35 -060037#include <acpi/acpi_s3.h>
Bin Menga4520022015-07-06 16:31:36 +080038#include <linux/screen_info.h>
Simon Glass6854f872014-11-14 20:56:33 -070039
Bin Meng68769eb2017-04-21 07:24:46 -070040DECLARE_GLOBAL_DATA_PTR;
Bin Meng68769eb2017-04-21 07:24:46 -070041
Simon Glass3f4e1e82015-11-29 13:17:57 -070042__weak bool board_should_run_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070043{
Bin Meng68769eb2017-04-21 07:24:46 -070044#if defined(CONFIG_X86) && defined(CONFIG_HAVE_ACPI_RESUME)
45 if (gd->arch.prev_sleep_state == ACPI_S3) {
46 if (IS_ENABLED(CONFIG_S3_VGA_ROM_RUN))
47 return true;
48 else
49 return false;
50 }
51#endif
52
Simon Glass6854f872014-11-14 20:56:33 -070053 return true;
54}
55
Bin Mengf698baa2016-06-14 02:02:40 -070056__weak bool board_should_load_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070057{
Bin Mengc0aea6b2016-06-14 02:02:39 -070058 return true;
Simon Glass6854f872014-11-14 20:56:33 -070059}
60
61__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
62{
63 return vendev;
64}
65
Simon Glass3f4e1e82015-11-29 13:17:57 -070066static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
Simon Glass6854f872014-11-14 20:56:33 -070067{
Simon Glass3f4e1e82015-11-29 13:17:57 -070068 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Simon Glass6854f872014-11-14 20:56:33 -070069 struct pci_rom_header *rom_header;
70 struct pci_rom_data *rom_data;
Simon Glass40305242014-12-29 19:32:23 -070071 u16 rom_vendor, rom_device;
Bin Mengd57c2f22015-04-24 15:48:03 +080072 u32 rom_class;
Simon Glass6854f872014-11-14 20:56:33 -070073 u32 vendev;
74 u32 mapped_vendev;
75 u32 rom_address;
76
Simon Glass3f4e1e82015-11-29 13:17:57 -070077 vendev = pplat->vendor << 16 | pplat->device;
Simon Glass6854f872014-11-14 20:56:33 -070078 mapped_vendev = board_map_oprom_vendev(vendev);
79 if (vendev != mapped_vendev)
80 debug("Device ID mapped to %#08x\n", mapped_vendev);
81
Bin Meng786a08e2015-07-06 16:31:33 +080082#ifdef CONFIG_VGA_BIOS_ADDR
83 rom_address = CONFIG_VGA_BIOS_ADDR;
Simon Glass6854f872014-11-14 20:56:33 -070084#else
Simon Glass4a2708a2015-01-14 21:37:04 -070085
Simon Glass3f4e1e82015-11-29 13:17:57 -070086 dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
Simon Glass6854f872014-11-14 20:56:33 -070087 if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
88 debug("%s: rom_address=%x\n", __func__, rom_address);
89 return -ENOENT;
90 }
91
92 /* Enable expansion ROM address decoding. */
Simon Glass3f4e1e82015-11-29 13:17:57 -070093 dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
94 rom_address | PCI_ROM_ADDRESS_ENABLE);
Simon Glass6854f872014-11-14 20:56:33 -070095#endif
96 debug("Option ROM address %x\n", rom_address);
Minghuan Lianef2d17f2015-01-22 13:21:55 +080097 rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
Simon Glass6854f872014-11-14 20:56:33 -070098
99 debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700100 le16_to_cpu(rom_header->signature),
101 rom_header->size * 512, le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700102
Simon Glass40305242014-12-29 19:32:23 -0700103 if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
Simon Glass6854f872014-11-14 20:56:33 -0700104 printf("Incorrect expansion ROM header signature %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700105 le16_to_cpu(rom_header->signature));
Bin Mengf110da92015-07-08 13:06:41 +0800106#ifndef CONFIG_VGA_BIOS_ADDR
107 /* Disable expansion ROM address decoding */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700108 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
Bin Mengf110da92015-07-08 13:06:41 +0800109#endif
Simon Glass6854f872014-11-14 20:56:33 -0700110 return -EINVAL;
111 }
112
Simon Glass40305242014-12-29 19:32:23 -0700113 rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
114 rom_vendor = le16_to_cpu(rom_data->vendor);
115 rom_device = le16_to_cpu(rom_data->device);
Simon Glass6854f872014-11-14 20:56:33 -0700116
117 debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
Simon Glass40305242014-12-29 19:32:23 -0700118 rom_vendor, rom_device);
Simon Glass6854f872014-11-14 20:56:33 -0700119
120 /* If the device id is mapped, a mismatch is expected */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700121 if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
Simon Glass6854f872014-11-14 20:56:33 -0700122 (vendev == mapped_vendev)) {
123 printf("ID mismatch: vendor ID %04x, device ID %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700124 rom_vendor, rom_device);
Simon Glassc5caba02014-12-29 19:32:27 -0700125 /* Continue anyway */
Simon Glass6854f872014-11-14 20:56:33 -0700126 }
127
Bin Mengd57c2f22015-04-24 15:48:03 +0800128 rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
129 debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
130 rom_class, rom_data->type);
Simon Glass6854f872014-11-14 20:56:33 -0700131
Simon Glass3f4e1e82015-11-29 13:17:57 -0700132 if (pplat->class != rom_class) {
Bin Mengd57c2f22015-04-24 15:48:03 +0800133 debug("Class Code mismatch ROM %06x, dev %06x\n",
Simon Glass3f4e1e82015-11-29 13:17:57 -0700134 rom_class, pplat->class);
Simon Glass6854f872014-11-14 20:56:33 -0700135 }
136 *hdrp = rom_header;
137
138 return 0;
139}
140
Simon Glassd830b152016-01-15 05:23:22 -0700141/**
142 * pci_rom_load() - Load a ROM image and return a pointer to it
143 *
144 * @rom_header: Pointer to ROM image
145 * @ram_headerp: Returns a pointer to the image in RAM
146 * @allocedp: Returns true if @ram_headerp was allocated and needs
147 * to be freed
148 * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of
149 * the error state. Even if this function returns an error, it may have
150 * allocated memory.
151 */
152static int pci_rom_load(struct pci_rom_header *rom_header,
153 struct pci_rom_header **ram_headerp, bool *allocedp)
Simon Glass6854f872014-11-14 20:56:33 -0700154{
155 struct pci_rom_data *rom_data;
156 unsigned int rom_size;
157 unsigned int image_size = 0;
158 void *target;
159
Simon Glassd830b152016-01-15 05:23:22 -0700160 *allocedp = false;
Simon Glass6854f872014-11-14 20:56:33 -0700161 do {
162 /* Get next image, until we see an x86 version */
163 rom_header = (struct pci_rom_header *)((void *)rom_header +
164 image_size);
165
166 rom_data = (struct pci_rom_data *)((void *)rom_header +
Simon Glass40305242014-12-29 19:32:23 -0700167 le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700168
Simon Glass40305242014-12-29 19:32:23 -0700169 image_size = le16_to_cpu(rom_data->ilen) * 512;
170 } while ((rom_data->type != 0) && (rom_data->indicator == 0));
Simon Glass6854f872014-11-14 20:56:33 -0700171
172 if (rom_data->type != 0)
173 return -EACCES;
174
175 rom_size = rom_header->size * 512;
176
Simon Glassbdc88d42014-12-29 19:32:24 -0700177#ifdef PCI_VGA_RAM_IMAGE_START
Simon Glass6854f872014-11-14 20:56:33 -0700178 target = (void *)PCI_VGA_RAM_IMAGE_START;
Simon Glassbdc88d42014-12-29 19:32:24 -0700179#else
180 target = (void *)malloc(rom_size);
181 if (!target)
182 return -ENOMEM;
Simon Glassd830b152016-01-15 05:23:22 -0700183 *allocedp = true;
Simon Glassbdc88d42014-12-29 19:32:24 -0700184#endif
Simon Glass6854f872014-11-14 20:56:33 -0700185 if (target != rom_header) {
Simon Glassfba7eac2015-01-01 16:18:01 -0700186 ulong start = get_timer(0);
187
Simon Glass6854f872014-11-14 20:56:33 -0700188 debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
189 rom_header, target, rom_size);
190 memcpy(target, rom_header, rom_size);
191 if (memcmp(target, rom_header, rom_size)) {
192 printf("VGA ROM copy failed\n");
193 return -EFAULT;
194 }
Simon Glassfba7eac2015-01-01 16:18:01 -0700195 debug("Copy took %lums\n", get_timer(start));
Simon Glass6854f872014-11-14 20:56:33 -0700196 }
197 *ram_headerp = target;
198
199 return 0;
200}
201
Bin Meng153e1dd2015-08-13 00:29:16 -0700202struct vbe_mode_info mode_info;
Simon Glass6854f872014-11-14 20:56:33 -0700203
Bin Menga4520022015-07-06 16:31:36 +0800204void setup_video(struct screen_info *screen_info)
205{
Bin Menga4520022015-07-06 16:31:36 +0800206 struct vesa_mode_info *vesa = &mode_info.vesa;
207
Bin Meng1e7a0472015-07-30 03:49:13 -0700208 /* Sanity test on VESA parameters */
209 if (!vesa->x_resolution || !vesa->y_resolution)
210 return;
211
Bin Menga4520022015-07-06 16:31:36 +0800212 screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
213
214 screen_info->lfb_width = vesa->x_resolution;
215 screen_info->lfb_height = vesa->y_resolution;
216 screen_info->lfb_depth = vesa->bits_per_pixel;
217 screen_info->lfb_linelength = vesa->bytes_per_scanline;
218 screen_info->lfb_base = vesa->phys_base_ptr;
219 screen_info->lfb_size =
220 ALIGN(screen_info->lfb_linelength * screen_info->lfb_height,
221 65536);
222 screen_info->lfb_size >>= 16;
223 screen_info->red_size = vesa->red_mask_size;
224 screen_info->red_pos = vesa->red_mask_pos;
225 screen_info->green_size = vesa->green_mask_size;
226 screen_info->green_pos = vesa->green_mask_pos;
227 screen_info->blue_size = vesa->blue_mask_size;
228 screen_info->blue_pos = vesa->blue_mask_pos;
229 screen_info->rsvd_size = vesa->reserved_mask_size;
230 screen_info->rsvd_pos = vesa->reserved_mask_pos;
Bin Menga4520022015-07-06 16:31:36 +0800231}
232
Simon Glass3f4e1e82015-11-29 13:17:57 -0700233int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
234 int exec_method)
Simon Glass6854f872014-11-14 20:56:33 -0700235{
Simon Glass3f4e1e82015-11-29 13:17:57 -0700236 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Andreas Bießmanned488992016-02-16 23:29:31 +0100237 struct pci_rom_header *rom = NULL, *ram = NULL;
Simon Glass6854f872014-11-14 20:56:33 -0700238 int vesa_mode = -1;
Simon Glassd830b152016-01-15 05:23:22 -0700239 bool emulate, alloced;
Simon Glass6854f872014-11-14 20:56:33 -0700240 int ret;
241
242 /* Only execute VGA ROMs */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700243 if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
244 debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
Simon Glass6854f872014-11-14 20:56:33 -0700245 PCI_CLASS_DISPLAY_VGA);
246 return -ENODEV;
247 }
248
Bin Mengf698baa2016-06-14 02:02:40 -0700249 if (!board_should_load_oprom(dev))
Simon Glass595aac92018-10-01 12:22:44 -0600250 return log_msg_ret("Should not load OPROM", -ENXIO);
Simon Glass6854f872014-11-14 20:56:33 -0700251
Simon Glass3f4e1e82015-11-29 13:17:57 -0700252 ret = pci_rom_probe(dev, &rom);
Simon Glass6854f872014-11-14 20:56:33 -0700253 if (ret)
254 return ret;
255
Simon Glassd830b152016-01-15 05:23:22 -0700256 ret = pci_rom_load(rom, &ram, &alloced);
Simon Glass6854f872014-11-14 20:56:33 -0700257 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700258 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700259
Simon Glassd830b152016-01-15 05:23:22 -0700260 if (!board_should_run_oprom(dev)) {
261 ret = -ENXIO;
262 goto err;
263 }
Simon Glass6854f872014-11-14 20:56:33 -0700264
265#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
266 defined(CONFIG_FRAMEBUFFER_VESA_MODE)
267 vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
268#endif
Simon Glass9a99caf2015-01-01 16:18:05 -0700269 debug("Selected vesa mode %#x\n", vesa_mode);
Simon Glassbc17d8f2015-01-27 22:13:34 -0700270
271 if (exec_method & PCI_ROM_USE_NATIVE) {
272#ifdef CONFIG_X86
273 emulate = false;
274#else
275 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
276 printf("BIOS native execution is only available on x86\n");
Simon Glassd830b152016-01-15 05:23:22 -0700277 ret = -ENOSYS;
278 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700279 }
280 emulate = true;
281#endif
282 } else {
283#ifdef CONFIG_BIOSEMU
284 emulate = true;
285#else
286 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
287 printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
Simon Glassd830b152016-01-15 05:23:22 -0700288 ret = -ENOSYS;
289 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700290 }
291 emulate = false;
292#endif
293 }
294
Simon Glass6854f872014-11-14 20:56:33 -0700295 if (emulate) {
296#ifdef CONFIG_BIOSEMU
297 BE_VGAInfo *info;
298
Simon Glass72826722016-01-17 16:11:09 -0700299 ret = biosemu_setup(dev, &info);
Simon Glass6854f872014-11-14 20:56:33 -0700300 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700301 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700302 biosemu_set_interrupt_handler(0x15, int15_handler);
Simon Glass72826722016-01-17 16:11:09 -0700303 ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
304 true, vesa_mode, &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700305 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700306 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700307#endif
308 } else {
Simon Glass6c456512019-04-25 21:59:08 -0600309#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
Simon Glass6854f872014-11-14 20:56:33 -0700310 bios_set_interrupt_handler(0x15, int15_handler);
311
Simon Glass8beb0bd2015-11-29 13:17:58 -0700312 bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
313 &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700314#endif
315 }
Simon Glass9a99caf2015-01-01 16:18:05 -0700316 debug("Final vesa mode %#x\n", mode_info.video_mode);
Simon Glassd830b152016-01-15 05:23:22 -0700317 ret = 0;
Simon Glass6854f872014-11-14 20:56:33 -0700318
Simon Glassd830b152016-01-15 05:23:22 -0700319err:
320 if (alloced)
321 free(ram);
322 return ret;
Simon Glass6854f872014-11-14 20:56:33 -0700323}
Simon Glassee87ee82016-10-05 20:42:17 -0600324
325#ifdef CONFIG_DM_VIDEO
Bin Meng5f6ad022016-10-09 04:14:15 -0700326int vbe_setup_video_priv(struct vesa_mode_info *vesa,
327 struct video_priv *uc_priv,
328 struct video_uc_platdata *plat)
Simon Glassee87ee82016-10-05 20:42:17 -0600329{
330 if (!vesa->x_resolution)
Simon Glass595aac92018-10-01 12:22:44 -0600331 return log_msg_ret("No x resolution", -ENXIO);
Simon Glassee87ee82016-10-05 20:42:17 -0600332 uc_priv->xsize = vesa->x_resolution;
333 uc_priv->ysize = vesa->y_resolution;
Simon Glass06696eb2018-11-29 15:08:52 -0700334 uc_priv->line_length = vesa->bytes_per_scanline;
Simon Glassee87ee82016-10-05 20:42:17 -0600335 switch (vesa->bits_per_pixel) {
336 case 32:
337 case 24:
338 uc_priv->bpix = VIDEO_BPP32;
339 break;
340 case 16:
341 uc_priv->bpix = VIDEO_BPP16;
342 break;
343 default:
344 return -EPROTONOSUPPORT;
345 }
346 plat->base = vesa->phys_base_ptr;
347 plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
348
349 return 0;
350}
351
352int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
353{
354 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
355 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
356 int ret;
357
358 /* If we are running from EFI or coreboot, this can't work */
Bin Mengf0920e42016-10-09 04:14:12 -0700359 if (!ll_boot_init()) {
360 printf("Not available (previous bootloader prevents it)\n");
Simon Glassee87ee82016-10-05 20:42:17 -0600361 return -EPERM;
Bin Mengf0920e42016-10-09 04:14:12 -0700362 }
Simon Glassee87ee82016-10-05 20:42:17 -0600363 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
364 ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
365 PCI_ROM_ALLOW_FALLBACK);
366 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
367 if (ret) {
368 debug("failed to run video BIOS: %d\n", ret);
369 return ret;
370 }
371
372 ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
373 if (ret) {
374 debug("No video mode configured\n");
375 return ret;
376 }
377
Bin Meng61130932018-04-11 22:02:18 -0700378 printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
Bin Mengf0920e42016-10-09 04:14:12 -0700379 mode_info.vesa.bits_per_pixel);
380
Simon Glassee87ee82016-10-05 20:42:17 -0600381 return 0;
382}
383#endif