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Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Sunc0c32af2018-01-29 09:44:35 -08002 * Copyright 2008-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP Semiconductor
Kumar Gala58e5e9a2008-08-26 15:01:29 -05004 *
Tom Riniac727572018-02-14 21:34:05 -05005 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala58e5e9a2008-08-26 15:01:29 -05006 */
7
8/*
Shengzhou Liu02fb2762016-11-21 11:36:48 +08009 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
Kumar Gala58e5e9a2008-08-26 15:01:29 -050010 * Based on code from spd_sdram.c
11 * Author: James Yang [at freescale.com]
12 */
13
14#include <common.h>
York Sun5614e712013-09-30 09:22:09 -070015#include <fsl_ddr_sdram.h>
Shengzhou Liu02fb2762016-11-21 11:36:48 +080016#include <fsl_errata.h>
York Sun5614e712013-09-30 09:22:09 -070017#include <fsl_ddr.h>
York Sun9a17eb52013-11-18 10:29:32 -080018#include <fsl_immap.h>
York Sun5614e712013-09-30 09:22:09 -070019#include <asm/io.h>
Simon Glass457e51c2017-05-17 08:23:10 -060020#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
21 defined(CONFIG_ARM)
Simon Glass6e2941d2017-05-17 08:23:06 -060022#include <asm/arch/clock.h>
23#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -050024
Kumar Gala58e5e9a2008-08-26 15:01:29 -050025/*
26 * Determine Rtt value.
27 *
28 * This should likely be either board or controller specific.
29 *
Dave Liuc360cea2009-03-14 12:48:30 +080030 * Rtt(nominal) - DDR2:
Kumar Gala58e5e9a2008-08-26 15:01:29 -050031 * 0 = Rtt disabled
32 * 1 = 75 ohm
33 * 2 = 150 ohm
34 * 3 = 50 ohm
Dave Liuc360cea2009-03-14 12:48:30 +080035 * Rtt(nominal) - DDR3:
36 * 0 = Rtt disabled
37 * 1 = 60 ohm
38 * 2 = 120 ohm
39 * 3 = 40 ohm
40 * 4 = 20 ohm
41 * 5 = 30 ohm
Kumar Gala58e5e9a2008-08-26 15:01:29 -050042 *
43 * FIXME: Apparently 8641 needs a value of 2
44 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
45 *
46 * FIXME: There was some effort down this line earlier:
47 *
48 * unsigned int i;
49 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
50 * if (popts->dimmslot[i].num_valid_cs
51 * && (popts->cs_local_opts[2*i].odt_rd_cfg
52 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
53 * rtt = 2;
54 * break;
55 * }
56 * }
57 */
58static inline int fsl_ddr_get_rtt(void)
59{
60 int rtt;
61
York Sun5614e712013-09-30 09:22:09 -070062#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050063 rtt = 0;
York Sun5614e712013-09-30 09:22:09 -070064#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050065 rtt = 3;
66#else
Dave Liuc360cea2009-03-14 12:48:30 +080067 rtt = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -050068#endif
69
70 return rtt;
71}
72
York Sun34e026f2014-03-27 17:54:47 -070073#ifdef CONFIG_SYS_FSL_DDR4
74/*
75 * compute CAS write latency according to DDR4 spec
76 * CWL = 9 for <= 1600MT/s
77 * 10 for <= 1866MT/s
78 * 11 for <= 2133MT/s
79 * 12 for <= 2400MT/s
80 * 14 for <= 2667MT/s
81 * 16 for <= 2933MT/s
82 * 18 for higher
83 */
York Sun03e664d2015-01-06 13:18:50 -080084static inline unsigned int compute_cas_write_latency(
85 const unsigned int ctrl_num)
York Sun34e026f2014-03-27 17:54:47 -070086{
87 unsigned int cwl;
York Sun03e664d2015-01-06 13:18:50 -080088 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sun34e026f2014-03-27 17:54:47 -070089 if (mclk_ps >= 1250)
90 cwl = 9;
91 else if (mclk_ps >= 1070)
92 cwl = 10;
93 else if (mclk_ps >= 935)
94 cwl = 11;
95 else if (mclk_ps >= 833)
96 cwl = 12;
97 else if (mclk_ps >= 750)
98 cwl = 14;
99 else if (mclk_ps >= 681)
100 cwl = 16;
101 else
102 cwl = 18;
103
104 return cwl;
105}
106#else
Dave Liuc360cea2009-03-14 12:48:30 +0800107/*
108 * compute the CAS write latency according to DDR3 spec
109 * CWL = 5 if tCK >= 2.5ns
110 * 6 if 2.5ns > tCK >= 1.875ns
111 * 7 if 1.875ns > tCK >= 1.5ns
112 * 8 if 1.5ns > tCK >= 1.25ns
York Sun2bba85f2011-08-24 09:40:25 -0700113 * 9 if 1.25ns > tCK >= 1.07ns
114 * 10 if 1.07ns > tCK >= 0.935ns
115 * 11 if 0.935ns > tCK >= 0.833ns
116 * 12 if 0.833ns > tCK >= 0.75ns
Dave Liuc360cea2009-03-14 12:48:30 +0800117 */
York Sun03e664d2015-01-06 13:18:50 -0800118static inline unsigned int compute_cas_write_latency(
119 const unsigned int ctrl_num)
Dave Liuc360cea2009-03-14 12:48:30 +0800120{
121 unsigned int cwl;
York Sun03e664d2015-01-06 13:18:50 -0800122 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
Dave Liuc360cea2009-03-14 12:48:30 +0800123
124 if (mclk_ps >= 2500)
125 cwl = 5;
126 else if (mclk_ps >= 1875)
127 cwl = 6;
128 else if (mclk_ps >= 1500)
129 cwl = 7;
130 else if (mclk_ps >= 1250)
131 cwl = 8;
York Sun2bba85f2011-08-24 09:40:25 -0700132 else if (mclk_ps >= 1070)
133 cwl = 9;
134 else if (mclk_ps >= 935)
135 cwl = 10;
136 else if (mclk_ps >= 833)
137 cwl = 11;
138 else if (mclk_ps >= 750)
139 cwl = 12;
140 else {
141 cwl = 12;
142 printf("Warning: CWL is out of range\n");
143 }
Dave Liuc360cea2009-03-14 12:48:30 +0800144 return cwl;
145}
York Sun34e026f2014-03-27 17:54:47 -0700146#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800147
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500148/* Chip Select Configuration (CSn_CONFIG) */
york5800e7a2010-07-02 22:25:53 +0000149static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500150 const memctl_options_t *popts,
151 const dimm_params_t *dimm_params)
152{
153 unsigned int cs_n_en = 0; /* Chip Select enable */
154 unsigned int intlv_en = 0; /* Memory controller interleave enable */
155 unsigned int intlv_ctl = 0; /* Interleaving control */
156 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
157 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
158 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
159 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
160 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
161 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
york5800e7a2010-07-02 22:25:53 +0000162 int go_config = 0;
York Sun34e026f2014-03-27 17:54:47 -0700163#ifdef CONFIG_SYS_FSL_DDR4
164 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
165#else
166 unsigned int n_banks_per_sdram_device;
167#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500168
169 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
york5800e7a2010-07-02 22:25:53 +0000170 switch (i) {
171 case 0:
172 if (dimm_params[dimm_number].n_ranks > 0) {
173 go_config = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500174 /* These fields only available in CS0_CONFIG */
York Suna4c66502012-08-17 08:22:39 +0000175 if (!popts->memctl_interleaving)
176 break;
177 switch (popts->memctl_interleaving_mode) {
York Sun6b1e1252014-02-10 13:59:44 -0800178 case FSL_DDR_256B_INTERLEAVING:
York Suna4c66502012-08-17 08:22:39 +0000179 case FSL_DDR_CACHE_LINE_INTERLEAVING:
180 case FSL_DDR_PAGE_INTERLEAVING:
181 case FSL_DDR_BANK_INTERLEAVING:
182 case FSL_DDR_SUPERBANK_INTERLEAVING:
183 intlv_en = popts->memctl_interleaving;
184 intlv_ctl = popts->memctl_interleaving_mode;
185 break;
186 default:
187 break;
188 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500189 }
york5800e7a2010-07-02 22:25:53 +0000190 break;
191 case 1:
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
193 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
194 go_config = 1;
195 break;
196 case 2:
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
York Suncae7c1b2011-08-26 11:32:40 -0700198 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
york5800e7a2010-07-02 22:25:53 +0000199 go_config = 1;
200 break;
201 case 3:
202 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
203 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
204 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
205 go_config = 1;
206 break;
207 default:
208 break;
209 }
210 if (go_config) {
york5800e7a2010-07-02 22:25:53 +0000211 cs_n_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500212 ap_n_en = popts->cs_local_opts[i].auto_precharge;
213 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
214 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
York Sun34e026f2014-03-27 17:54:47 -0700215#ifdef CONFIG_SYS_FSL_DDR4
216 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
217 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
218#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500219 n_banks_per_sdram_device
york5800e7a2010-07-02 22:25:53 +0000220 = dimm_params[dimm_number].n_banks_per_sdram_device;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500221 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
York Sun34e026f2014-03-27 17:54:47 -0700222#endif
york5800e7a2010-07-02 22:25:53 +0000223 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
224 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500225 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500226 ddr->cs[i].config = (0
227 | ((cs_n_en & 0x1) << 31)
228 | ((intlv_en & 0x3) << 29)
Haiying Wangdbbbb3a2008-10-03 12:36:39 -0400229 | ((intlv_ctl & 0xf) << 24)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500230 | ((ap_n_en & 0x1) << 23)
231
232 /* XXX: some implementation only have 1 bit starting at left */
233 | ((odt_rd_cfg & 0x7) << 20)
234
235 /* XXX: Some implementation only have 1 bit starting at left */
236 | ((odt_wr_cfg & 0x7) << 16)
237
238 | ((ba_bits_cs_n & 0x3) << 14)
239 | ((row_bits_cs_n & 0x7) << 8)
York Sun34e026f2014-03-27 17:54:47 -0700240#ifdef CONFIG_SYS_FSL_DDR4
241 | ((bg_bits_cs_n & 0x3) << 4)
242#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500243 | ((col_bits_cs_n & 0x7) << 0)
244 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400245 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500246}
247
248/* Chip Select Configuration 2 (CSn_CONFIG_2) */
249/* FIXME: 8572 */
250static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
251{
252 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
253
254 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
Haiying Wang1f293b42008-10-03 12:37:26 -0400255 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500256}
257
258/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
259
York Sun5614e712013-09-30 09:22:09 -0700260#if !defined(CONFIG_SYS_FSL_DDR1)
York Sun84baed22014-11-07 12:14:36 -0800261/*
262 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
263 * Return 1 if other two slots configuration. Return 0 if single slot.
264 */
York Sun123922b2012-10-08 07:44:23 +0000265static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
266{
267#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
268 if (dimm_params[0].n_ranks == 4)
York Sun84baed22014-11-07 12:14:36 -0800269 return 2;
York Sun123922b2012-10-08 07:44:23 +0000270#endif
271
272#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
273 if ((dimm_params[0].n_ranks == 2) &&
274 (dimm_params[1].n_ranks == 2))
York Sun84baed22014-11-07 12:14:36 -0800275 return 2;
York Sun123922b2012-10-08 07:44:23 +0000276
277#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
278 if (dimm_params[0].n_ranks == 4)
York Sun84baed22014-11-07 12:14:36 -0800279 return 2;
York Sun123922b2012-10-08 07:44:23 +0000280#endif
York Sun84baed22014-11-07 12:14:36 -0800281
282 if ((dimm_params[0].n_ranks != 0) &&
283 (dimm_params[2].n_ranks != 0))
284 return 1;
York Sun123922b2012-10-08 07:44:23 +0000285#endif
286 return 0;
287}
288
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500289/*
290 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
291 *
292 * Avoid writing for DDR I. The new PQ38 DDR controller
293 * dreams up non-zero default values to be backwards compatible.
294 */
York Sun03e664d2015-01-06 13:18:50 -0800295static void set_timing_cfg_0(const unsigned int ctrl_num,
296 fsl_ddr_cfg_regs_t *ddr,
York Sun123922b2012-10-08 07:44:23 +0000297 const memctl_options_t *popts,
298 const dimm_params_t *dimm_params)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500299{
300 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
301 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
302 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
303 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
304 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
305
306 /* Active powerdown exit timing (tXARD and tXARDS). */
307 unsigned char act_pd_exit_mclk;
308 /* Precharge powerdown exit timing (tXP). */
309 unsigned char pre_pd_exit_mclk;
york5fb8a8a2010-07-02 22:25:56 +0000310 /* ODT powerdown exit timing (tAXPD). */
York Sun34e026f2014-03-27 17:54:47 -0700311 unsigned char taxpd_mclk = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500312 /* Mode register set cycle time (tMRD). */
313 unsigned char tmrd_mclk;
York Sunbb578322014-08-21 16:13:22 -0700314#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
York Sun03e664d2015-01-06 13:18:50 -0800315 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sunbb578322014-08-21 16:13:22 -0700316#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500317
York Sun34e026f2014-03-27 17:54:47 -0700318#ifdef CONFIG_SYS_FSL_DDR4
319 /* tXP=max(4nCK, 6ns) */
Masahiro Yamadab4141192014-11-07 03:03:31 +0900320 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
York Sun66869f92015-03-19 09:30:26 -0700321 unsigned int data_rate = get_ddr_freq(ctrl_num);
322
323 /* for faster clock, need more time for data setup */
324 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
York Sun6c6e0062015-11-04 10:03:21 -0800325
326 /*
327 * for single quad-rank DIMM and two-slot DIMMs
328 * to avoid ODT overlap
329 */
330 switch (avoid_odt_overlap(dimm_params)) {
331 case 2:
332 twrt_mclk = 2;
333 twwt_mclk = 2;
334 trrt_mclk = 2;
335 break;
336 default:
337 twrt_mclk = 1;
338 twwt_mclk = 1;
339 trrt_mclk = 0;
340 break;
341 }
342
York Sun03e664d2015-01-06 13:18:50 -0800343 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
York Sun34e026f2014-03-27 17:54:47 -0700344 pre_pd_exit_mclk = act_pd_exit_mclk;
345 /*
346 * MRS_CYC = max(tMRD, tMOD)
347 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
348 */
York Sun03e664d2015-01-06 13:18:50 -0800349 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
York Sun34e026f2014-03-27 17:54:47 -0700350#elif defined(CONFIG_SYS_FSL_DDR3)
York Sun03e664d2015-01-06 13:18:50 -0800351 unsigned int data_rate = get_ddr_freq(ctrl_num);
York Sunbb578322014-08-21 16:13:22 -0700352 int txp;
York Sun938bbb62014-12-02 11:18:09 -0800353 unsigned int ip_rev;
York Sun84baed22014-11-07 12:14:36 -0800354 int odt_overlap;
Dave Liuc360cea2009-03-14 12:48:30 +0800355 /*
356 * (tXARD and tXARDS). Empirical?
357 * The DDR3 spec has not tXARD,
358 * we use the tXP instead of it.
York Sunbb578322014-08-21 16:13:22 -0700359 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
360 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
Dave Liuc360cea2009-03-14 12:48:30 +0800361 * spec has not the tAXPD, we use
york5fb8a8a2010-07-02 22:25:56 +0000362 * tAXPD=1, need design to confirm.
Dave Liuc360cea2009-03-14 12:48:30 +0800363 */
Masahiro Yamadab4141192014-11-07 03:03:31 +0900364 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
York Sunbb578322014-08-21 16:13:22 -0700365
York Sun66869f92015-03-19 09:30:26 -0700366 ip_rev = fsl_ddr_get_version(ctrl_num);
York Sun938bbb62014-12-02 11:18:09 -0800367 if (ip_rev >= 0x40700) {
368 /*
369 * MRS_CYC = max(tMRD, tMOD)
370 * tMRD = 4nCK (8nCK for RDIMM)
371 * tMOD = max(12nCK, 15ns)
372 */
York Sun03e664d2015-01-06 13:18:50 -0800373 tmrd_mclk = max((unsigned int)12,
374 picos_to_mclk(ctrl_num, 15000));
York Sun938bbb62014-12-02 11:18:09 -0800375 } else {
376 /*
377 * MRS_CYC = tMRD
378 * tMRD = 4nCK (8nCK for RDIMM)
379 */
380 if (popts->registered_dimm_en)
381 tmrd_mclk = 8;
382 else
383 tmrd_mclk = 4;
384 }
385
Dave Liu99bac472009-12-08 11:56:48 +0800386 /* set the turnaround time */
York Sun123922b2012-10-08 07:44:23 +0000387
388 /*
York Sun84baed22014-11-07 12:14:36 -0800389 * for single quad-rank DIMM and two-slot DIMMs
York Sun123922b2012-10-08 07:44:23 +0000390 * to avoid ODT overlap
391 */
York Sun84baed22014-11-07 12:14:36 -0800392 odt_overlap = avoid_odt_overlap(dimm_params);
393 switch (odt_overlap) {
394 case 2:
York Sun123922b2012-10-08 07:44:23 +0000395 twwt_mclk = 2;
396 trrt_mclk = 1;
York Sun84baed22014-11-07 12:14:36 -0800397 break;
398 case 1:
399 twwt_mclk = 1;
400 trrt_mclk = 0;
401 break;
402 default:
403 break;
York Sun123922b2012-10-08 07:44:23 +0000404 }
York Sun84baed22014-11-07 12:14:36 -0800405
York Sun123922b2012-10-08 07:44:23 +0000406 /* for faster clock, need more time for data setup */
407 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
408
York Sun856e4b02011-02-10 10:13:10 -0800409 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
410 twrt_mclk = 1;
York Sune1fd16b2011-01-10 12:03:00 +0000411
412 if (popts->dynamic_power == 0) { /* powerdown is not used */
413 act_pd_exit_mclk = 1;
414 pre_pd_exit_mclk = 1;
415 taxpd_mclk = 1;
416 } else {
417 /* act_pd_exit_mclk = tXARD, see above */
York Sun03e664d2015-01-06 13:18:50 -0800418 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
York Sune1fd16b2011-01-10 12:03:00 +0000419 /* Mode register MR0[A12] is '1' - fast exit */
420 pre_pd_exit_mclk = act_pd_exit_mclk;
421 taxpd_mclk = 1;
422 }
York Sun5614e712013-09-30 09:22:09 -0700423#else /* CONFIG_SYS_FSL_DDR2 */
Dave Liuc360cea2009-03-14 12:48:30 +0800424 /*
425 * (tXARD and tXARDS). Empirical?
426 * tXARD = 2 for DDR2
427 * tXP=2
428 * tAXPD=8
429 */
430 act_pd_exit_mclk = 2;
431 pre_pd_exit_mclk = 2;
432 taxpd_mclk = 8;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500433 tmrd_mclk = 2;
Dave Liuc360cea2009-03-14 12:48:30 +0800434#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500435
York Sun23f96702011-05-27 13:44:28 +0800436 if (popts->trwt_override)
437 trwt_mclk = popts->trwt;
438
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500439 ddr->timing_cfg_0 = (0
440 | ((trwt_mclk & 0x3) << 30) /* RWT */
441 | ((twrt_mclk & 0x3) << 28) /* WRT */
442 | ((trrt_mclk & 0x3) << 26) /* RRT */
443 | ((twwt_mclk & 0x3) << 24) /* WWT */
York Sund4263b82013-06-03 12:39:06 -0700444 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
Dave Liu22ff3d02008-11-21 16:31:29 +0800445 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500446 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
York Sund4263b82013-06-03 12:39:06 -0700447 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500448 );
449 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
450}
York Sun84baed22014-11-07 12:14:36 -0800451#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500452
453/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
York Sun03e664d2015-01-06 13:18:50 -0800454static void set_timing_cfg_3(const unsigned int ctrl_num,
455 fsl_ddr_cfg_regs_t *ddr,
456 const memctl_options_t *popts,
457 const common_timing_params_t *common_dimm,
458 unsigned int cas_latency,
459 unsigned int additive_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500460{
York Sun45064ad2012-08-17 08:22:40 +0000461 /* Extended precharge to activate interval (tRP) */
462 unsigned int ext_pretoact = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500463 /* Extended Activate to precharge interval (tRAS) */
464 unsigned int ext_acttopre = 0;
York Sun45064ad2012-08-17 08:22:40 +0000465 /* Extended activate to read/write interval (tRCD) */
466 unsigned int ext_acttorw = 0;
467 /* Extended refresh recovery time (tRFC) */
468 unsigned int ext_refrec;
469 /* Extended MCAS latency from READ cmd */
470 unsigned int ext_caslat = 0;
York Sund4263b82013-06-03 12:39:06 -0700471 /* Extended additive latency */
472 unsigned int ext_add_lat = 0;
York Sun45064ad2012-08-17 08:22:40 +0000473 /* Extended last data to precharge interval (tWR) */
474 unsigned int ext_wrrec = 0;
475 /* Control Adjust */
476 unsigned int cntl_adj = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500477
York Sun03e664d2015-01-06 13:18:50 -0800478 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
479 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
480 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000481 ext_caslat = (2 * cas_latency - 1) >> 4;
York Sund4263b82013-06-03 12:39:06 -0700482 ext_add_lat = additive_latency >> 4;
York Sun34e026f2014-03-27 17:54:47 -0700483#ifdef CONFIG_SYS_FSL_DDR4
York Sun03e664d2015-01-06 13:18:50 -0800484 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
York Sun34e026f2014-03-27 17:54:47 -0700485#else
York Sun03e664d2015-01-06 13:18:50 -0800486 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
York Sun45064ad2012-08-17 08:22:40 +0000487 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
York Sun34e026f2014-03-27 17:54:47 -0700488#endif
York Sun03e664d2015-01-06 13:18:50 -0800489 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530490 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
Dave Liuc360cea2009-03-14 12:48:30 +0800491
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500492 ddr->timing_cfg_3 = (0
York Sun45064ad2012-08-17 08:22:40 +0000493 | ((ext_pretoact & 0x1) << 28)
James Yangc45f5c02013-07-22 09:35:26 -0700494 | ((ext_acttopre & 0x3) << 24)
York Sun45064ad2012-08-17 08:22:40 +0000495 | ((ext_acttorw & 0x1) << 22)
York Sunc0c32af2018-01-29 09:44:35 -0800496 | ((ext_refrec & 0x3F) << 16)
York Sun45064ad2012-08-17 08:22:40 +0000497 | ((ext_caslat & 0x3) << 12)
York Sund4263b82013-06-03 12:39:06 -0700498 | ((ext_add_lat & 0x1) << 10)
York Sun45064ad2012-08-17 08:22:40 +0000499 | ((ext_wrrec & 0x1) << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500500 | ((cntl_adj & 0x7) << 0)
501 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400502 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500503}
504
505/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
York Sun03e664d2015-01-06 13:18:50 -0800506static void set_timing_cfg_1(const unsigned int ctrl_num,
507 fsl_ddr_cfg_regs_t *ddr,
508 const memctl_options_t *popts,
509 const common_timing_params_t *common_dimm,
510 unsigned int cas_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500511{
512 /* Precharge-to-activate interval (tRP) */
513 unsigned char pretoact_mclk;
514 /* Activate to precharge interval (tRAS) */
515 unsigned char acttopre_mclk;
516 /* Activate to read/write interval (tRCD) */
517 unsigned char acttorw_mclk;
518 /* CASLAT */
519 unsigned char caslat_ctrl;
520 /* Refresh recovery time (tRFC) ; trfc_low */
521 unsigned char refrec_ctrl;
522 /* Last data to precharge minimum interval (tWR) */
523 unsigned char wrrec_mclk;
524 /* Activate-to-activate interval (tRRD) */
525 unsigned char acttoact_mclk;
526 /* Last write data pair to read command issue interval (tWTR) */
527 unsigned char wrtord_mclk;
York Sun34e026f2014-03-27 17:54:47 -0700528#ifdef CONFIG_SYS_FSL_DDR4
529 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
530 static const u8 wrrec_table[] = {
531 10, 10, 10, 10, 10,
532 10, 10, 10, 10, 10,
533 12, 12, 14, 14, 16,
534 16, 18, 18, 20, 20,
535 24, 24, 24, 24};
536#else
York Sunf5b6fb72011-03-02 14:24:11 -0800537 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
538 static const u8 wrrec_table[] = {
539 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
York Sun34e026f2014-03-27 17:54:47 -0700540#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500541
York Sun03e664d2015-01-06 13:18:50 -0800542 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
543 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
544 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500545
546 /*
547 * Translate CAS Latency to a DDR controller field value:
548 *
549 * CAS Lat DDR I DDR II Ctrl
550 * Clocks SPD Bit SPD Bit Value
551 * ------- ------- ------- -----
552 * 1.0 0 0001
553 * 1.5 1 0010
554 * 2.0 2 2 0011
555 * 2.5 3 0100
556 * 3.0 4 3 0101
557 * 3.5 5 0110
558 * 4.0 4 0111
559 * 4.5 1000
560 * 5.0 5 1001
561 */
York Sun5614e712013-09-30 09:22:09 -0700562#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500563 caslat_ctrl = (cas_latency + 1) & 0x07;
York Sun5614e712013-09-30 09:22:09 -0700564#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500565 caslat_ctrl = 2 * cas_latency - 1;
566#else
Dave Liuc360cea2009-03-14 12:48:30 +0800567 /*
568 * if the CAS latency more than 8 cycle,
569 * we need set extend bit for it at
570 * TIMING_CFG_3[EXT_CASLAT]
571 */
York Sun66869f92015-03-19 09:30:26 -0700572 if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
York Sun34e026f2014-03-27 17:54:47 -0700573 caslat_ctrl = 2 * cas_latency - 1;
574 else
575 caslat_ctrl = (cas_latency - 1) << 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500576#endif
577
York Sun34e026f2014-03-27 17:54:47 -0700578#ifdef CONFIG_SYS_FSL_DDR4
York Sun03e664d2015-01-06 13:18:50 -0800579 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
580 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
581 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
582 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
York Sun349689b2014-04-01 14:20:49 -0700583 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
584 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun34e026f2014-03-27 17:54:47 -0700585 else
586 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
587#else
York Sun03e664d2015-01-06 13:18:50 -0800588 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
589 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
590 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
591 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
York Sun349689b2014-04-01 14:20:49 -0700592 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
593 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
York Sun45064ad2012-08-17 08:22:40 +0000594 else
595 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
York Sun34e026f2014-03-27 17:54:47 -0700596#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530597 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800598 wrrec_mclk += 2;
599
Dave Liuc360cea2009-03-14 12:48:30 +0800600 /*
601 * JEDEC has min requirement for tRRD
602 */
York Sun5614e712013-09-30 09:22:09 -0700603#if defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800604 if (acttoact_mclk < 4)
605 acttoact_mclk = 4;
606#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800607 /*
608 * JEDEC has some min requirements for tWTR
609 */
York Sun5614e712013-09-30 09:22:09 -0700610#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800611 if (wrtord_mclk < 2)
612 wrtord_mclk = 2;
York Sun5614e712013-09-30 09:22:09 -0700613#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +0800614 if (wrtord_mclk < 4)
615 wrtord_mclk = 4;
616#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530617 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800618 wrtord_mclk += 2;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500619
620 ddr->timing_cfg_1 = (0
Dave Liu80ee3ce2008-11-21 16:31:22 +0800621 | ((pretoact_mclk & 0x0F) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500622 | ((acttopre_mclk & 0x0F) << 24)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800623 | ((acttorw_mclk & 0xF) << 20)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500624 | ((caslat_ctrl & 0xF) << 16)
625 | ((refrec_ctrl & 0xF) << 12)
Dave Liu80ee3ce2008-11-21 16:31:22 +0800626 | ((wrrec_mclk & 0x0F) << 8)
York Sun57495e42012-10-08 07:44:22 +0000627 | ((acttoact_mclk & 0x0F) << 4)
628 | ((wrtord_mclk & 0x0F) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500629 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400630 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500631}
632
633/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
York Sun03e664d2015-01-06 13:18:50 -0800634static void set_timing_cfg_2(const unsigned int ctrl_num,
635 fsl_ddr_cfg_regs_t *ddr,
636 const memctl_options_t *popts,
637 const common_timing_params_t *common_dimm,
638 unsigned int cas_latency,
639 unsigned int additive_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500640{
641 /* Additive latency */
642 unsigned char add_lat_mclk;
643 /* CAS-to-preamble override */
644 unsigned short cpo;
645 /* Write latency */
646 unsigned char wr_lat;
647 /* Read to precharge (tRTP) */
648 unsigned char rd_to_pre;
649 /* Write command to write data strobe timing adjustment */
650 unsigned char wr_data_delay;
651 /* Minimum CKE pulse width (tCKE) */
652 unsigned char cke_pls;
653 /* Window for four activates (tFAW) */
654 unsigned short four_act;
York Sunbb578322014-08-21 16:13:22 -0700655#ifdef CONFIG_SYS_FSL_DDR3
York Sun03e664d2015-01-06 13:18:50 -0800656 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sunbb578322014-08-21 16:13:22 -0700657#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500658
659 /* FIXME add check that this must be less than acttorw_mclk */
660 add_lat_mclk = additive_latency;
661 cpo = popts->cpo_override;
662
York Sun5614e712013-09-30 09:22:09 -0700663#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500664 /*
665 * This is a lie. It should really be 1, but if it is
666 * set to 1, bits overlap into the old controller's
667 * otherwise unused ACSM field. If we leave it 0, then
668 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
669 */
670 wr_lat = 0;
York Sun5614e712013-09-30 09:22:09 -0700671#elif defined(CONFIG_SYS_FSL_DDR2)
Dave Liu6a819782009-03-14 12:48:19 +0800672 wr_lat = cas_latency - 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500673#else
York Sun03e664d2015-01-06 13:18:50 -0800674 wr_lat = compute_cas_write_latency(ctrl_num);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500675#endif
676
York Sun34e026f2014-03-27 17:54:47 -0700677#ifdef CONFIG_SYS_FSL_DDR4
York Sun03e664d2015-01-06 13:18:50 -0800678 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
York Sun34e026f2014-03-27 17:54:47 -0700679#else
York Sun03e664d2015-01-06 13:18:50 -0800680 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
York Sun34e026f2014-03-27 17:54:47 -0700681#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800682 /*
683 * JEDEC has some min requirements for tRTP
684 */
York Sun5614e712013-09-30 09:22:09 -0700685#if defined(CONFIG_SYS_FSL_DDR2)
Dave Liuc360cea2009-03-14 12:48:30 +0800686 if (rd_to_pre < 2)
687 rd_to_pre = 2;
York Sun34e026f2014-03-27 17:54:47 -0700688#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800689 if (rd_to_pre < 4)
690 rd_to_pre = 4;
Dave Liu6a819782009-03-14 12:48:19 +0800691#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530692 if (popts->otf_burst_chop_en)
Dave Liuc360cea2009-03-14 12:48:30 +0800693 rd_to_pre += 2; /* according to UM */
694
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500695 wr_data_delay = popts->write_data_delay;
York Sun34e026f2014-03-27 17:54:47 -0700696#ifdef CONFIG_SYS_FSL_DDR4
697 cpo = 0;
York Sun03e664d2015-01-06 13:18:50 -0800698 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
York Sunbb578322014-08-21 16:13:22 -0700699#elif defined(CONFIG_SYS_FSL_DDR3)
700 /*
701 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
702 * max(3nCK, 5.625ns) for DDR3-1066, 1333
703 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
704 */
York Sun03e664d2015-01-06 13:18:50 -0800705 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
706 (mclk_ps > 1245 ? 5625 : 5000)));
York Sun34e026f2014-03-27 17:54:47 -0700707#else
York Sunbb578322014-08-21 16:13:22 -0700708 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
York Sun34e026f2014-03-27 17:54:47 -0700709#endif
York Sun03e664d2015-01-06 13:18:50 -0800710 four_act = picos_to_mclk(ctrl_num,
711 popts->tfaw_window_four_activates_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500712
713 ddr->timing_cfg_2 = (0
Dave Liu22ff3d02008-11-21 16:31:29 +0800714 | ((add_lat_mclk & 0xf) << 28)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500715 | ((cpo & 0x1f) << 23)
Dave Liu22ff3d02008-11-21 16:31:29 +0800716 | ((wr_lat & 0xf) << 19)
York Sun89366912016-07-29 09:02:29 -0700717 | (((wr_lat & 0x10) >> 4) << 18)
Dave Liuc360cea2009-03-14 12:48:30 +0800718 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
719 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500720 | ((cke_pls & 0x7) << 6)
Dave Liu22ff3d02008-11-21 16:31:29 +0800721 | ((four_act & 0x3f) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500722 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400723 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500724}
725
york9490ff42010-07-02 22:25:55 +0000726/* DDR SDRAM Register Control Word */
York Sun564e9382018-01-29 10:24:08 -0800727static void set_ddr_sdram_rcw(const unsigned int ctrl_num,
728 fsl_ddr_cfg_regs_t *ddr,
729 const memctl_options_t *popts,
730 const common_timing_params_t *common_dimm)
york9490ff42010-07-02 22:25:55 +0000731{
York Sun564e9382018-01-29 10:24:08 -0800732 unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
733 unsigned int rc0a, rc0f;
734
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530735 if (common_dimm->all_dimms_registered &&
736 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000737 if (popts->rcw_override) {
738 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
739 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
York Sun426230a2018-01-29 09:44:33 -0800740 ddr->ddr_sdram_rcw_3 = popts->rcw_3;
York Sune1fd16b2011-01-10 12:03:00 +0000741 } else {
York Sun564e9382018-01-29 10:24:08 -0800742 rc0a = ddr_freq > 3200 ? 0x7 :
743 (ddr_freq > 2933 ? 0x6 :
744 (ddr_freq > 2666 ? 0x5 :
745 (ddr_freq > 2400 ? 0x4 :
746 (ddr_freq > 2133 ? 0x3 :
747 (ddr_freq > 1866 ? 0x2 :
748 (ddr_freq > 1600 ? 1 : 0))))));
749 rc0f = ddr_freq > 3200 ? 0x3 :
750 (ddr_freq > 2400 ? 0x2 :
751 (ddr_freq > 2133 ? 0x1 : 0));
York Sune1fd16b2011-01-10 12:03:00 +0000752 ddr->ddr_sdram_rcw_1 =
753 common_dimm->rcw[0] << 28 | \
754 common_dimm->rcw[1] << 24 | \
755 common_dimm->rcw[2] << 20 | \
756 common_dimm->rcw[3] << 16 | \
757 common_dimm->rcw[4] << 12 | \
758 common_dimm->rcw[5] << 8 | \
759 common_dimm->rcw[6] << 4 | \
760 common_dimm->rcw[7];
761 ddr->ddr_sdram_rcw_2 =
762 common_dimm->rcw[8] << 28 | \
763 common_dimm->rcw[9] << 24 | \
York Sun564e9382018-01-29 10:24:08 -0800764 rc0a << 20 | \
York Sune1fd16b2011-01-10 12:03:00 +0000765 common_dimm->rcw[11] << 16 | \
766 common_dimm->rcw[12] << 12 | \
767 common_dimm->rcw[13] << 8 | \
768 common_dimm->rcw[14] << 4 | \
York Sun564e9382018-01-29 10:24:08 -0800769 rc0f;
770 ddr->ddr_sdram_rcw_3 =
771 ((ddr_freq - 1260 + 19) / 20) << 8;
York Sune1fd16b2011-01-10 12:03:00 +0000772 }
York Sun426230a2018-01-29 09:44:33 -0800773 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
774 ddr->ddr_sdram_rcw_1);
775 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
776 ddr->ddr_sdram_rcw_2);
777 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
778 ddr->ddr_sdram_rcw_3);
york9490ff42010-07-02 22:25:55 +0000779 }
780}
781
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500782/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
783static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
784 const memctl_options_t *popts,
785 const common_timing_params_t *common_dimm)
786{
787 unsigned int mem_en; /* DDR SDRAM interface logic enable */
788 unsigned int sren; /* Self refresh enable (during sleep) */
789 unsigned int ecc_en; /* ECC enable. */
790 unsigned int rd_en; /* Registered DIMM enable */
791 unsigned int sdram_type; /* Type of SDRAM */
792 unsigned int dyn_pwr; /* Dynamic power management mode */
793 unsigned int dbw; /* DRAM dta bus width */
Dave Liu22ff3d02008-11-21 16:31:29 +0800794 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500795 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530796 unsigned int threet_en; /* Enable 3T timing */
797 unsigned int twot_en; /* Enable 2T timing */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500798 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
799 unsigned int x32_en = 0; /* x32 enable */
800 unsigned int pchb8 = 0; /* precharge bit 8 enable */
801 unsigned int hse; /* Global half strength override */
York Sund28cb672014-09-05 13:52:41 +0800802 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500803 unsigned int mem_halt = 0; /* memory controller halt */
804 unsigned int bi = 0; /* Bypass initialization */
805
806 mem_en = 1;
807 sren = popts->self_refresh_in_sleep;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530808 if (common_dimm->all_dimms_ecc_capable) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500809 /* Allow setting of ECC only if all DIMMs are ECC. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530810 ecc_en = popts->ecc_mode;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500811 } else {
812 ecc_en = 0;
813 }
814
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530815 if (common_dimm->all_dimms_registered &&
816 !common_dimm->all_dimms_unbuffered) {
York Sune1fd16b2011-01-10 12:03:00 +0000817 rd_en = 1;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530818 twot_en = 0;
York Sune1fd16b2011-01-10 12:03:00 +0000819 } else {
820 rd_en = 0;
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530821 twot_en = popts->twot_en;
York Sune1fd16b2011-01-10 12:03:00 +0000822 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500823
824 sdram_type = CONFIG_FSL_SDRAM_TYPE;
825
826 dyn_pwr = popts->dynamic_power;
827 dbw = popts->data_bus_width;
Dave Liuc360cea2009-03-14 12:48:30 +0800828 /* 8-beat burst enable DDR-III case
829 * we must clear it when use the on-the-fly mode,
830 * must set it when use the 32-bits bus mode.
831 */
York Sun34e026f2014-03-27 17:54:47 -0700832 if ((sdram_type == SDRAM_TYPE_DDR3) ||
833 (sdram_type == SDRAM_TYPE_DDR4)) {
Dave Liuc360cea2009-03-14 12:48:30 +0800834 if (popts->burst_length == DDR_BL8)
835 eight_be = 1;
836 if (popts->burst_length == DDR_OTF)
837 eight_be = 0;
838 if (dbw == 0x1)
839 eight_be = 1;
840 }
841
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530842 threet_en = popts->threet_en;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500843 ba_intlv_ctl = popts->ba_intlv_ctl;
844 hse = popts->half_strength_driver_enable;
845
York Sund28cb672014-09-05 13:52:41 +0800846 /* set when ddr bus width < 64 */
847 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
848
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500849 ddr->ddr_sdram_cfg = (0
850 | ((mem_en & 0x1) << 31)
851 | ((sren & 0x1) << 30)
852 | ((ecc_en & 0x1) << 29)
853 | ((rd_en & 0x1) << 28)
854 | ((sdram_type & 0x7) << 24)
855 | ((dyn_pwr & 0x1) << 21)
856 | ((dbw & 0x3) << 19)
857 | ((eight_be & 0x1) << 18)
858 | ((ncap & 0x1) << 17)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530859 | ((threet_en & 0x1) << 16)
860 | ((twot_en & 0x1) << 15)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500861 | ((ba_intlv_ctl & 0x7F) << 8)
862 | ((x32_en & 0x1) << 5)
863 | ((pchb8 & 0x1) << 4)
864 | ((hse & 0x1) << 3)
York Sund28cb672014-09-05 13:52:41 +0800865 | ((acc_ecc_en & 0x1) << 2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500866 | ((mem_halt & 0x1) << 1)
867 | ((bi & 0x1) << 0)
868 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400869 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500870}
871
872/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
York Sun03e664d2015-01-06 13:18:50 -0800873static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
874 fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000875 const memctl_options_t *popts,
876 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500877{
878 unsigned int frc_sr = 0; /* Force self refresh */
879 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
York Suncae7c1b2011-08-26 11:32:40 -0700880 unsigned int odt_cfg = 0; /* ODT configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500881 unsigned int num_pr; /* Number of posted refreshes */
York Sun57495e42012-10-08 07:44:22 +0000882 unsigned int slow = 0; /* DDR will be run less than 1250 */
York Sunb61e0612013-06-25 11:37:47 -0700883 unsigned int x4_en = 0; /* x4 DRAM enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500884 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
885 unsigned int ap_en; /* Address Parity Enable */
886 unsigned int d_init; /* DRAM data initialization */
887 unsigned int rcw_en = 0; /* Register Control Word Enable */
888 unsigned int md_en = 0; /* Mirrored DIMM Enable */
york5800e7a2010-07-02 22:25:53 +0000889 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
York Suncae7c1b2011-08-26 11:32:40 -0700890 int i;
York Sun34e026f2014-03-27 17:54:47 -0700891#ifndef CONFIG_SYS_FSL_DDR4
892 unsigned int dll_rst_dis = 1; /* DLL reset disable */
893 unsigned int dqs_cfg; /* DQS configuration */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500894
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530895 dqs_cfg = popts->dqs_config;
York Sun34e026f2014-03-27 17:54:47 -0700896#endif
York Suncae7c1b2011-08-26 11:32:40 -0700897 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
898 if (popts->cs_local_opts[i].odt_rd_cfg
899 || popts->cs_local_opts[i].odt_wr_cfg) {
900 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
901 break;
902 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500903 }
Joakim Tjernlunde368c202015-10-14 16:32:00 +0200904 sr_ie = popts->self_refresh_interrupt_en;
York Sunc0c32af2018-01-29 09:44:35 -0800905 num_pr = popts->package_3ds + 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500906
907 /*
908 * 8572 manual says
909 * {TIMING_CFG_1[PRETOACT]
910 * + [DDR_SDRAM_CFG_2[NUM_PR]
911 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
912 * << DDR_SDRAM_INTERVAL[REFINT]
913 */
York Sun34e026f2014-03-27 17:54:47 -0700914#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530915 obc_cfg = popts->otf_burst_chop_en;
Dave Liuc360cea2009-03-14 12:48:30 +0800916#else
917 obc_cfg = 0;
918#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500919
York Sun57495e42012-10-08 07:44:22 +0000920#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
York Sun03e664d2015-01-06 13:18:50 -0800921 slow = get_ddr_freq(ctrl_num) < 1249000000;
York Sun57495e42012-10-08 07:44:22 +0000922#endif
923
Shengzhou Liueb118802016-03-10 17:36:56 +0800924 if (popts->registered_dimm_en)
York Sune1fd16b2011-01-10 12:03:00 +0000925 rcw_en = 1;
Shengzhou Liueb118802016-03-10 17:36:56 +0800926
927 /* DDR4 can have address parity for UDIMM and discrete */
928 if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
929 (!popts->registered_dimm_en)) {
York Sune1fd16b2011-01-10 12:03:00 +0000930 ap_en = 0;
Shengzhou Liueb118802016-03-10 17:36:56 +0800931 } else {
932 ap_en = popts->ap_en;
York Sune1fd16b2011-01-10 12:03:00 +0000933 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500934
York Sunb61e0612013-06-25 11:37:47 -0700935 x4_en = popts->x4_en ? 1 : 0;
936
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500937#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
938 /* Use the DDR controller to auto initialize memory. */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530939 d_init = popts->ecc_init_using_memctl;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500940 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
941 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
942#else
943 /* Memory will be initialized via DMA, or not at all. */
944 d_init = 0;
945#endif
946
York Sun34e026f2014-03-27 17:54:47 -0700947#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800948 md_en = popts->mirrored_dimm;
949#endif
york5800e7a2010-07-02 22:25:53 +0000950 qd_en = popts->quad_rank_present ? 1 : 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500951 ddr->ddr_sdram_cfg_2 = (0
952 | ((frc_sr & 0x1) << 31)
953 | ((sr_ie & 0x1) << 30)
York Sun34e026f2014-03-27 17:54:47 -0700954#ifndef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500955 | ((dll_rst_dis & 0x1) << 29)
956 | ((dqs_cfg & 0x3) << 26)
York Sun34e026f2014-03-27 17:54:47 -0700957#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500958 | ((odt_cfg & 0x3) << 21)
959 | ((num_pr & 0xf) << 12)
York Sun57495e42012-10-08 07:44:22 +0000960 | ((slow & 1) << 11)
York Sunb61e0612013-06-25 11:37:47 -0700961 | (x4_en << 10)
york5800e7a2010-07-02 22:25:53 +0000962 | (qd_en << 9)
York Sune1fd16b2011-01-10 12:03:00 +0000963 | (unq_mrs_en << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500964 | ((obc_cfg & 0x1) << 6)
965 | ((ap_en & 0x1) << 5)
966 | ((d_init & 0x1) << 4)
967 | ((rcw_en & 0x1) << 2)
968 | ((md_en & 0x1) << 0)
969 );
Haiying Wang1f293b42008-10-03 12:37:26 -0400970 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500971}
972
York Sun34e026f2014-03-27 17:54:47 -0700973#ifdef CONFIG_SYS_FSL_DDR4
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500974/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
York Sun03e664d2015-01-06 13:18:50 -0800975static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
976 fsl_ddr_cfg_regs_t *ddr,
York Sune1fd16b2011-01-10 12:03:00 +0000977 const memctl_options_t *popts,
Valentin Longchamp7e157b02013-10-18 11:47:20 +0200978 const common_timing_params_t *common_dimm,
York Sune1fd16b2011-01-10 12:03:00 +0000979 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500980{
981 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
982 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
York Sun34e026f2014-03-27 17:54:47 -0700983 int i;
984 unsigned int wr_crc = 0; /* Disable */
985 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
986 unsigned int srt = 0; /* self-refresh temerature, normal range */
York Sun03e664d2015-01-06 13:18:50 -0800987 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
York Sun34e026f2014-03-27 17:54:47 -0700988 unsigned int mpr = 0; /* serial */
989 unsigned int wc_lat;
York Sun03e664d2015-01-06 13:18:50 -0800990 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500991
York Sun34e026f2014-03-27 17:54:47 -0700992 if (popts->rtt_override)
993 rtt_wr = popts->rtt_wr_override_value;
994 else
995 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
996
997 if (common_dimm->extended_op_srt)
998 srt = common_dimm->extended_op_srt;
999
1000 esdmode2 = (0
1001 | ((wr_crc & 0x1) << 12)
1002 | ((rtt_wr & 0x3) << 9)
1003 | ((srt & 0x3) << 6)
1004 | ((cwl & 0x7) << 3));
1005
1006 if (mclk_ps >= 1250)
1007 wc_lat = 0;
1008 else if (mclk_ps >= 833)
1009 wc_lat = 1;
1010 else
1011 wc_lat = 2;
1012
1013 esdmode3 = (0
1014 | ((mpr & 0x3) << 11)
1015 | ((wc_lat & 0x3) << 9));
1016
1017 ddr->ddr_sdram_mode_2 = (0
1018 | ((esdmode2 & 0xFFFF) << 16)
1019 | ((esdmode3 & 0xFFFF) << 0)
1020 );
1021 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1022
1023 if (unq_mrs_en) { /* unique mode registers are supported */
1024 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1025 if (popts->rtt_override)
1026 rtt_wr = popts->rtt_wr_override_value;
1027 else
1028 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1029
1030 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1031 esdmode2 |= (rtt_wr & 0x3) << 9;
1032 switch (i) {
1033 case 1:
1034 ddr->ddr_sdram_mode_4 = (0
1035 | ((esdmode2 & 0xFFFF) << 16)
1036 | ((esdmode3 & 0xFFFF) << 0)
1037 );
1038 break;
1039 case 2:
1040 ddr->ddr_sdram_mode_6 = (0
1041 | ((esdmode2 & 0xFFFF) << 16)
1042 | ((esdmode3 & 0xFFFF) << 0)
1043 );
1044 break;
1045 case 3:
1046 ddr->ddr_sdram_mode_8 = (0
1047 | ((esdmode2 & 0xFFFF) << 16)
1048 | ((esdmode3 & 0xFFFF) << 0)
1049 );
1050 break;
1051 }
1052 }
1053 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1054 ddr->ddr_sdram_mode_4);
1055 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1056 ddr->ddr_sdram_mode_6);
1057 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1058 ddr->ddr_sdram_mode_8);
1059 }
1060}
1061#elif defined(CONFIG_SYS_FSL_DDR3)
1062/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
York Sun03e664d2015-01-06 13:18:50 -08001063static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1064 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001065 const memctl_options_t *popts,
1066 const common_timing_params_t *common_dimm,
1067 const unsigned int unq_mrs_en)
1068{
1069 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1070 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
Kumar Gala92966832011-01-20 01:53:15 -06001071 int i;
Dave Liu1aa3d082009-12-16 10:24:38 -06001072 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
Dave Liuc360cea2009-03-14 12:48:30 +08001073 unsigned int srt = 0; /* self-refresh temerature, normal range */
1074 unsigned int asr = 0; /* auto self-refresh disable */
York Sun03e664d2015-01-06 13:18:50 -08001075 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
Dave Liuc360cea2009-03-14 12:48:30 +08001076 unsigned int pasr = 0; /* partial array self refresh disable */
1077
Dave Liu1aa3d082009-12-16 10:24:38 -06001078 if (popts->rtt_override)
1079 rtt_wr = popts->rtt_wr_override_value;
York Sune1fd16b2011-01-10 12:03:00 +00001080 else
1081 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
Valentin Longchamp7e157b02013-10-18 11:47:20 +02001082
1083 if (common_dimm->extended_op_srt)
1084 srt = common_dimm->extended_op_srt;
1085
Dave Liuc360cea2009-03-14 12:48:30 +08001086 esdmode2 = (0
1087 | ((rtt_wr & 0x3) << 9)
1088 | ((srt & 0x1) << 7)
1089 | ((asr & 0x1) << 6)
1090 | ((cwl & 0x7) << 3)
1091 | ((pasr & 0x7) << 0));
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001092 ddr->ddr_sdram_mode_2 = (0
1093 | ((esdmode2 & 0xFFFF) << 16)
1094 | ((esdmode3 & 0xFFFF) << 0)
1095 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001096 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
York Sune1fd16b2011-01-10 12:03:00 +00001097
York Sune1fd16b2011-01-10 12:03:00 +00001098 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -06001099 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +00001100 if (popts->rtt_override)
1101 rtt_wr = popts->rtt_wr_override_value;
1102 else
1103 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1104
1105 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1106 esdmode2 |= (rtt_wr & 0x3) << 9;
1107 switch (i) {
1108 case 1:
1109 ddr->ddr_sdram_mode_4 = (0
1110 | ((esdmode2 & 0xFFFF) << 16)
1111 | ((esdmode3 & 0xFFFF) << 0)
1112 );
1113 break;
1114 case 2:
1115 ddr->ddr_sdram_mode_6 = (0
1116 | ((esdmode2 & 0xFFFF) << 16)
1117 | ((esdmode3 & 0xFFFF) << 0)
1118 );
1119 break;
1120 case 3:
1121 ddr->ddr_sdram_mode_8 = (0
1122 | ((esdmode2 & 0xFFFF) << 16)
1123 | ((esdmode3 & 0xFFFF) << 0)
1124 );
1125 break;
1126 }
1127 }
1128 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1129 ddr->ddr_sdram_mode_4);
1130 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1131 ddr->ddr_sdram_mode_6);
1132 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1133 ddr->ddr_sdram_mode_8);
1134 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001135}
1136
York Sun34e026f2014-03-27 17:54:47 -07001137#else /* for DDR2 and DDR1 */
1138/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
York Sun03e664d2015-01-06 13:18:50 -08001139static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1140 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001141 const memctl_options_t *popts,
1142 const common_timing_params_t *common_dimm,
1143 const unsigned int unq_mrs_en)
1144{
1145 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1146 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1147
1148 ddr->ddr_sdram_mode_2 = (0
1149 | ((esdmode2 & 0xFFFF) << 16)
1150 | ((esdmode3 & 0xFFFF) << 0)
1151 );
1152 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1153}
1154#endif
1155
1156#ifdef CONFIG_SYS_FSL_DDR4
1157/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1158static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1159 const memctl_options_t *popts,
1160 const common_timing_params_t *common_dimm,
1161 const unsigned int unq_mrs_en)
1162{
1163 int i;
1164 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1165 unsigned short esdmode5; /* Extended SDRAM mode 5 */
York Sun6b95be22015-03-19 09:30:27 -07001166 int rtt_park = 0;
York Sun8a514292015-11-04 10:03:19 -08001167 bool four_cs = false;
Shengzhou Liueb118802016-03-10 17:36:56 +08001168 const unsigned int mclk_ps = get_memory_clk_period_ps(0);
York Sun34e026f2014-03-27 17:54:47 -07001169
York Sun8a514292015-11-04 10:03:19 -08001170#if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1171 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1172 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1173 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1174 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1175 four_cs = true;
1176#endif
York Sun6b95be22015-03-19 09:30:27 -07001177 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1178 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
York Sun8a514292015-11-04 10:03:19 -08001179 rtt_park = four_cs ? 0 : 1;
York Sun6b95be22015-03-19 09:30:27 -07001180 } else {
1181 esdmode5 = 0x00000400; /* Data mask enabled */
1182 }
York Sun34e026f2014-03-27 17:54:47 -07001183
York Sun426230a2018-01-29 09:44:33 -08001184 /*
1185 * For DDR3, set C/A latency if address parity is enabled.
1186 * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1187 * handled by register chip and RCW settings.
1188 */
1189 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1190 ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1191 !popts->registered_dimm_en)) {
Shengzhou Liueb118802016-03-10 17:36:56 +08001192 if (mclk_ps >= 935) {
1193 /* for DDR4-1600/1866/2133 */
1194 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1195 } else if (mclk_ps >= 833) {
1196 /* for DDR4-2400 */
1197 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1198 } else {
1199 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1200 }
1201 }
1202
York Sun34e026f2014-03-27 17:54:47 -07001203 ddr->ddr_sdram_mode_9 = (0
1204 | ((esdmode4 & 0xffff) << 16)
1205 | ((esdmode5 & 0xffff) << 0)
1206 );
York Sun66869f92015-03-19 09:30:26 -07001207
York Sun8a514292015-11-04 10:03:19 -08001208 /* Normally only the first enabled CS use 0x500, others use 0x400
1209 * But when four chip-selects are all enabled, all mode registers
1210 * need 0x500 to park.
1211 */
York Sun66869f92015-03-19 09:30:26 -07001212
York Sunc0c32af2018-01-29 09:44:35 -08001213 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
York Sun34e026f2014-03-27 17:54:47 -07001214 if (unq_mrs_en) { /* unique mode registers are supported */
1215 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sun6b95be22015-03-19 09:30:27 -07001216 if (!rtt_park &&
1217 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1218 esdmode5 |= 0x00000500; /* RTT_PARK */
York Sun8a514292015-11-04 10:03:19 -08001219 rtt_park = four_cs ? 0 : 1;
York Sun6b95be22015-03-19 09:30:27 -07001220 } else {
1221 esdmode5 = 0x00000400;
1222 }
Shengzhou Liueb118802016-03-10 17:36:56 +08001223
York Sun426230a2018-01-29 09:44:33 -08001224 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1225 ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1226 !popts->registered_dimm_en)) {
Shengzhou Liueb118802016-03-10 17:36:56 +08001227 if (mclk_ps >= 935) {
1228 /* for DDR4-1600/1866/2133 */
1229 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1230 } else if (mclk_ps >= 833) {
1231 /* for DDR4-2400 */
1232 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1233 } else {
1234 printf("parity: mclk_ps = %d not supported\n",
1235 mclk_ps);
1236 }
1237 }
1238
York Sun34e026f2014-03-27 17:54:47 -07001239 switch (i) {
1240 case 1:
1241 ddr->ddr_sdram_mode_11 = (0
1242 | ((esdmode4 & 0xFFFF) << 16)
1243 | ((esdmode5 & 0xFFFF) << 0)
1244 );
1245 break;
1246 case 2:
1247 ddr->ddr_sdram_mode_13 = (0
1248 | ((esdmode4 & 0xFFFF) << 16)
1249 | ((esdmode5 & 0xFFFF) << 0)
1250 );
1251 break;
1252 case 3:
1253 ddr->ddr_sdram_mode_15 = (0
1254 | ((esdmode4 & 0xFFFF) << 16)
1255 | ((esdmode5 & 0xFFFF) << 0)
1256 );
1257 break;
1258 }
1259 }
1260 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1261 ddr->ddr_sdram_mode_11);
1262 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1263 ddr->ddr_sdram_mode_13);
1264 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1265 ddr->ddr_sdram_mode_15);
1266 }
1267}
1268
1269/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
York Sun03e664d2015-01-06 13:18:50 -08001270static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1271 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001272 const memctl_options_t *popts,
1273 const common_timing_params_t *common_dimm,
1274 const unsigned int unq_mrs_en)
1275{
1276 int i;
1277 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1278 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
York Sun03e664d2015-01-06 13:18:50 -08001279 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
York Sun34e026f2014-03-27 17:54:47 -07001280
1281 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1282
York Sun0fb71972015-11-04 10:03:18 -08001283 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1284 esdmode6 |= 1 << 6; /* Range 2 */
1285
York Sun34e026f2014-03-27 17:54:47 -07001286 ddr->ddr_sdram_mode_10 = (0
1287 | ((esdmode6 & 0xffff) << 16)
1288 | ((esdmode7 & 0xffff) << 0)
1289 );
York Sunc0c32af2018-01-29 09:44:35 -08001290 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
York Sun34e026f2014-03-27 17:54:47 -07001291 if (unq_mrs_en) { /* unique mode registers are supported */
1292 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1293 switch (i) {
1294 case 1:
1295 ddr->ddr_sdram_mode_12 = (0
1296 | ((esdmode6 & 0xFFFF) << 16)
1297 | ((esdmode7 & 0xFFFF) << 0)
1298 );
1299 break;
1300 case 2:
1301 ddr->ddr_sdram_mode_14 = (0
1302 | ((esdmode6 & 0xFFFF) << 16)
1303 | ((esdmode7 & 0xFFFF) << 0)
1304 );
1305 break;
1306 case 3:
1307 ddr->ddr_sdram_mode_16 = (0
1308 | ((esdmode6 & 0xFFFF) << 16)
1309 | ((esdmode7 & 0xFFFF) << 0)
1310 );
1311 break;
1312 }
1313 }
1314 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1315 ddr->ddr_sdram_mode_12);
1316 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1317 ddr->ddr_sdram_mode_14);
1318 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1319 ddr->ddr_sdram_mode_16);
1320 }
1321}
1322
1323#endif
1324
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001325/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
York Sun03e664d2015-01-06 13:18:50 -08001326static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1327 fsl_ddr_cfg_regs_t *ddr,
1328 const memctl_options_t *popts,
1329 const common_timing_params_t *common_dimm)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001330{
1331 unsigned int refint; /* Refresh interval */
1332 unsigned int bstopre; /* Precharge interval */
1333
York Sun03e664d2015-01-06 13:18:50 -08001334 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001335
1336 bstopre = popts->bstopre;
1337
1338 /* refint field used 0x3FFF in earlier controllers */
1339 ddr->ddr_sdram_interval = (0
1340 | ((refint & 0xFFFF) << 16)
1341 | ((bstopre & 0x3FFF) << 0)
1342 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001343 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001344}
1345
York Sun34e026f2014-03-27 17:54:47 -07001346#ifdef CONFIG_SYS_FSL_DDR4
Dave Liuc360cea2009-03-14 12:48:30 +08001347/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
York Sun03e664d2015-01-06 13:18:50 -08001348static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1349 fsl_ddr_cfg_regs_t *ddr,
Dave Liuc360cea2009-03-14 12:48:30 +08001350 const memctl_options_t *popts,
1351 const common_timing_params_t *common_dimm,
1352 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001353 unsigned int additive_latency,
1354 const unsigned int unq_mrs_en)
Dave Liuc360cea2009-03-14 12:48:30 +08001355{
York Sun34e026f2014-03-27 17:54:47 -07001356 int i;
1357 unsigned short esdmode; /* Extended SDRAM mode */
1358 unsigned short sdmode; /* SDRAM mode */
1359
1360 /* Mode Register - MR1 */
1361 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1362 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1363 unsigned int rtt;
1364 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1365 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1366 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1367 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1368 0=Disable (Test/Debug) */
1369
1370 /* Mode Register - MR0 */
1371 unsigned int wr = 0; /* Write Recovery */
1372 unsigned int dll_rst; /* DLL Reset */
1373 unsigned int mode; /* Normal=0 or Test=1 */
1374 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1375 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1376 unsigned int bt;
1377 unsigned int bl; /* BL: Burst Length */
1378
1379 unsigned int wr_mclk;
1380 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1381 static const u8 wr_table[] = {
1382 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1383 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1384 static const u8 cas_latency_table[] = {
1385 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1386 9, 9, 10, 10, 11, 11};
1387
1388 if (popts->rtt_override)
1389 rtt = popts->rtt_override_value;
1390 else
1391 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1392
1393 if (additive_latency == (cas_latency - 1))
1394 al = 1;
1395 if (additive_latency == (cas_latency - 2))
1396 al = 2;
1397
1398 if (popts->quad_rank_present)
1399 dic = 1; /* output driver impedance 240/7 ohm */
1400
1401 /*
1402 * The esdmode value will also be used for writing
1403 * MR1 during write leveling for DDR3, although the
1404 * bits specifically related to the write leveling
1405 * scheme will be handled automatically by the DDR
1406 * controller. so we set the wrlvl_en = 0 here.
1407 */
1408 esdmode = (0
1409 | ((qoff & 0x1) << 12)
1410 | ((tdqs_en & 0x1) << 11)
1411 | ((rtt & 0x7) << 8)
1412 | ((wrlvl_en & 0x1) << 7)
1413 | ((al & 0x3) << 3)
1414 | ((dic & 0x3) << 1) /* DIC field is split */
1415 | ((dll_en & 0x1) << 0)
1416 );
1417
1418 /*
1419 * DLL control for precharge PD
1420 * 0=slow exit DLL off (tXPDLL)
1421 * 1=fast exit DLL on (tXP)
1422 */
1423
York Sun03e664d2015-01-06 13:18:50 -08001424 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
York Sun34e026f2014-03-27 17:54:47 -07001425 if (wr_mclk <= 24) {
1426 wr = wr_table[wr_mclk - 10];
1427 } else {
1428 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1429 wr_mclk);
1430 }
1431
1432 dll_rst = 0; /* dll no reset */
1433 mode = 0; /* normal mode */
1434
1435 /* look up table to get the cas latency bits */
1436 if (cas_latency >= 9 && cas_latency <= 24)
1437 caslat = cas_latency_table[cas_latency - 9];
1438 else
1439 printf("Error: unsupported cas latency for mode register\n");
1440
1441 bt = 0; /* Nibble sequential */
1442
1443 switch (popts->burst_length) {
1444 case DDR_BL8:
1445 bl = 0;
1446 break;
1447 case DDR_OTF:
1448 bl = 1;
1449 break;
1450 case DDR_BC4:
1451 bl = 2;
1452 break;
1453 default:
1454 printf("Error: invalid burst length of %u specified. ",
1455 popts->burst_length);
1456 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1457 bl = 1;
1458 break;
1459 }
1460
1461 sdmode = (0
1462 | ((wr & 0x7) << 9)
1463 | ((dll_rst & 0x1) << 8)
1464 | ((mode & 0x1) << 7)
1465 | (((caslat >> 1) & 0x7) << 4)
1466 | ((bt & 0x1) << 3)
1467 | ((caslat & 1) << 2)
1468 | ((bl & 0x3) << 0)
1469 );
1470
1471 ddr->ddr_sdram_mode = (0
1472 | ((esdmode & 0xFFFF) << 16)
1473 | ((sdmode & 0xFFFF) << 0)
1474 );
1475
1476 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1477
1478 if (unq_mrs_en) { /* unique mode registers are supported */
1479 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1480 if (popts->rtt_override)
1481 rtt = popts->rtt_override_value;
1482 else
1483 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1484
1485 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1486 esdmode |= (rtt & 0x7) << 8;
1487 switch (i) {
1488 case 1:
1489 ddr->ddr_sdram_mode_3 = (0
1490 | ((esdmode & 0xFFFF) << 16)
1491 | ((sdmode & 0xFFFF) << 0)
1492 );
1493 break;
1494 case 2:
1495 ddr->ddr_sdram_mode_5 = (0
1496 | ((esdmode & 0xFFFF) << 16)
1497 | ((sdmode & 0xFFFF) << 0)
1498 );
1499 break;
1500 case 3:
1501 ddr->ddr_sdram_mode_7 = (0
1502 | ((esdmode & 0xFFFF) << 16)
1503 | ((sdmode & 0xFFFF) << 0)
1504 );
1505 break;
1506 }
1507 }
1508 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1509 ddr->ddr_sdram_mode_3);
1510 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1511 ddr->ddr_sdram_mode_5);
1512 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1513 ddr->ddr_sdram_mode_5);
1514 }
1515}
1516
1517#elif defined(CONFIG_SYS_FSL_DDR3)
1518/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
York Sun03e664d2015-01-06 13:18:50 -08001519static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1520 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07001521 const memctl_options_t *popts,
1522 const common_timing_params_t *common_dimm,
1523 unsigned int cas_latency,
1524 unsigned int additive_latency,
1525 const unsigned int unq_mrs_en)
1526{
1527 int i;
Dave Liuc360cea2009-03-14 12:48:30 +08001528 unsigned short esdmode; /* Extended SDRAM mode */
1529 unsigned short sdmode; /* SDRAM mode */
1530
1531 /* Mode Register - MR1 */
1532 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1533 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1534 unsigned int rtt;
1535 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1536 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
York Sune1fd16b2011-01-10 12:03:00 +00001537 unsigned int dic = 0; /* Output driver impedance, 40ohm */
Dave Liuc360cea2009-03-14 12:48:30 +08001538 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1539 1=Disable (Test/Debug) */
1540
1541 /* Mode Register - MR0 */
1542 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
York Sunfcea3062012-08-17 08:22:38 +00001543 unsigned int wr = 0; /* Write Recovery */
Dave Liuc360cea2009-03-14 12:48:30 +08001544 unsigned int dll_rst; /* DLL Reset */
1545 unsigned int mode; /* Normal=0 or Test=1 */
1546 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1547 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1548 unsigned int bt;
1549 unsigned int bl; /* BL: Burst Length */
1550
1551 unsigned int wr_mclk;
York Sunf5b6fb72011-03-02 14:24:11 -08001552 /*
1553 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1554 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1555 * for this table
1556 */
1557 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
Dave Liuc360cea2009-03-14 12:48:30 +08001558
Dave Liuc360cea2009-03-14 12:48:30 +08001559 if (popts->rtt_override)
1560 rtt = popts->rtt_override_value;
York Sune1fd16b2011-01-10 12:03:00 +00001561 else
1562 rtt = popts->cs_local_opts[0].odt_rtt_norm;
Dave Liuc360cea2009-03-14 12:48:30 +08001563
1564 if (additive_latency == (cas_latency - 1))
1565 al = 1;
1566 if (additive_latency == (cas_latency - 2))
1567 al = 2;
1568
York Sune1fd16b2011-01-10 12:03:00 +00001569 if (popts->quad_rank_present)
1570 dic = 1; /* output driver impedance 240/7 ohm */
1571
Dave Liuc360cea2009-03-14 12:48:30 +08001572 /*
1573 * The esdmode value will also be used for writing
1574 * MR1 during write leveling for DDR3, although the
1575 * bits specifically related to the write leveling
1576 * scheme will be handled automatically by the DDR
1577 * controller. so we set the wrlvl_en = 0 here.
1578 */
1579 esdmode = (0
1580 | ((qoff & 0x1) << 12)
1581 | ((tdqs_en & 0x1) << 11)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001582 | ((rtt & 0x4) << 7) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001583 | ((wrlvl_en & 0x1) << 7)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001584 | ((rtt & 0x2) << 5) /* rtt field is split */
1585 | ((dic & 0x2) << 4) /* DIC field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001586 | ((al & 0x3) << 3)
Kumar Gala6d8565a2009-09-10 14:54:55 -05001587 | ((rtt & 0x1) << 2) /* rtt field is split */
Dave Liuc360cea2009-03-14 12:48:30 +08001588 | ((dic & 0x1) << 1) /* DIC field is split */
1589 | ((dll_en & 0x1) << 0)
1590 );
1591
1592 /*
1593 * DLL control for precharge PD
1594 * 0=slow exit DLL off (tXPDLL)
1595 * 1=fast exit DLL on (tXP)
1596 */
1597 dll_on = 1;
York Sunf5b6fb72011-03-02 14:24:11 -08001598
York Sun03e664d2015-01-06 13:18:50 -08001599 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
York Sunfcea3062012-08-17 08:22:38 +00001600 if (wr_mclk <= 16) {
1601 wr = wr_table[wr_mclk - 5];
1602 } else {
1603 printf("Error: unsupported write recovery for mode register "
1604 "wr_mclk = %d\n", wr_mclk);
1605 }
York Sunf5b6fb72011-03-02 14:24:11 -08001606
Dave Liuc360cea2009-03-14 12:48:30 +08001607 dll_rst = 0; /* dll no reset */
1608 mode = 0; /* normal mode */
1609
1610 /* look up table to get the cas latency bits */
York Sunfcea3062012-08-17 08:22:38 +00001611 if (cas_latency >= 5 && cas_latency <= 16) {
1612 unsigned char cas_latency_table[] = {
Dave Liuc360cea2009-03-14 12:48:30 +08001613 0x2, /* 5 clocks */
1614 0x4, /* 6 clocks */
1615 0x6, /* 7 clocks */
1616 0x8, /* 8 clocks */
1617 0xa, /* 9 clocks */
1618 0xc, /* 10 clocks */
York Sunfcea3062012-08-17 08:22:38 +00001619 0xe, /* 11 clocks */
1620 0x1, /* 12 clocks */
1621 0x3, /* 13 clocks */
1622 0x5, /* 14 clocks */
1623 0x7, /* 15 clocks */
1624 0x9, /* 16 clocks */
Dave Liuc360cea2009-03-14 12:48:30 +08001625 };
1626 caslat = cas_latency_table[cas_latency - 5];
York Sunfcea3062012-08-17 08:22:38 +00001627 } else {
1628 printf("Error: unsupported cas latency for mode register\n");
Dave Liuc360cea2009-03-14 12:48:30 +08001629 }
York Sunfcea3062012-08-17 08:22:38 +00001630
Dave Liuc360cea2009-03-14 12:48:30 +08001631 bt = 0; /* Nibble sequential */
1632
1633 switch (popts->burst_length) {
1634 case DDR_BL8:
1635 bl = 0;
1636 break;
1637 case DDR_OTF:
1638 bl = 1;
1639 break;
1640 case DDR_BC4:
1641 bl = 2;
1642 break;
1643 default:
1644 printf("Error: invalid burst length of %u specified. "
1645 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1646 popts->burst_length);
1647 bl = 1;
1648 break;
1649 }
1650
1651 sdmode = (0
1652 | ((dll_on & 0x1) << 12)
1653 | ((wr & 0x7) << 9)
1654 | ((dll_rst & 0x1) << 8)
1655 | ((mode & 0x1) << 7)
1656 | (((caslat >> 1) & 0x7) << 4)
1657 | ((bt & 0x1) << 3)
York Sunfcea3062012-08-17 08:22:38 +00001658 | ((caslat & 1) << 2)
Dave Liuc360cea2009-03-14 12:48:30 +08001659 | ((bl & 0x3) << 0)
1660 );
1661
1662 ddr->ddr_sdram_mode = (0
1663 | ((esdmode & 0xFFFF) << 16)
1664 | ((sdmode & 0xFFFF) << 0)
1665 );
1666
1667 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
York Sune1fd16b2011-01-10 12:03:00 +00001668
1669 if (unq_mrs_en) { /* unique mode registers are supported */
Kumar Galadea7f882011-11-09 10:05:10 -06001670 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sune1fd16b2011-01-10 12:03:00 +00001671 if (popts->rtt_override)
1672 rtt = popts->rtt_override_value;
1673 else
1674 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1675
1676 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1677 esdmode |= (0
1678 | ((rtt & 0x4) << 7) /* rtt field is split */
1679 | ((rtt & 0x2) << 5) /* rtt field is split */
1680 | ((rtt & 0x1) << 2) /* rtt field is split */
1681 );
1682 switch (i) {
1683 case 1:
1684 ddr->ddr_sdram_mode_3 = (0
1685 | ((esdmode & 0xFFFF) << 16)
1686 | ((sdmode & 0xFFFF) << 0)
1687 );
1688 break;
1689 case 2:
1690 ddr->ddr_sdram_mode_5 = (0
1691 | ((esdmode & 0xFFFF) << 16)
1692 | ((sdmode & 0xFFFF) << 0)
1693 );
1694 break;
1695 case 3:
1696 ddr->ddr_sdram_mode_7 = (0
1697 | ((esdmode & 0xFFFF) << 16)
1698 | ((sdmode & 0xFFFF) << 0)
1699 );
1700 break;
1701 }
1702 }
1703 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1704 ddr->ddr_sdram_mode_3);
1705 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1706 ddr->ddr_sdram_mode_5);
1707 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1708 ddr->ddr_sdram_mode_5);
1709 }
Dave Liuc360cea2009-03-14 12:48:30 +08001710}
1711
York Sun5614e712013-09-30 09:22:09 -07001712#else /* !CONFIG_SYS_FSL_DDR3 */
Dave Liuc360cea2009-03-14 12:48:30 +08001713
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001714/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
York Sun03e664d2015-01-06 13:18:50 -08001715static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1716 fsl_ddr_cfg_regs_t *ddr,
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001717 const memctl_options_t *popts,
1718 const common_timing_params_t *common_dimm,
1719 unsigned int cas_latency,
York Sune1fd16b2011-01-10 12:03:00 +00001720 unsigned int additive_latency,
1721 const unsigned int unq_mrs_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001722{
1723 unsigned short esdmode; /* Extended SDRAM mode */
1724 unsigned short sdmode; /* SDRAM mode */
1725
1726 /*
1727 * FIXME: This ought to be pre-calculated in a
1728 * technology-specific routine,
1729 * e.g. compute_DDR2_mode_register(), and then the
1730 * sdmode and esdmode passed in as part of common_dimm.
1731 */
1732
1733 /* Extended Mode Register */
1734 unsigned int mrs = 0; /* Mode Register Set */
1735 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1736 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1737 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1738 unsigned int ocd = 0; /* 0x0=OCD not supported,
1739 0x7=OCD default state */
1740 unsigned int rtt;
1741 unsigned int al; /* Posted CAS# additive latency (AL) */
1742 unsigned int ods = 0; /* Output Drive Strength:
1743 0 = Full strength (18ohm)
1744 1 = Reduced strength (4ohm) */
1745 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1746 1=Disable (Test/Debug) */
1747
1748 /* Mode Register (MR) */
1749 unsigned int mr; /* Mode Register Definition */
1750 unsigned int pd; /* Power-Down Mode */
1751 unsigned int wr; /* Write Recovery */
1752 unsigned int dll_res; /* DLL Reset */
1753 unsigned int mode; /* Normal=0 or Test=1 */
Kumar Gala302e52e2008-09-05 14:40:29 -05001754 unsigned int caslat = 0;/* CAS# latency */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001755 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1756 unsigned int bt;
1757 unsigned int bl; /* BL: Burst Length */
1758
Priyanka Jain0dd38a32013-09-25 10:41:19 +05301759 dqs_en = !popts->dqs_config;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001760 rtt = fsl_ddr_get_rtt();
1761
1762 al = additive_latency;
1763
1764 esdmode = (0
1765 | ((mrs & 0x3) << 14)
1766 | ((outputs & 0x1) << 12)
1767 | ((rdqs_en & 0x1) << 11)
1768 | ((dqs_en & 0x1) << 10)
1769 | ((ocd & 0x7) << 7)
1770 | ((rtt & 0x2) << 5) /* rtt field is split */
1771 | ((al & 0x7) << 3)
1772 | ((rtt & 0x1) << 2) /* rtt field is split */
1773 | ((ods & 0x1) << 1)
1774 | ((dll_en & 0x1) << 0)
1775 );
1776
1777 mr = 0; /* FIXME: CHECKME */
1778
1779 /*
1780 * 0 = Fast Exit (Normal)
1781 * 1 = Slow Exit (Low Power)
1782 */
1783 pd = 0;
1784
York Sun5614e712013-09-30 09:22:09 -07001785#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001786 wr = 0; /* Historical */
York Sun5614e712013-09-30 09:22:09 -07001787#elif defined(CONFIG_SYS_FSL_DDR2)
York Sun03e664d2015-01-06 13:18:50 -08001788 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001789#endif
1790 dll_res = 0;
1791 mode = 0;
1792
York Sun5614e712013-09-30 09:22:09 -07001793#if defined(CONFIG_SYS_FSL_DDR1)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001794 if (1 <= cas_latency && cas_latency <= 4) {
1795 unsigned char mode_caslat_table[4] = {
1796 0x5, /* 1.5 clocks */
1797 0x2, /* 2.0 clocks */
1798 0x6, /* 2.5 clocks */
1799 0x3 /* 3.0 clocks */
1800 };
Kumar Gala302e52e2008-09-05 14:40:29 -05001801 caslat = mode_caslat_table[cas_latency - 1];
1802 } else {
1803 printf("Warning: unknown cas_latency %d\n", cas_latency);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001804 }
York Sun5614e712013-09-30 09:22:09 -07001805#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001806 caslat = cas_latency;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001807#endif
1808 bt = 0;
1809
1810 switch (popts->burst_length) {
Dave Liuc360cea2009-03-14 12:48:30 +08001811 case DDR_BL4:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001812 bl = 2;
1813 break;
Dave Liuc360cea2009-03-14 12:48:30 +08001814 case DDR_BL8:
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001815 bl = 3;
1816 break;
1817 default:
1818 printf("Error: invalid burst length of %u specified. "
1819 " Defaulting to 4 beats.\n",
1820 popts->burst_length);
1821 bl = 2;
1822 break;
1823 }
1824
1825 sdmode = (0
1826 | ((mr & 0x3) << 14)
1827 | ((pd & 0x1) << 12)
1828 | ((wr & 0x7) << 9)
1829 | ((dll_res & 0x1) << 8)
1830 | ((mode & 0x1) << 7)
1831 | ((caslat & 0x7) << 4)
1832 | ((bt & 0x1) << 3)
1833 | ((bl & 0x7) << 0)
1834 );
1835
1836 ddr->ddr_sdram_mode = (0
1837 | ((esdmode & 0xFFFF) << 16)
1838 | ((sdmode & 0xFFFF) << 0)
1839 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001840 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001841}
Dave Liuc360cea2009-03-14 12:48:30 +08001842#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001843
1844/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1845static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1846{
1847 unsigned int init_value; /* Initialization value */
1848
Anatolij Gustschin5b933942013-01-21 23:50:27 +00001849#ifdef CONFIG_MEM_INIT_VALUE
1850 init_value = CONFIG_MEM_INIT_VALUE;
1851#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001852 init_value = 0xDEADBEEF;
Anatolij Gustschin5b933942013-01-21 23:50:27 +00001853#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001854 ddr->ddr_data_init = init_value;
1855}
1856
1857/*
1858 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1859 * The old controller on the 8540/60 doesn't have this register.
1860 * Hope it's OK to set it (to 0) anyway.
1861 */
1862static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1863 const memctl_options_t *popts)
1864{
1865 unsigned int clk_adjust; /* Clock adjust */
Curt Bruned7c865b2015-02-13 10:57:11 -08001866 unsigned int ss_en = 0; /* Source synchronous enable */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001867
York Sun3c3d8ab2016-11-16 11:23:23 -08001868#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
Curt Bruned7c865b2015-02-13 10:57:11 -08001869 /* Per FSL Application Note: AN2805 */
1870 ss_en = 1;
1871#endif
Shengzhou Liud8e51632016-05-04 10:20:21 +08001872 if (fsl_ddr_get_version(0) >= 0x40701) {
1873 /* clk_adjust in 5-bits on T-series and LS-series */
1874 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1875 } else {
1876 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1877 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1878 }
1879
Curt Bruned7c865b2015-02-13 10:57:11 -08001880 ddr->ddr_sdram_clk_cntl = (0
1881 | ((ss_en & 0x1) << 31)
Shengzhou Liud8e51632016-05-04 10:20:21 +08001882 | clk_adjust
Curt Bruned7c865b2015-02-13 10:57:11 -08001883 );
york9490ff42010-07-02 22:25:55 +00001884 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001885}
1886
1887/* DDR Initialization Address (DDR_INIT_ADDR) */
1888static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1889{
1890 unsigned int init_addr = 0; /* Initialization address */
1891
1892 ddr->ddr_init_addr = init_addr;
1893}
1894
1895/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1896static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1897{
1898 unsigned int uia = 0; /* Use initialization address */
1899 unsigned int init_ext_addr = 0; /* Initialization address */
1900
1901 ddr->ddr_init_ext_addr = (0
1902 | ((uia & 0x1) << 31)
1903 | (init_ext_addr & 0xF)
1904 );
1905}
1906
1907/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
Dave Liuec145e82010-03-05 12:22:00 +08001908static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1909 const memctl_options_t *popts)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001910{
1911 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1912 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1913 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1914 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
York Sun6c6e0062015-11-04 10:03:21 -08001915 unsigned int trwt_mclk = 0; /* ext_rwt */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001916 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1917
York Sun34e026f2014-03-27 17:54:47 -07001918#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuec145e82010-03-05 12:22:00 +08001919 if (popts->burst_length == DDR_BL8) {
1920 /* We set BL/2 for fixed BL8 */
1921 rrt = 0; /* BL/2 clocks */
1922 wwt = 0; /* BL/2 clocks */
1923 } else {
1924 /* We need to set BL/2 + 2 to BC4 and OTF */
1925 rrt = 2; /* BL/2 + 2 clocks */
1926 wwt = 2; /* BL/2 + 2 clocks */
1927 }
York Sun34e026f2014-03-27 17:54:47 -07001928#endif
York Sun34e026f2014-03-27 17:54:47 -07001929#ifdef CONFIG_SYS_FSL_DDR4
1930 dll_lock = 2; /* tDLLK = 1024 clocks */
1931#elif defined(CONFIG_SYS_FSL_DDR3)
Dave Liuc360cea2009-03-14 12:48:30 +08001932 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1933#endif
York Sun6c6e0062015-11-04 10:03:21 -08001934
1935 if (popts->trwt_override)
1936 trwt_mclk = popts->trwt;
1937
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001938 ddr->timing_cfg_4 = (0
1939 | ((rwt & 0xf) << 28)
1940 | ((wrt & 0xf) << 24)
1941 | ((rrt & 0xf) << 20)
1942 | ((wwt & 0xf) << 16)
York Sun6c6e0062015-11-04 10:03:21 -08001943 | ((trwt_mclk & 0xc) << 12)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001944 | (dll_lock & 0x3)
1945 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001946 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001947}
1948
1949/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
York Sune1fd16b2011-01-10 12:03:00 +00001950static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001951{
1952 unsigned int rodt_on = 0; /* Read to ODT on */
1953 unsigned int rodt_off = 0; /* Read to ODT off */
1954 unsigned int wodt_on = 0; /* Write to ODT on */
1955 unsigned int wodt_off = 0; /* Write to ODT off */
1956
York Sun34e026f2014-03-27 17:54:47 -07001957#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1958 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1959 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
York Sune1fd16b2011-01-10 12:03:00 +00001960 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
York Sun34e026f2014-03-27 17:54:47 -07001961 if (cas_latency >= wr_lat)
1962 rodt_on = cas_latency - wr_lat + 1;
Dave Liuc360cea2009-03-14 12:48:30 +08001963 rodt_off = 4; /* 4 clocks */
york5fb8a8a2010-07-02 22:25:56 +00001964 wodt_on = 1; /* 1 clocks */
Dave Liuc360cea2009-03-14 12:48:30 +08001965 wodt_off = 4; /* 4 clocks */
1966#endif
1967
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001968 ddr->timing_cfg_5 = (0
Dave Liu22ff3d02008-11-21 16:31:29 +08001969 | ((rodt_on & 0x1f) << 24)
1970 | ((rodt_off & 0x7) << 20)
1971 | ((wodt_on & 0x1f) << 12)
1972 | ((wodt_off & 0x7) << 8)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001973 );
Haiying Wang1f293b42008-10-03 12:37:26 -04001974 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001975}
1976
York Sun34e026f2014-03-27 17:54:47 -07001977#ifdef CONFIG_SYS_FSL_DDR4
1978static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1979{
1980 unsigned int hs_caslat = 0;
1981 unsigned int hs_wrlat = 0;
1982 unsigned int hs_wrrec = 0;
1983 unsigned int hs_clkadj = 0;
1984 unsigned int hs_wrlvl_start = 0;
1985
1986 ddr->timing_cfg_6 = (0
1987 | ((hs_caslat & 0x1f) << 24)
1988 | ((hs_wrlat & 0x1f) << 19)
1989 | ((hs_wrrec & 0x1f) << 12)
1990 | ((hs_clkadj & 0x1f) << 6)
1991 | ((hs_wrlvl_start & 0x1f) << 0)
1992 );
1993 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1994}
1995
York Sun03e664d2015-01-06 13:18:50 -08001996static void set_timing_cfg_7(const unsigned int ctrl_num,
1997 fsl_ddr_cfg_regs_t *ddr,
York Sun426230a2018-01-29 09:44:33 -08001998 const memctl_options_t *popts,
York Sun03e664d2015-01-06 13:18:50 -08001999 const common_timing_params_t *common_dimm)
York Sun34e026f2014-03-27 17:54:47 -07002000{
2001 unsigned int txpr, tcksre, tcksrx;
Shengzhou Liueb118802016-03-10 17:36:56 +08002002 unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
2003 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sun34e026f2014-03-27 17:54:47 -07002004
York Sun03e664d2015-01-06 13:18:50 -08002005 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
2006 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
2007 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
Shengzhou Liueb118802016-03-10 17:36:56 +08002008
York Sun426230a2018-01-29 09:44:33 -08002009 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
2010 CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
2011 /* for DDR4 only */
York Sunc0c32af2018-01-29 09:44:35 -08002012 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
York Sun426230a2018-01-29 09:44:33 -08002013 debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
Shengzhou Liueb118802016-03-10 17:36:56 +08002014 }
2015
York Sun34e026f2014-03-27 17:54:47 -07002016 cs_to_cmd = 0;
2017
2018 if (txpr <= 200)
2019 cke_rst = 0;
2020 else if (txpr <= 256)
2021 cke_rst = 1;
2022 else if (txpr <= 512)
2023 cke_rst = 2;
2024 else
2025 cke_rst = 3;
2026
2027 if (tcksre <= 19)
2028 cksre = tcksre - 5;
2029 else
2030 cksre = 15;
2031
2032 if (tcksrx <= 19)
2033 cksrx = tcksrx - 5;
2034 else
2035 cksrx = 15;
2036
2037 ddr->timing_cfg_7 = (0
2038 | ((cke_rst & 0x3) << 28)
2039 | ((cksre & 0xf) << 24)
2040 | ((cksrx & 0xf) << 20)
2041 | ((par_lat & 0xf) << 16)
2042 | ((cs_to_cmd & 0xf) << 4)
2043 );
2044 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2045}
2046
York Sun03e664d2015-01-06 13:18:50 -08002047static void set_timing_cfg_8(const unsigned int ctrl_num,
2048 fsl_ddr_cfg_regs_t *ddr,
York Sun34e026f2014-03-27 17:54:47 -07002049 const memctl_options_t *popts,
2050 const common_timing_params_t *common_dimm,
2051 unsigned int cas_latency)
2052{
York Sun426230a2018-01-29 09:44:33 -08002053 int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
York Sun34e026f2014-03-27 17:54:47 -07002054 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
York Sun426230a2018-01-29 09:44:33 -08002055 int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2056 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2057 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
York Sun34e026f2014-03-27 17:54:47 -07002058
2059 rwt_bg = cas_latency + 2 + 4 - wr_lat;
2060 if (rwt_bg < tccdl)
2061 rwt_bg = tccdl - rwt_bg;
2062 else
2063 rwt_bg = 0;
2064
2065 wrt_bg = wr_lat + 4 + 1 - cas_latency;
2066 if (wrt_bg < tccdl)
2067 wrt_bg = tccdl - wrt_bg;
2068 else
2069 wrt_bg = 0;
2070
2071 if (popts->burst_length == DDR_BL8) {
2072 rrt_bg = tccdl - 4;
2073 wwt_bg = tccdl - 4;
2074 } else {
2075 rrt_bg = tccdl - 2;
York Sundc1437a2015-01-06 13:18:52 -08002076 wwt_bg = tccdl - 2;
York Sun34e026f2014-03-27 17:54:47 -07002077 }
2078
York Sun03e664d2015-01-06 13:18:50 -08002079 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2080 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
York Sun3d75ec92014-06-26 11:14:44 -07002081 if (popts->otf_burst_chop_en)
2082 wrtord_bg += 2;
2083
York Sun34e026f2014-03-27 17:54:47 -07002084 pre_all_rec = 0;
2085
2086 ddr->timing_cfg_8 = (0
2087 | ((rwt_bg & 0xf) << 28)
2088 | ((wrt_bg & 0xf) << 24)
2089 | ((rrt_bg & 0xf) << 20)
2090 | ((wwt_bg & 0xf) << 16)
2091 | ((acttoact_bg & 0xf) << 12)
2092 | ((wrtord_bg & 0xf) << 8)
2093 | ((pre_all_rec & 0x1f) << 0)
2094 );
2095
2096 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2097}
2098
York Sunc0c32af2018-01-29 09:44:35 -08002099static void set_timing_cfg_9(const unsigned int ctrl_num,
2100 fsl_ddr_cfg_regs_t *ddr,
2101 const memctl_options_t *popts,
2102 const common_timing_params_t *common_dimm)
York Sun34e026f2014-03-27 17:54:47 -07002103{
York Sunc0c32af2018-01-29 09:44:35 -08002104 unsigned int refrec_cid_mclk = 0;
2105 unsigned int acttoact_cid_mclk = 0;
2106
2107 if (popts->package_3ds) {
2108 refrec_cid_mclk =
2109 picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);
2110 acttoact_cid_mclk = 4U; /* tRRDS_slr */
2111 }
2112
2113 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 |
2114 (acttoact_cid_mclk & 0xf) << 8;
2115
York Sun34e026f2014-03-27 17:54:47 -07002116 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2117}
2118
York Sunf80d6472014-09-11 13:32:06 -07002119/* This function needs to be called after set_ddr_sdram_cfg() is called */
York Sun34e026f2014-03-27 17:54:47 -07002120static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2121 const dimm_params_t *dimm_params)
2122{
York Sunf80d6472014-09-11 13:32:06 -07002123 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
York Sun6b95be22015-03-19 09:30:27 -07002124 int i;
York Sunf80d6472014-09-11 13:32:06 -07002125
York Sun6b95be22015-03-19 09:30:27 -07002126 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2127 if (dimm_params[i].n_ranks)
2128 break;
2129 }
2130 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2131 puts("DDR error: no DIMM found!\n");
2132 return;
2133 }
York Sun34e026f2014-03-27 17:54:47 -07002134
York Sun6b95be22015-03-19 09:30:27 -07002135 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2136 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2137 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2138 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2139 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
York Sun34e026f2014-03-27 17:54:47 -07002140
York Sun6b95be22015-03-19 09:30:27 -07002141 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2142 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2143 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2144 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2145 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2146
2147 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2148 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2149 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2150 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2151 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
York Sun34e026f2014-03-27 17:54:47 -07002152
York Sunf80d6472014-09-11 13:32:06 -07002153 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
York Sun6b95be22015-03-19 09:30:27 -07002154 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2155 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
York Sunf80d6472014-09-11 13:32:06 -07002156 (acc_ecc_en ? 0 :
York Sun6b95be22015-03-19 09:30:27 -07002157 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2158 dimm_params[i].dq_mapping_ors;
York Sun34e026f2014-03-27 17:54:47 -07002159
2160 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2161 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2162 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2163 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2164}
2165static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2166 const memctl_options_t *popts)
2167{
2168 int rd_pre;
2169
2170 rd_pre = popts->quad_rank_present ? 1 : 0;
2171
2172 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
York Sun426230a2018-01-29 09:44:33 -08002173 /* Disable MRS on parity error for RDIMMs */
2174 ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
York Sun34e026f2014-03-27 17:54:47 -07002175
York Sunc0c32af2018-01-29 09:44:35 -08002176 if (popts->package_3ds) { /* only 2,4,8 are supported */
2177 if ((popts->package_3ds + 1) & 0x1) {
2178 printf("Error: Unsupported 3DS DIMM with %d die\n",
2179 popts->package_3ds + 1);
2180 } else {
2181 ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1)
2182 << 4;
2183 }
2184 }
2185
York Sun34e026f2014-03-27 17:54:47 -07002186 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2187}
2188#endif /* CONFIG_SYS_FSL_DDR4 */
2189
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002190/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
Dave Liuc360cea2009-03-14 12:48:30 +08002191static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002192{
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002193 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2194 /* Normal Operation Full Calibration Time (tZQoper) */
2195 unsigned int zqoper = 0;
2196 /* Normal Operation Short Calibration Time (tZQCS) */
2197 unsigned int zqcs = 0;
York Sun34e026f2014-03-27 17:54:47 -07002198#ifdef CONFIG_SYS_FSL_DDR4
2199 unsigned int zqcs_init;
2200#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002201
Dave Liuc360cea2009-03-14 12:48:30 +08002202 if (zq_en) {
York Sun34e026f2014-03-27 17:54:47 -07002203#ifdef CONFIG_SYS_FSL_DDR4
2204 zqinit = 10; /* 1024 clocks */
2205 zqoper = 9; /* 512 clocks */
2206 zqcs = 7; /* 128 clocks */
2207 zqcs_init = 5; /* 1024 refresh sequences */
2208#else
Dave Liuc360cea2009-03-14 12:48:30 +08002209 zqinit = 9; /* 512 clocks */
2210 zqoper = 8; /* 256 clocks */
2211 zqcs = 6; /* 64 clocks */
York Sun34e026f2014-03-27 17:54:47 -07002212#endif
Dave Liuc360cea2009-03-14 12:48:30 +08002213 }
2214
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002215 ddr->ddr_zq_cntl = (0
2216 | ((zq_en & 0x1) << 31)
2217 | ((zqinit & 0xF) << 24)
2218 | ((zqoper & 0xF) << 16)
2219 | ((zqcs & 0xF) << 8)
York Sun34e026f2014-03-27 17:54:47 -07002220#ifdef CONFIG_SYS_FSL_DDR4
2221 | ((zqcs_init & 0xF) << 0)
2222#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002223 );
York Sune1fd16b2011-01-10 12:03:00 +00002224 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002225}
2226
2227/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
Dave Liubdc9f7b2009-12-16 10:24:37 -06002228static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2229 const memctl_options_t *popts)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002230{
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002231 /*
2232 * First DQS pulse rising edge after margining mode
2233 * is programmed (tWL_MRD)
2234 */
2235 unsigned int wrlvl_mrd = 0;
2236 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2237 unsigned int wrlvl_odten = 0;
2238 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2239 unsigned int wrlvl_dqsen = 0;
2240 /* WRLVL_SMPL: Write leveling sample time */
2241 unsigned int wrlvl_smpl = 0;
2242 /* WRLVL_WLR: Write leveling repeition time */
2243 unsigned int wrlvl_wlr = 0;
2244 /* WRLVL_START: Write leveling start time */
2245 unsigned int wrlvl_start = 0;
2246
Dave Liuc360cea2009-03-14 12:48:30 +08002247 /* suggest enable write leveling for DDR3 due to fly-by topology */
2248 if (wrlvl_en) {
2249 /* tWL_MRD min = 40 nCK, we set it 64 */
2250 wrlvl_mrd = 0x6;
2251 /* tWL_ODTEN 128 */
2252 wrlvl_odten = 0x7;
2253 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2254 wrlvl_dqsen = 0x5;
2255 /*
Dave Liubdc9f7b2009-12-16 10:24:37 -06002256 * Write leveling sample time at least need 6 clocks
2257 * higher than tWLO to allow enough time for progagation
2258 * delay and sampling the prime data bits.
Dave Liuc360cea2009-03-14 12:48:30 +08002259 */
2260 wrlvl_smpl = 0xf;
2261 /*
2262 * Write leveling repetition time
2263 * at least tWLO + 6 clocks clocks
york5fb8a8a2010-07-02 22:25:56 +00002264 * we set it 64
Dave Liuc360cea2009-03-14 12:48:30 +08002265 */
york5fb8a8a2010-07-02 22:25:56 +00002266 wrlvl_wlr = 0x6;
Dave Liuc360cea2009-03-14 12:48:30 +08002267 /*
2268 * Write leveling start time
2269 * The value use for the DQS_ADJUST for the first sample
York Sune1fd16b2011-01-10 12:03:00 +00002270 * when write leveling is enabled. It probably needs to be
Robert P. J. Day62a3b7d2016-07-15 13:44:45 -04002271 * overridden per platform.
Dave Liuc360cea2009-03-14 12:48:30 +08002272 */
2273 wrlvl_start = 0x8;
Dave Liubdc9f7b2009-12-16 10:24:37 -06002274 /*
2275 * Override the write leveling sample and start time
2276 * according to specific board
2277 */
2278 if (popts->wrlvl_override) {
2279 wrlvl_smpl = popts->wrlvl_sample;
2280 wrlvl_start = popts->wrlvl_start;
2281 }
Dave Liuc360cea2009-03-14 12:48:30 +08002282 }
2283
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002284 ddr->ddr_wrlvl_cntl = (0
2285 | ((wrlvl_en & 0x1) << 31)
2286 | ((wrlvl_mrd & 0x7) << 24)
2287 | ((wrlvl_odten & 0x7) << 20)
2288 | ((wrlvl_dqsen & 0x7) << 16)
2289 | ((wrlvl_smpl & 0xf) << 12)
2290 | ((wrlvl_wlr & 0x7) << 8)
Dave Liu22ff3d02008-11-21 16:31:29 +08002291 | ((wrlvl_start & 0x1F) << 0)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002292 );
York Sune1fd16b2011-01-10 12:03:00 +00002293 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
York Sun57495e42012-10-08 07:44:22 +00002294 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2295 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2296 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2297 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2298
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002299}
2300
2301/* DDR Self Refresh Counter (DDR_SR_CNTR) */
Dave Liu22cca7e2008-11-21 16:31:35 +08002302static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002303{
Dave Liu22cca7e2008-11-21 16:31:35 +08002304 /* Self Refresh Idle Threshold */
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002305 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2306}
2307
york7fd101c2010-07-02 22:25:54 +00002308static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2309{
2310 if (popts->addr_hash) {
2311 ddr->ddr_eor = 0x40000000; /* address hash enable */
Kumar Galac2a63f42011-03-18 11:53:06 -05002312 puts("Address hashing enabled.\n");
york7fd101c2010-07-02 22:25:54 +00002313 }
2314}
2315
York Sune1fd16b2011-01-10 12:03:00 +00002316static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2317{
2318 ddr->ddr_cdr1 = popts->ddr_cdr1;
2319 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2320}
2321
York Sun57495e42012-10-08 07:44:22 +00002322static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2323{
2324 ddr->ddr_cdr2 = popts->ddr_cdr2;
2325 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2326}
2327
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002328unsigned int
2329check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2330{
2331 unsigned int res = 0;
2332
2333 /*
2334 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2335 * not set at the same time.
2336 */
2337 if (ddr->ddr_sdram_cfg & 0x10000000
2338 && ddr->ddr_sdram_cfg & 0x00008000) {
2339 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2340 " should not be set at the same time.\n");
2341 res++;
2342 }
2343
2344 return res;
2345}
2346
2347unsigned int
York Sun03e664d2015-01-06 13:18:50 -08002348compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2349 const memctl_options_t *popts,
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002350 fsl_ddr_cfg_regs_t *ddr,
2351 const common_timing_params_t *common_dimm,
2352 const dimm_params_t *dimm_params,
Haiying Wangfc0c2b62010-12-01 10:35:31 -05002353 unsigned int dbw_cap_adj,
2354 unsigned int size_only)
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002355{
2356 unsigned int i;
2357 unsigned int cas_latency;
2358 unsigned int additive_latency;
Dave Liu22cca7e2008-11-21 16:31:35 +08002359 unsigned int sr_it;
Dave Liuc360cea2009-03-14 12:48:30 +08002360 unsigned int zq_en;
2361 unsigned int wrlvl_en;
York Sune1fd16b2011-01-10 12:03:00 +00002362 unsigned int ip_rev = 0;
2363 unsigned int unq_mrs_en = 0;
York Sun58edbc92010-10-18 13:46:50 -07002364 int cs_en = 1;
Shengzhou Liu02fb2762016-11-21 11:36:48 +08002365#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2366 unsigned int ddr_freq;
2367#endif
2368#if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
2369 defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
2370 defined(CONFIG_SYS_FSL_ERRATUM_A009942)
2371 struct ccsr_ddr __iomem *ddrc;
2372
2373 switch (ctrl_num) {
2374 case 0:
2375 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
2376 break;
York Sun51370d52016-12-28 08:43:45 -08002377#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
Shengzhou Liu02fb2762016-11-21 11:36:48 +08002378 case 1:
2379 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
2380 break;
2381#endif
York Sun51370d52016-12-28 08:43:45 -08002382#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
Shengzhou Liu02fb2762016-11-21 11:36:48 +08002383 case 2:
2384 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
2385 break;
2386#endif
York Sun51370d52016-12-28 08:43:45 -08002387#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
Shengzhou Liu02fb2762016-11-21 11:36:48 +08002388 case 3:
2389 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
2390 break;
2391#endif
2392 default:
2393 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
2394 return 1;
2395 }
2396#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002397
2398 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2399
2400 if (common_dimm == NULL) {
2401 printf("Error: subset DIMM params struct null pointer\n");
2402 return 1;
2403 }
2404
2405 /*
2406 * Process overrides first.
2407 *
2408 * FIXME: somehow add dereated caslat to this
2409 */
2410 cas_latency = (popts->cas_latency_override)
2411 ? popts->cas_latency_override_value
York Sun34e026f2014-03-27 17:54:47 -07002412 : common_dimm->lowest_common_spd_caslat;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002413
2414 additive_latency = (popts->additive_latency_override)
2415 ? popts->additive_latency_override_value
2416 : common_dimm->additive_latency;
2417
Dave Liu22cca7e2008-11-21 16:31:35 +08002418 sr_it = (popts->auto_self_refresh_en)
2419 ? popts->sr_it
2420 : 0;
Dave Liuc360cea2009-03-14 12:48:30 +08002421 /* ZQ calibration */
2422 zq_en = (popts->zq_en) ? 1 : 0;
2423 /* write leveling */
2424 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
Dave Liu22cca7e2008-11-21 16:31:35 +08002425
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002426 /* Chip Select Memory Bounds (CSn_BNDS) */
2427 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Suna4c66502012-08-17 08:22:39 +00002428 unsigned long long ea, sa;
york076bff82010-07-02 22:25:52 +00002429 unsigned int cs_per_dimm
2430 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2431 unsigned int dimm_number
2432 = i / cs_per_dimm;
2433 unsigned long long rank_density
York Suna4c66502012-08-17 08:22:39 +00002434 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002435
york076bff82010-07-02 22:25:52 +00002436 if (dimm_params[dimm_number].n_ranks == 0) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002437 debug("Skipping setup of CS%u "
york5800e7a2010-07-02 22:25:53 +00002438 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002439 continue;
2440 }
York Suna4c66502012-08-17 08:22:39 +00002441 if (popts->memctl_interleaving) {
york076bff82010-07-02 22:25:52 +00002442 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
York Suna4c66502012-08-17 08:22:39 +00002443 case FSL_DDR_CS0_CS1_CS2_CS3:
2444 break;
york076bff82010-07-02 22:25:52 +00002445 case FSL_DDR_CS0_CS1:
2446 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
York Sun58edbc92010-10-18 13:46:50 -07002447 if (i > 1)
2448 cs_en = 0;
york076bff82010-07-02 22:25:52 +00002449 break;
2450 case FSL_DDR_CS2_CS3:
York Suna4c66502012-08-17 08:22:39 +00002451 default:
York Sun58edbc92010-10-18 13:46:50 -07002452 if (i > 0)
2453 cs_en = 0;
york076bff82010-07-02 22:25:52 +00002454 break;
york076bff82010-07-02 22:25:52 +00002455 }
York Suna4c66502012-08-17 08:22:39 +00002456 sa = common_dimm->base_address;
York Sun123922b2012-10-08 07:44:23 +00002457 ea = sa + common_dimm->total_mem - 1;
York Suna4c66502012-08-17 08:22:39 +00002458 } else if (!popts->memctl_interleaving) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002459 /*
2460 * If memory interleaving between controllers is NOT
2461 * enabled, the starting address for each memory
2462 * controller is distinct. However, because rank
2463 * interleaving is enabled, the starting and ending
2464 * addresses of the total memory on that memory
2465 * controller needs to be programmed into its
2466 * respective CS0_BNDS.
2467 */
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002468 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2469 case FSL_DDR_CS0_CS1_CS2_CS3:
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002470 sa = common_dimm->base_address;
York Sun123922b2012-10-08 07:44:23 +00002471 ea = sa + common_dimm->total_mem - 1;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002472 break;
2473 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
York Suna4c66502012-08-17 08:22:39 +00002474 if ((i >= 2) && (dimm_number == 0)) {
york076bff82010-07-02 22:25:52 +00002475 sa = dimm_params[dimm_number].base_address +
York Suna4c66502012-08-17 08:22:39 +00002476 2 * rank_density;
2477 ea = sa + 2 * rank_density - 1;
york076bff82010-07-02 22:25:52 +00002478 } else {
2479 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002480 ea = sa + 2 * rank_density - 1;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002481 }
2482 break;
2483 case FSL_DDR_CS0_CS1:
york076bff82010-07-02 22:25:52 +00002484 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2485 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002486 ea = sa + rank_density - 1;
2487 if (i != 1)
2488 sa += (i % cs_per_dimm) * rank_density;
2489 ea += (i % cs_per_dimm) * rank_density;
york076bff82010-07-02 22:25:52 +00002490 } else {
2491 sa = 0;
2492 ea = 0;
2493 }
2494 if (i == 0)
York Suna4c66502012-08-17 08:22:39 +00002495 ea += rank_density;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002496 break;
2497 case FSL_DDR_CS2_CS3:
york076bff82010-07-02 22:25:52 +00002498 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2499 sa = dimm_params[dimm_number].base_address;
York Suna4c66502012-08-17 08:22:39 +00002500 ea = sa + rank_density - 1;
2501 if (i != 3)
2502 sa += (i % cs_per_dimm) * rank_density;
2503 ea += (i % cs_per_dimm) * rank_density;
york076bff82010-07-02 22:25:52 +00002504 } else {
2505 sa = 0;
2506 ea = 0;
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002507 }
york076bff82010-07-02 22:25:52 +00002508 if (i == 2)
2509 ea += (rank_density >> dbw_cap_adj);
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002510 break;
2511 default: /* No bank(chip-select) interleaving */
York Suna4c66502012-08-17 08:22:39 +00002512 sa = dimm_params[dimm_number].base_address;
2513 ea = sa + rank_density - 1;
2514 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2515 sa += (i % cs_per_dimm) * rank_density;
2516 ea += (i % cs_per_dimm) * rank_density;
2517 } else {
2518 sa = 0;
2519 ea = 0;
2520 }
Haiying Wangdbbbb3a2008-10-03 12:36:39 -04002521 break;
2522 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002523 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002524
2525 sa >>= 24;
2526 ea >>= 24;
2527
York Sun123922b2012-10-08 07:44:23 +00002528 if (cs_en) {
2529 ddr->cs[i].bnds = (0
York Sund4263b82013-06-03 12:39:06 -07002530 | ((sa & 0xffff) << 16) /* starting address */
2531 | ((ea & 0xffff) << 0) /* ending address */
York Sun123922b2012-10-08 07:44:23 +00002532 );
2533 } else {
York Sund8556db2013-06-25 11:37:45 -07002534 /* setting bnds to 0xffffffff for inactive CS */
2535 ddr->cs[i].bnds = 0xffffffff;
York Sun123922b2012-10-08 07:44:23 +00002536 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002537
Haiying Wang1f293b42008-10-03 12:37:26 -04002538 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
York Sun123922b2012-10-08 07:44:23 +00002539 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2540 set_csn_config_2(i, ddr);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002541 }
2542
Haiying Wangfc0c2b62010-12-01 10:35:31 -05002543 /*
2544 * In the case we only need to compute the ddr sdram size, we only need
2545 * to set csn registers, so return from here.
2546 */
2547 if (size_only)
2548 return 0;
2549
york7fd101c2010-07-02 22:25:54 +00002550 set_ddr_eor(ddr, popts);
2551
York Sun5614e712013-09-30 09:22:09 -07002552#if !defined(CONFIG_SYS_FSL_DDR1)
York Sun03e664d2015-01-06 13:18:50 -08002553 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002554#endif
2555
York Sun03e664d2015-01-06 13:18:50 -08002556 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
York Sund4263b82013-06-03 12:39:06 -07002557 additive_latency);
York Sun03e664d2015-01-06 13:18:50 -08002558 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2559 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2560 cas_latency, additive_latency);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002561
York Sune1fd16b2011-01-10 12:03:00 +00002562 set_ddr_cdr1(ddr, popts);
York Sun57495e42012-10-08 07:44:22 +00002563 set_ddr_cdr2(ddr, popts);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002564 set_ddr_sdram_cfg(ddr, popts, common_dimm);
York Sun66869f92015-03-19 09:30:26 -07002565 ip_rev = fsl_ddr_get_version(ctrl_num);
York Sune1fd16b2011-01-10 12:03:00 +00002566 if (ip_rev > 0x40400)
2567 unq_mrs_en = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002568
York Sunf80d6472014-09-11 13:32:06 -07002569 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
York Sunef87cab2014-09-05 13:52:43 +08002570 ddr->debug[18] = popts->cswl_override;
2571
York Sun03e664d2015-01-06 13:18:50 -08002572 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2573 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2574 cas_latency, additive_latency, unq_mrs_en);
2575 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
York Sun34e026f2014-03-27 17:54:47 -07002576#ifdef CONFIG_SYS_FSL_DDR4
2577 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
York Sun03e664d2015-01-06 13:18:50 -08002578 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
York Sun34e026f2014-03-27 17:54:47 -07002579#endif
York Sun564e9382018-01-29 10:24:08 -08002580 set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
2581
York Sun03e664d2015-01-06 13:18:50 -08002582 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002583 set_ddr_data_init(ddr);
2584 set_ddr_sdram_clk_cntl(ddr, popts);
2585 set_ddr_init_addr(ddr);
2586 set_ddr_init_ext_addr(ddr);
Dave Liuec145e82010-03-05 12:22:00 +08002587 set_timing_cfg_4(ddr, popts);
York Sune1fd16b2011-01-10 12:03:00 +00002588 set_timing_cfg_5(ddr, cas_latency);
York Sun34e026f2014-03-27 17:54:47 -07002589#ifdef CONFIG_SYS_FSL_DDR4
2590 set_ddr_sdram_cfg_3(ddr, popts);
2591 set_timing_cfg_6(ddr);
York Sun426230a2018-01-29 09:44:33 -08002592 set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
York Sun03e664d2015-01-06 13:18:50 -08002593 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
York Sunc0c32af2018-01-29 09:44:35 -08002594 set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);
York Sun34e026f2014-03-27 17:54:47 -07002595 set_ddr_dq_mapping(ddr, dimm_params);
2596#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002597
Dave Liuc360cea2009-03-14 12:48:30 +08002598 set_ddr_zq_cntl(ddr, zq_en);
Dave Liubdc9f7b2009-12-16 10:24:37 -06002599 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002600
Dave Liu22cca7e2008-11-21 16:31:35 +08002601 set_ddr_sr_cntr(ddr, sr_it);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002602
York Suncb930712013-06-25 11:37:41 -07002603#ifdef CONFIG_SYS_FSL_DDR_EMU
2604 /* disble DDR training for emulator */
2605 ddr->debug[2] = 0x00000400;
York Sun1f3402e2015-01-06 13:18:45 -08002606 ddr->debug[4] = 0xff800800;
2607 ddr->debug[5] = 0x08000800;
2608 ddr->debug[6] = 0x08000800;
2609 ddr->debug[7] = 0x08000800;
2610 ddr->debug[8] = 0x08000800;
York Suncb930712013-06-25 11:37:41 -07002611#endif
York Sun9855b3b2014-05-23 13:15:00 -07002612#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2613 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2614 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2615#endif
2616
Shengzhou Liu02fb2762016-11-21 11:36:48 +08002617#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
2618 /* Erratum applies when accumulated ECC is used, or DBI is enabled */
2619#define IS_ACC_ECC_EN(v) ((v) & 0x4)
2620#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
2621 if (has_erratum_a008378()) {
2622 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
2623 IS_DBI(ddr->ddr_sdram_cfg_3)) {
2624 ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
2625 ddr->debug[28] |= (0x9 << 20);
2626 }
2627 }
2628#endif
2629
2630#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2631 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
2632 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
2633 ddr->debug[28] &= 0xff0fff00;
2634 if (ddr_freq <= 1333)
2635 ddr->debug[28] |= 0x0080006a;
2636 else if (ddr_freq <= 1600)
2637 ddr->debug[28] |= 0x0070006f;
2638 else if (ddr_freq <= 1867)
2639 ddr->debug[28] |= 0x00700076;
2640 else if (ddr_freq <= 2133)
2641 ddr->debug[28] |= 0x0060007b;
2642 if (popts->cpo_sample)
2643 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2644 popts->cpo_sample;
2645#endif
2646
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002647 return check_fsl_memctl_config_regs(ddr);
2648}
Shengzhou Liu02fb2762016-11-21 11:36:48 +08002649
2650#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2651/*
2652 * This additional workaround of A009942 checks the condition to determine if
2653 * the CPO value set by the existing A009942 workaround needs to be updated.
2654 * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2655 * expected optimal value, the optimal value is highly board dependent.
2656 */
2657void erratum_a009942_check_cpo(void)
2658{
2659 struct ccsr_ddr __iomem *ddr =
2660 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2661 u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2662 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2663 u32 cpo_max = cpo_min;
2664 u32 sdram_cfg, i, tmp, lanes, ddr_type;
2665 bool update_cpo = false, has_ecc = false;
2666
2667 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2668 if (sdram_cfg & SDRAM_CFG_32_BE)
2669 lanes = 4;
2670 else if (sdram_cfg & SDRAM_CFG_16_BE)
2671 lanes = 2;
2672 else
2673 lanes = 8;
2674
2675 if (sdram_cfg & SDRAM_CFG_ECC_EN)
2676 has_ecc = true;
2677
2678 /* determine the maximum and minimum CPO values */
2679 for (i = 9; i < 9 + lanes / 2; i++) {
2680 cpo = ddr_in32(&ddr->debug[i]);
2681 cpo_e = cpo >> 24;
2682 cpo_o = (cpo >> 8) & 0xff;
2683 tmp = min(cpo_e, cpo_o);
2684 if (tmp < cpo_min)
2685 cpo_min = tmp;
2686 tmp = max(cpo_e, cpo_o);
2687 if (tmp > cpo_max)
2688 cpo_max = tmp;
2689 }
2690
2691 if (has_ecc) {
2692 cpo = ddr_in32(&ddr->debug[13]);
2693 cpo = cpo >> 24;
2694 if (cpo < cpo_min)
2695 cpo_min = cpo;
2696 if (cpo > cpo_max)
2697 cpo_max = cpo;
2698 }
2699
2700 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2701 cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2702 debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2703 cpo_target);
2704 debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2705
2706 ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2707 SDRAM_CFG_SDRAM_TYPE_SHIFT;
2708 if (ddr_type == SDRAM_TYPE_DDR4)
2709 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2710 else if (ddr_type == SDRAM_TYPE_DDR3)
2711 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2712
2713 if (update_cpo) {
2714 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2715 printf("in <board>/ddr.c to optimize cpo\n");
2716 }
2717}
2718#endif