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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
19 help
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
23 access the device.
24
25config TPL_MISC
26 bool "Enable Driver Model for Misc drivers in TPL"
27 depends on TPL_DM
28 help
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
32 access the device.
33
Thomas Chouca844dd2015-10-14 08:43:31 +080034config ALTERA_SYSID
35 bool "Altera Sysid support"
36 depends on MISC
37 help
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
40
Marek BehĂșnaa5eb9a2017-06-09 19:28:44 +020041config ATSHA204A
42 bool "Support for Atmel ATSHA204A module"
43 depends on MISC
44 help
45 Enable support for I2C connected Atmel's ATSHA204A
46 CryptoAuthentication module found for example on the Turris Omnia
47 board.
48
Tim Harvey8479b9e2022-03-07 16:24:04 -080049config GATEWORKS_SC
50 bool "Gateworks System Controller Support"
51 depends on MISC
52 help
53 Enable access for the Gateworks System Controller used on Gateworks
54 boards to provide a boot watchdog, power control, temperature monitor,
55 voltage ADCs, and EEPROM.
56
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020057config ROCKCHIP_EFUSE
58 bool "Rockchip e-fuse support"
59 depends on MISC
60 help
61 Enable (read-only) access for the e-fuse block found in Rockchip
62 SoCs: accesses can either be made using byte addressing and a length
63 or through child-nodes that are generated based on the e-fuse map
64 retrieved from the DTS.
65
66 This driver currently supports the RK3399 only, but can easily be
67 extended (by porting the read function from the Linux kernel sources)
68 to support other recent Rockchip devices.
69
Finley Xiaoa907dc32019-09-25 17:57:49 +020070config ROCKCHIP_OTP
71 bool "Rockchip OTP Support"
72 depends on MISC
73 help
74 Enable (read-only) access for the one-time-programmable memory block
75 found in Rockchip SoCs: accesses can either be made using byte
76 addressing and a length or through child-nodes that are generated
77 based on the e-fuse map retrieved from the DTS.
78
Pragnesh Patel05307212020-05-29 11:33:21 +053079config SIFIVE_OTP
80 bool "SiFive eMemory OTP driver"
81 depends on MISC
82 help
83 Enable support for reading and writing the eMemory OTP on the
84 SiFive SoCs.
85
Liviu Dudau0fabfeb2018-09-28 13:43:31 +010086config VEXPRESS_CONFIG
87 bool "Enable support for Arm Versatile Express config bus"
88 depends on MISC
89 help
90 If you say Y here, you will get support for accessing the
91 configuration bus on the Arm Versatile Express boards via
92 a sysreg driver.
93
Simon Glass6fb9ac12015-02-13 12:20:47 -070094config CMD_CROS_EC
95 bool "Enable crosec command"
96 depends on CROS_EC
97 help
98 Enable command-line access to the Chrome OS EC (Embedded
99 Controller). This provides the 'crosec' command which has
100 a number of sub-commands for performing EC tasks such as
101 updating its flash, accessing a small saved context area
102 and talking to the I2C bus behind the EC (if there is one).
103
104config CROS_EC
105 bool "Enable Chrome OS EC"
106 help
107 Enable access to the Chrome OS EC. This is a separate
108 microcontroller typically available on a SPI bus on Chromebooks. It
109 provides access to the keyboard, some internal storage and may
110 control access to the battery and main PMIC depending on the
111 device. You can use the 'crosec' command to access it.
112
Simon Glassaaba7032018-11-18 08:14:27 -0700113config SPL_CROS_EC
114 bool "Enable Chrome OS EC in SPL"
Adam Forda0746672019-08-24 13:50:34 -0500115 depends on SPL
Simon Glassaaba7032018-11-18 08:14:27 -0700116 help
117 Enable access to the Chrome OS EC in SPL. This is a separate
118 microcontroller typically available on a SPI bus on Chromebooks. It
119 provides access to the keyboard, some internal storage and may
120 control access to the battery and main PMIC depending on the
121 device. You can use the 'crosec' command to access it.
122
123config TPL_CROS_EC
124 bool "Enable Chrome OS EC in TPL"
Adam Forda0746672019-08-24 13:50:34 -0500125 depends on TPL
Simon Glassaaba7032018-11-18 08:14:27 -0700126 help
127 Enable access to the Chrome OS EC in TPL. This is a separate
128 microcontroller typically available on a SPI bus on Chromebooks. It
129 provides access to the keyboard, some internal storage and may
130 control access to the battery and main PMIC depending on the
131 device. You can use the 'crosec' command to access it.
132
Simon Glass6fb9ac12015-02-13 12:20:47 -0700133config CROS_EC_I2C
134 bool "Enable Chrome OS EC I2C driver"
135 depends on CROS_EC
136 help
137 Enable I2C access to the Chrome OS EC. This is used on older
138 ARM Chromebooks such as snow and spring before the standard bus
139 changed to SPI. The EC will accept commands across the I2C using
140 a special message protocol, and provide responses.
141
142config CROS_EC_LPC
143 bool "Enable Chrome OS EC LPC driver"
144 depends on CROS_EC
145 help
146 Enable I2C access to the Chrome OS EC. This is used on x86
147 Chromebooks such as link and falco. The keyboard is provided
148 through a legacy port interface, so on x86 machines the main
149 function of the EC is power and thermal management.
150
Simon Glassaaba7032018-11-18 08:14:27 -0700151config SPL_CROS_EC_LPC
152 bool "Enable Chrome OS EC LPC driver in SPL"
153 depends on CROS_EC
154 help
155 Enable I2C access to the Chrome OS EC. This is used on x86
156 Chromebooks such as link and falco. The keyboard is provided
157 through a legacy port interface, so on x86 machines the main
158 function of the EC is power and thermal management.
159
160config TPL_CROS_EC_LPC
161 bool "Enable Chrome OS EC LPC driver in TPL"
162 depends on CROS_EC
163 help
164 Enable I2C access to the Chrome OS EC. This is used on x86
165 Chromebooks such as link and falco. The keyboard is provided
166 through a legacy port interface, so on x86 machines the main
167 function of the EC is power and thermal management.
168
Simon Glass47cb8c62015-03-26 09:29:40 -0600169config CROS_EC_SANDBOX
170 bool "Enable Chrome OS EC sandbox driver"
171 depends on CROS_EC && SANDBOX
172 help
173 Enable a sandbox emulation of the Chrome OS EC. This supports
174 keyboard (use the -l flag to enable the LCD), verified boot context,
175 EC flash read/write/erase support and a few other things. It is
176 enough to perform a Chrome OS verified boot on sandbox.
177
Simon Glassaaba7032018-11-18 08:14:27 -0700178config SPL_CROS_EC_SANDBOX
179 bool "Enable Chrome OS EC sandbox driver in SPL"
180 depends on SPL_CROS_EC && SANDBOX
181 help
182 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
183 keyboard (use the -l flag to enable the LCD), verified boot context,
184 EC flash read/write/erase support and a few other things. It is
185 enough to perform a Chrome OS verified boot on sandbox.
186
187config TPL_CROS_EC_SANDBOX
188 bool "Enable Chrome OS EC sandbox driver in TPL"
189 depends on TPL_CROS_EC && SANDBOX
190 help
191 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
192 keyboard (use the -l flag to enable the LCD), verified boot context,
193 EC flash read/write/erase support and a few other things. It is
194 enough to perform a Chrome OS verified boot on sandbox.
195
Simon Glass6fb9ac12015-02-13 12:20:47 -0700196config CROS_EC_SPI
197 bool "Enable Chrome OS EC SPI driver"
198 depends on CROS_EC
199 help
200 Enable SPI access to the Chrome OS EC. This is used on newer
201 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
202 provides a faster and more robust interface than I2C but the bugs
203 are less interesting.
204
Simon Glass879704d2017-05-17 03:25:02 -0600205config DS4510
206 bool "Enable support for DS4510 CPU supervisor"
207 help
208 Enable support for the Maxim DS4510 CPU supervisor. It has an
209 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
210 and a configurable timer for the supervisor function. The device is
211 connected over I2C.
212
Peng Fanc12e0d92015-08-26 15:41:33 +0800213config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530214 bool "Enable FSL SEC_MON Driver"
215 help
216 Freescale Security Monitor block is responsible for monitoring
217 system states.
218 Security Monitor can be transitioned on any security failures,
219 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100220
Simon Glass79d66a62019-12-06 21:41:58 -0700221config IRQ
Wasim Khan182c5f12021-03-08 16:48:13 +0100222 bool "Interrupt controller"
Simon Glass79d66a62019-12-06 21:41:58 -0700223 help
Wasim Khan182c5f12021-03-08 16:48:13 +0100224 This enables support for interrupt controllers, including ITSS.
Simon Glass79d66a62019-12-06 21:41:58 -0700225 Some devices have extra features, such as Apollo Lake. The
226 device has its own uclass since there are several operations
227 involved.
228
Paul Burtonb5392c52018-12-16 19:25:19 -0300229config JZ4780_EFUSE
230 bool "Ingenic JZ4780 eFUSE support"
231 depends on ARCH_JZ47XX
232 help
233 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
234
Peng Fan3e020f02015-08-27 14:49:05 +0800235config MXC_OCOTP
236 bool "Enable MXC OCOTP Driver"
Peng Fan994ab732019-07-22 01:24:55 +0000237 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100238 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800239 help
240 If you say Y here, you will get support for the One Time
241 Programmable memory pages that are stored on the some
242 Freescale i.MX processors.
243
Michael Scott33e9a692021-09-25 19:49:28 +0300244config SPL_MXC_OCOTP
245 bool "Enable MXC OCOTP driver in SPL"
246 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
247 default y
248 help
249 If you say Y here, you will get support for the One Time
250 Programmable memory pages, that are stored on some
251 Freescale i.MX processors, in SPL.
252
Stefan Roese4cf9e462016-07-19 07:45:46 +0200253config NUVOTON_NCT6102D
254 bool "Enable Nuvoton NCT6102D Super I/O driver"
255 help
256 If you say Y here, you will get support for the Nuvoton
257 NCT6102D Super I/O driver. This can be used to enable or
258 disable the legacy UART, the watchdog or other devices
259 in the Nuvoton Super IO chips on X86 platforms.
260
Simon Glass5bee27a2019-12-06 21:41:55 -0700261config P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200262 bool "Intel Primary to Sideband Bridge"
Simon Glass5bee27a2019-12-06 21:41:55 -0700263 depends on X86 || SANDBOX
264 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200265 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass5bee27a2019-12-06 21:41:55 -0700266 abbreviated to P2SB. The P2SB is used to access various peripherals
267 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
268 space. The space is segmented into different channels and peripherals
269 are accessed by device-specific means within those channels. Devices
270 should be added in the device tree as subnodes of the P2SB. A
271 Peripheral Channel Register? (PCR) API is provided to access those
272 devices - see pcr_readl(), etc.
273
274config SPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200275 bool "Intel Primary to Sideband Bridge in SPL"
Simon Glass5bee27a2019-12-06 21:41:55 -0700276 depends on SPL && (X86 || SANDBOX)
277 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200278 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700279 through memory-mapped I/O in a large chunk of PCI space. The space is
280 segmented into different channels and peripherals are accessed by
281 device-specific means within those channels. Devices should be added
282 in the device tree as subnodes of the p2sb.
283
284config TPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200285 bool "Intel Primary to Sideband Bridge in TPL"
Simon Glass5bee27a2019-12-06 21:41:55 -0700286 depends on TPL && (X86 || SANDBOX)
287 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200288 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700289 through memory-mapped I/O in a large chunk of PCI space. The space is
290 segmented into different channels and peripherals are accessed by
291 device-specific means within those channels. Devices should be added
292 in the device tree as subnodes of the p2sb.
293
Simon Glass5fd6bad2016-01-21 19:43:31 -0700294config PWRSEQ
295 bool "Enable power-sequencing drivers"
296 depends on DM
297 help
298 Power-sequencing drivers provide support for controlling power for
299 devices. They are typically referenced by a phandle from another
300 device. When the device is started up, its power sequence can be
301 initiated.
302
303config SPL_PWRSEQ
304 bool "Enable power-sequencing drivers for SPL"
305 depends on PWRSEQ
306 help
307 Power-sequencing drivers provide support for controlling power for
308 devices. They are typically referenced by a phandle from another
309 device. When the device is started up, its power sequence can be
310 initiated.
311
Stefan Roese1cdd9412015-03-12 11:22:46 +0100312config PCA9551_LED
313 bool "Enable PCA9551 LED driver"
314 help
315 Enable driver for PCA9551 LED controller. This controller
316 is connected via I2C. So I2C needs to be enabled.
317
318config PCA9551_I2C_ADDR
319 hex "I2C address of PCA9551 LED controller"
320 depends on PCA9551_LED
321 default 0x60
322 help
323 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600324
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200325config STM32MP_FUSE
326 bool "Enable STM32MP fuse wrapper providing the fuse API"
327 depends on ARCH_STM32MP && MISC
328 default y if CMD_FUSE
329 help
330 If you say Y here, you will get support for the fuse API (OTP)
331 for STM32MP architecture.
332 This API is needed for CMD_FUSE.
333
Christophe Kerello4e280b92017-09-13 18:00:08 +0200334config STM32_RCC
335 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner71f63542020-05-06 08:02:42 -0400336 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200337 help
338 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
339 block) is responsible of the management of the clock and reset
340 generation.
341 This driver is similar to an MFD driver in the Linux kernel.
342
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600343config TEGRA_CAR
344 bool "Enable support for the Tegra CAR driver"
345 depends on TEGRA_NO_BPMP
346 help
347 The Tegra CAR (Clock and Reset Controller) is a HW module that
348 controls almost all clocks and resets in a Tegra SoC.
349
Stephen Warren73dd5c42016-08-08 09:41:34 -0600350config TEGRA186_BPMP
351 bool "Enable support for the Tegra186 BPMP driver"
352 depends on TEGRA186
353 help
354 The Tegra BPMP (Boot and Power Management Processor) is a separate
355 auxiliary CPU embedded into Tegra to perform power management work,
356 and controls related features such as clocks, resets, power domains,
357 PMIC I2C bus, etc. This driver provides the core low-level
358 communication path by which feature-specific drivers (such as clock)
359 can make requests to the BPMP. This driver is similar to an MFD
360 driver in the Linux kernel.
361
Simon Glass079ac592020-12-23 08:11:18 -0700362config TEST_DRV
363 bool "Enable support for test drivers"
364 default y if SANDBOX
365 help
366 This enables drivers and uclasses that provides a way of testing the
367 operations of memory allocation and driver/uclass methods in driver
368 model. This should only be enabled for testing as it is not useful for
369 anything else.
370
Adam Fordcc3fedb2018-08-06 14:26:50 -0500371config TWL4030_LED
372 bool "Enable TWL4030 LED controller"
373 help
374 Enable this to add support for the TWL4030 LED controller.
375
Stefan Roese85056932016-01-19 14:05:10 +0100376config WINBOND_W83627
377 bool "Enable Winbond Super I/O driver"
378 help
379 If you say Y here, you will get support for the Winbond
380 W83627 Super I/O driver. This can be used to enable the
381 legacy UART or other devices in the Winbond Super IO chips
382 on X86 platforms.
383
Miao Yanfcf5c042016-05-22 19:37:14 -0700384config QFW
385 bool
386 help
Asherah Connor5b0b43e2021-03-19 18:21:40 +1100387 Hidden option to enable QEMU fw_cfg interface and uclass. This will
388 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
389
390config QFW_PIO
391 bool
392 depends on QFW
393 help
394 Hidden option to enable PIO QEMU fw_cfg interface. This will be
395 selected by the appropriate QEMU board.
Miao Yanfcf5c042016-05-22 19:37:14 -0700396
Asherah Connor5830b572021-03-19 18:21:42 +1100397config QFW_MMIO
398 bool
399 depends on QFW
400 help
401 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
402 selected by the appropriate QEMU board.
403
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200404config I2C_EEPROM
405 bool "Enable driver for generic I2C-attached EEPROMs"
406 depends on MISC
407 help
408 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500409
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800410
411config SPL_I2C_EEPROM
412 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
413 depends on MISC && SPL && SPL_DM
414 help
415 This option is an SPL-variant of the I2C_EEPROM option.
416 See the help of I2C_EEPROM for details.
417
Adam Forde3f24d42017-08-13 09:00:28 -0500418config SYS_I2C_EEPROM_ADDR
419 hex "Chip address of the EEPROM device"
Tom Rini88cd7d02021-08-17 17:59:45 -0400420 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500421 default 0
422
Tom Rini88cd7d02021-08-17 17:59:45 -0400423if I2C_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500424
425config SYS_I2C_EEPROM_ADDR_OVERFLOW
426 hex "EEPROM Address Overflow"
Tom Rini5fd4a7e2021-12-11 14:55:47 -0500427 default 0x0
Adam Forde3f24d42017-08-13 09:00:28 -0500428 help
429 EEPROM chips that implement "address overflow" are ones
430 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
431 address and the extra bits end up in the "chip address" bit
432 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
433 byte chips.
434
435endif
436
Mario Six86da8c12018-04-27 14:53:33 +0200437config GDSYS_RXAUI_CTRL
438 bool "Enable gdsys RXAUI control driver"
439 depends on MISC
440 help
441 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200442
443config GDSYS_IOEP
444 bool "Enable gdsys IOEP driver"
445 depends on MISC
446 help
447 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200448
449config MPC83XX_SERDES
450 bool "Enable MPC83xx serdes driver"
451 depends on MISC
452 help
453 Support for serdes found on MPC83xx SoCs.
454
Tien Fong Chee62030002018-07-06 16:28:03 +0800455config FS_LOADER
456 bool "Enable loader driver for file system"
457 help
458 This is file system generic loader which can be used to load
459 the file image from the storage into target such as memory.
460
461 The consumer driver would then use this loader to program whatever,
462 ie. the FPGA device.
463
Keerthyb071a072022-01-27 13:16:53 +0100464config SPL_FS_LOADER
465 bool "Enable loader driver for file system"
466 help
467 This is file system generic loader which can be used to load
468 the file image from the storage into target such as memory.
469
470 The consumer driver would then use this loader to program whatever,
471 ie. the FPGA device.
472
Mario Sixc0a2b082018-10-04 09:00:54 +0200473config GDSYS_SOC
474 bool "Enable gdsys SOC driver"
475 depends on MISC
476 help
477 Support for gdsys IHS SOC, a simple bus associated with each gdsys
478 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
479 register maps are contained within the FPGA's register map.
480
Mario Sixab88bd22018-10-04 09:00:55 +0200481config IHS_FPGA
482 bool "Enable IHS FPGA driver"
483 depends on MISC
484 help
485 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
486 gdsys devices, which supply the majority of the functionality offered
487 by the devices. This driver supports both CON and CPU variants of the
488 devices, depending on the device tree entry.
Tero Kristo344eb6d2020-02-14 11:18:15 +0200489config ESM_K3
490 bool "Enable K3 ESM driver"
491 depends on ARCH_K3
492 help
493 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Sixab88bd22018-10-04 09:00:55 +0200494
Eugen Hristevf8164952019-10-09 09:23:39 +0000495config MICROCHIP_FLEXCOM
496 bool "Enable Microchip Flexcom driver"
497 depends on MISC
498 help
499 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
500 an I2C controller and an USART.
501 Only one function can be used at a time and is chosen at boot time
502 according to the device tree.
503
Tero Kristo9d233b42019-10-24 15:00:46 +0530504config K3_AVS0
505 depends on ARCH_K3 && SPL_DM_REGULATOR
506 bool "AVS class 0 support for K3 devices"
507 help
508 K3 devices have the optimized voltage values for the main voltage
509 domains stored in efuse within the VTM IP. This driver reads the
510 optimized voltage from the efuse, so that it can be programmed
511 to the PMIC on board.
512
Tero Kristo3b36b382020-02-14 11:18:16 +0200513config ESM_PMIC
514 bool "Enable PMIC ESM driver"
515 depends on DM_PMIC
516 help
517 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
518 typically to reboot the board in error condition.
519
Tom Rini98ab8312021-12-11 14:55:49 -0500520config FSL_IFC
521 bool
522
Michael Walle42595eb2022-02-25 18:06:24 +0530523config SL28CPLD
524 bool "Enable Kontron sl28cpld multi-function driver"
525 depends on DM_I2C
526 help
527 Support for the Kontron sl28cpld management controller. This is
528 the base driver which provides common access methods for the
529 sub-drivers.
530
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900531endmenu