Kever Yang | c43acfd | 2018-12-20 11:33:42 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016-2017 Rockchip Inc. |
| 4 | * |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 5 | * Adapted from coreboot. |
| 6 | */ |
Philipp Tomsich | fbecb94 | 2017-05-31 18:16:34 +0200 | [diff] [blame] | 7 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 8 | #include <common.h> |
| 9 | #include <clk.h> |
| 10 | #include <dm.h> |
| 11 | #include <dt-structs.h> |
| 12 | #include <ram.h> |
| 13 | #include <regmap.h> |
| 14 | #include <syscon.h> |
| 15 | #include <asm/io.h> |
Kever Yang | 15f09a1 | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 16 | #include <asm/arch-rockchip/clock.h> |
Kever Yang | 15f09a1 | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 17 | #include <asm/arch-rockchip/cru_rk3399.h> |
| 18 | #include <asm/arch-rockchip/grf_rk3399.h> |
| 19 | #include <asm/arch-rockchip/hardware.h> |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 20 | #include <asm/arch-rockchip/sdram_common.h> |
| 21 | #include <asm/arch-rockchip/sdram_rk3399.h> |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 22 | #include <linux/err.h> |
Philipp Tomsich | fbecb94 | 2017-05-31 18:16:34 +0200 | [diff] [blame] | 23 | #include <time.h> |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 24 | |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 25 | #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) |
| 26 | #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) |
| 27 | #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) |
| 28 | |
| 29 | #define PHY_DRV_ODT_HI_Z 0x0 |
| 30 | #define PHY_DRV_ODT_240 0x1 |
| 31 | #define PHY_DRV_ODT_120 0x8 |
| 32 | #define PHY_DRV_ODT_80 0x9 |
| 33 | #define PHY_DRV_ODT_60 0xc |
| 34 | #define PHY_DRV_ODT_48 0xd |
| 35 | #define PHY_DRV_ODT_40 0xe |
| 36 | #define PHY_DRV_ODT_34_3 0xf |
| 37 | |
Jagan Teki | 881860f | 2019-07-16 17:27:15 +0530 | [diff] [blame^] | 38 | #define PHY_BOOSTP_EN 0x1 |
| 39 | #define PHY_BOOSTN_EN 0x1 |
| 40 | |
Jagan Teki | 3392103 | 2019-07-15 23:58:43 +0530 | [diff] [blame] | 41 | #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ |
| 42 | ((n) << (8 + (ch) * 4))) |
| 43 | #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ |
| 44 | ((n) << (9 + (ch) * 4))) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 45 | struct chan_info { |
| 46 | struct rk3399_ddr_pctl_regs *pctl; |
| 47 | struct rk3399_ddr_pi_regs *pi; |
| 48 | struct rk3399_ddr_publ_regs *publ; |
| 49 | struct rk3399_msch_regs *msch; |
| 50 | }; |
| 51 | |
| 52 | struct dram_info { |
Kever Yang | 8276334 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 53 | #if defined(CONFIG_TPL_BUILD) || \ |
| 54 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Jagan Teki | a0aebe8 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 55 | u32 pwrup_srefresh_exit[2]; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 56 | struct chan_info chan[2]; |
| 57 | struct clk ddr_clk; |
| 58 | struct rk3399_cru *cru; |
Jagan Teki | a0aebe8 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 59 | struct rk3399_grf_regs *grf; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 60 | struct rk3399_pmucru *pmucru; |
| 61 | struct rk3399_pmusgrf_regs *pmusgrf; |
| 62 | struct rk3399_ddr_cic_regs *cic; |
| 63 | #endif |
| 64 | struct ram_info info; |
| 65 | struct rk3399_pmugrf_regs *pmugrf; |
| 66 | }; |
| 67 | |
Kever Yang | 8276334 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 68 | #if defined(CONFIG_TPL_BUILD) || \ |
| 69 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 70 | |
| 71 | struct rockchip_dmc_plat { |
| 72 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 73 | struct dtd_rockchip_rk3399_dmc dtplat; |
| 74 | #else |
| 75 | struct rk3399_sdram_params sdram_params; |
| 76 | #endif |
| 77 | struct regmap *map; |
| 78 | }; |
| 79 | |
Jagan Teki | a0aebe8 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 80 | static void *get_ddrc0_con(struct dram_info *dram, u8 channel) |
| 81 | { |
| 82 | return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1; |
| 83 | } |
| 84 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 85 | static void copy_to_reg(u32 *dest, const u32 *src, u32 n) |
| 86 | { |
| 87 | int i; |
| 88 | |
| 89 | for (i = 0; i < n / sizeof(u32); i++) { |
| 90 | writel(*src, dest); |
| 91 | src++; |
| 92 | dest++; |
| 93 | } |
| 94 | } |
| 95 | |
Jagan Teki | 3392103 | 2019-07-15 23:58:43 +0530 | [diff] [blame] | 96 | static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, |
| 97 | u32 phy) |
| 98 | { |
| 99 | channel &= 0x1; |
| 100 | ctl &= 0x1; |
| 101 | phy &= 0x1; |
| 102 | writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | |
| 103 | CRU_SFTRST_DDR_PHY(channel, phy), |
| 104 | &cru->softrst_con[4]); |
| 105 | } |
| 106 | |
| 107 | static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) |
| 108 | { |
| 109 | rkclk_ddr_reset(cru, channel, 1, 1); |
| 110 | udelay(10); |
| 111 | |
| 112 | rkclk_ddr_reset(cru, channel, 1, 0); |
| 113 | udelay(10); |
| 114 | |
| 115 | rkclk_ddr_reset(cru, channel, 0, 0); |
| 116 | udelay(10); |
| 117 | } |
| 118 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 119 | static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, |
| 120 | u32 freq) |
| 121 | { |
| 122 | u32 *denali_phy = ddr_publ_regs->denali_phy; |
| 123 | |
| 124 | /* From IP spec, only freq small than 125 can enter dll bypass mode */ |
| 125 | if (freq <= 125) { |
| 126 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
| 127 | setbits_le32(&denali_phy[86], (0x3 << 2) << 8); |
| 128 | setbits_le32(&denali_phy[214], (0x3 << 2) << 8); |
| 129 | setbits_le32(&denali_phy[342], (0x3 << 2) << 8); |
| 130 | setbits_le32(&denali_phy[470], (0x3 << 2) << 8); |
| 131 | |
| 132 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
| 133 | setbits_le32(&denali_phy[547], (0x3 << 2) << 16); |
| 134 | setbits_le32(&denali_phy[675], (0x3 << 2) << 16); |
| 135 | setbits_le32(&denali_phy[803], (0x3 << 2) << 16); |
| 136 | } else { |
| 137 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
| 138 | clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); |
| 139 | clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); |
| 140 | clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); |
| 141 | clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); |
| 142 | |
| 143 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
| 144 | clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); |
| 145 | clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); |
| 146 | clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); |
| 147 | } |
| 148 | } |
| 149 | |
| 150 | static void set_memory_map(const struct chan_info *chan, u32 channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 151 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 152 | { |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 153 | const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel]; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 154 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 155 | u32 *denali_pi = chan->pi->denali_pi; |
| 156 | u32 cs_map; |
| 157 | u32 reduc; |
| 158 | u32 row; |
| 159 | |
| 160 | /* Get row number from ddrconfig setting */ |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 161 | if (sdram_ch->cap_info.ddrconfig < 2 || |
| 162 | sdram_ch->cap_info.ddrconfig == 4) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 163 | row = 16; |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 164 | else if (sdram_ch->cap_info.ddrconfig == 3) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 165 | row = 14; |
| 166 | else |
| 167 | row = 15; |
| 168 | |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 169 | cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; |
| 170 | reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 171 | |
| 172 | /* Set the dram configuration to ctrl */ |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 173 | clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 174 | clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 175 | ((3 - sdram_ch->cap_info.bk) << 16) | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 176 | ((16 - row) << 24)); |
| 177 | |
| 178 | clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), |
| 179 | cs_map | (reduc << 16)); |
| 180 | |
| 181 | /* PI_199 PI_COL_DIFF:RW:0:4 */ |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 182 | clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 183 | |
| 184 | /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ |
| 185 | clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 186 | ((3 - sdram_ch->cap_info.bk) << 16) | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 187 | ((16 - row) << 24)); |
| 188 | /* PI_41 PI_CS_MAP:RW:24:4 */ |
| 189 | clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 190 | if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 191 | writel(0x2EC7FFFF, &denali_pi[34]); |
| 192 | } |
| 193 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 194 | static int phy_io_config(const struct chan_info *chan, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 195 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 196 | { |
| 197 | u32 *denali_phy = chan->publ->denali_phy; |
| 198 | u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; |
| 199 | u32 mode_sel; |
| 200 | u32 reg_value; |
| 201 | u32 drv_value, odt_value; |
| 202 | u32 speed; |
| 203 | |
| 204 | /* vref setting */ |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 205 | if (params->base.dramtype == LPDDR4) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 206 | /* LPDDR4 */ |
| 207 | vref_mode_dq = 0x6; |
| 208 | vref_value_dq = 0x1f; |
| 209 | vref_mode_ac = 0x6; |
| 210 | vref_value_ac = 0x1f; |
Jagan Teki | 6cbd242 | 2019-07-16 17:27:11 +0530 | [diff] [blame] | 211 | mode_sel = 0x6; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 212 | } else if (params->base.dramtype == LPDDR3) { |
| 213 | if (params->base.odt == 1) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 214 | vref_mode_dq = 0x5; /* LPDDR3 ODT */ |
| 215 | drv_value = (readl(&denali_phy[6]) >> 12) & 0xf; |
| 216 | odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; |
| 217 | if (drv_value == PHY_DRV_ODT_48) { |
| 218 | switch (odt_value) { |
| 219 | case PHY_DRV_ODT_240: |
| 220 | vref_value_dq = 0x16; |
| 221 | break; |
| 222 | case PHY_DRV_ODT_120: |
| 223 | vref_value_dq = 0x26; |
| 224 | break; |
| 225 | case PHY_DRV_ODT_60: |
| 226 | vref_value_dq = 0x36; |
| 227 | break; |
| 228 | default: |
| 229 | debug("Invalid ODT value.\n"); |
| 230 | return -EINVAL; |
| 231 | } |
| 232 | } else if (drv_value == PHY_DRV_ODT_40) { |
| 233 | switch (odt_value) { |
| 234 | case PHY_DRV_ODT_240: |
| 235 | vref_value_dq = 0x19; |
| 236 | break; |
| 237 | case PHY_DRV_ODT_120: |
| 238 | vref_value_dq = 0x23; |
| 239 | break; |
| 240 | case PHY_DRV_ODT_60: |
| 241 | vref_value_dq = 0x31; |
| 242 | break; |
| 243 | default: |
| 244 | debug("Invalid ODT value.\n"); |
| 245 | return -EINVAL; |
| 246 | } |
| 247 | } else if (drv_value == PHY_DRV_ODT_34_3) { |
| 248 | switch (odt_value) { |
| 249 | case PHY_DRV_ODT_240: |
| 250 | vref_value_dq = 0x17; |
| 251 | break; |
| 252 | case PHY_DRV_ODT_120: |
| 253 | vref_value_dq = 0x20; |
| 254 | break; |
| 255 | case PHY_DRV_ODT_60: |
| 256 | vref_value_dq = 0x2e; |
| 257 | break; |
| 258 | default: |
| 259 | debug("Invalid ODT value.\n"); |
| 260 | return -EINVAL; |
| 261 | } |
| 262 | } else { |
| 263 | debug("Invalid DRV value.\n"); |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | } else { |
| 267 | vref_mode_dq = 0x2; /* LPDDR3 */ |
| 268 | vref_value_dq = 0x1f; |
| 269 | } |
| 270 | vref_mode_ac = 0x2; |
| 271 | vref_value_ac = 0x1f; |
Jagan Teki | 6cbd242 | 2019-07-16 17:27:11 +0530 | [diff] [blame] | 272 | mode_sel = 0x0; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 273 | } else if (params->base.dramtype == DDR3) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 274 | /* DDR3L */ |
| 275 | vref_mode_dq = 0x1; |
| 276 | vref_value_dq = 0x1f; |
| 277 | vref_mode_ac = 0x1; |
| 278 | vref_value_ac = 0x1f; |
Jagan Teki | 6cbd242 | 2019-07-16 17:27:11 +0530 | [diff] [blame] | 279 | mode_sel = 0x1; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 280 | } else { |
| 281 | debug("Unknown DRAM type.\n"); |
| 282 | return -EINVAL; |
| 283 | } |
| 284 | |
| 285 | reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; |
| 286 | |
| 287 | /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ |
| 288 | clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); |
| 289 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ |
| 290 | clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); |
| 291 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ |
| 292 | clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); |
| 293 | /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ |
| 294 | clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); |
| 295 | |
| 296 | reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; |
| 297 | |
| 298 | /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ |
| 299 | clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); |
| 300 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 301 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
| 302 | clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); |
| 303 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 304 | clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); |
| 305 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 306 | clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); |
| 307 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 308 | clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); |
| 309 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 310 | clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); |
| 311 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 312 | clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); |
| 313 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 314 | clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); |
| 315 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 316 | clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); |
| 317 | |
Jagan Teki | 881860f | 2019-07-16 17:27:15 +0530 | [diff] [blame^] | 318 | if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { |
| 319 | /* BOOSTP_EN & BOOSTN_EN */ |
| 320 | reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN); |
| 321 | /* PHY_925 PHY_PAD_FDBK_DRIVE2 */ |
| 322 | clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8); |
| 323 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 324 | clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12); |
| 325 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 326 | clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14); |
| 327 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 328 | clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20); |
| 329 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 330 | clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22); |
| 331 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 332 | clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20); |
| 333 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 334 | clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20); |
| 335 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 336 | clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20); |
| 337 | } |
| 338 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 339 | /* speed setting */ |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 340 | if (params->base.ddr_freq < 400) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 341 | speed = 0x0; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 342 | else if (params->base.ddr_freq < 800) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 343 | speed = 0x1; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 344 | else if (params->base.ddr_freq < 1200) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 345 | speed = 0x2; |
| 346 | else |
| 347 | speed = 0x3; |
| 348 | |
| 349 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
| 350 | clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); |
| 351 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 352 | clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); |
| 353 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 354 | clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); |
| 355 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 356 | clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); |
| 357 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 358 | clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); |
| 359 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 360 | clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); |
| 361 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 362 | clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); |
| 363 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 364 | clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); |
| 365 | |
| 366 | return 0; |
| 367 | } |
| 368 | |
Jagan Teki | ba607fa | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 369 | static void set_ds_odt(const struct chan_info *chan, |
| 370 | const struct rk3399_sdram_params *params) |
| 371 | { |
| 372 | u32 *denali_phy = chan->publ->denali_phy; |
| 373 | |
| 374 | u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; |
| 375 | u32 tsel_idle_select_p, tsel_rd_select_p; |
| 376 | u32 tsel_idle_select_n, tsel_rd_select_n; |
| 377 | u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; |
| 378 | u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; |
| 379 | u32 reg_value; |
| 380 | |
| 381 | if (params->base.dramtype == LPDDR4) { |
| 382 | tsel_rd_select_p = PHY_DRV_ODT_HI_Z; |
| 383 | tsel_rd_select_n = PHY_DRV_ODT_240; |
| 384 | |
| 385 | tsel_idle_select_p = PHY_DRV_ODT_HI_Z; |
| 386 | tsel_idle_select_n = PHY_DRV_ODT_240; |
| 387 | |
| 388 | tsel_wr_select_dq_p = PHY_DRV_ODT_40; |
| 389 | tsel_wr_select_dq_n = PHY_DRV_ODT_40; |
| 390 | |
| 391 | tsel_wr_select_ca_p = PHY_DRV_ODT_40; |
| 392 | tsel_wr_select_ca_n = PHY_DRV_ODT_40; |
| 393 | } else if (params->base.dramtype == LPDDR3) { |
| 394 | tsel_rd_select_p = PHY_DRV_ODT_240; |
| 395 | tsel_rd_select_n = PHY_DRV_ODT_HI_Z; |
| 396 | |
| 397 | tsel_idle_select_p = PHY_DRV_ODT_240; |
| 398 | tsel_idle_select_n = PHY_DRV_ODT_HI_Z; |
| 399 | |
| 400 | tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; |
| 401 | tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; |
| 402 | |
| 403 | tsel_wr_select_ca_p = PHY_DRV_ODT_48; |
| 404 | tsel_wr_select_ca_n = PHY_DRV_ODT_48; |
| 405 | } else { |
| 406 | tsel_rd_select_p = PHY_DRV_ODT_240; |
| 407 | tsel_rd_select_n = PHY_DRV_ODT_240; |
| 408 | |
| 409 | tsel_idle_select_p = PHY_DRV_ODT_240; |
| 410 | tsel_idle_select_n = PHY_DRV_ODT_240; |
| 411 | |
| 412 | tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; |
| 413 | tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; |
| 414 | |
| 415 | tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; |
| 416 | tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; |
| 417 | } |
| 418 | |
| 419 | if (params->base.odt == 1) |
| 420 | tsel_rd_en = 1; |
| 421 | else |
| 422 | tsel_rd_en = 0; |
| 423 | |
| 424 | tsel_wr_en = 0; |
| 425 | tsel_idle_en = 0; |
| 426 | |
| 427 | /* |
| 428 | * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 |
| 429 | * sets termination values for read/idle cycles and drive strength |
| 430 | * for write cycles for DQ/DM |
| 431 | */ |
| 432 | reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | |
| 433 | (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | |
| 434 | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); |
| 435 | clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); |
| 436 | clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); |
| 437 | clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); |
| 438 | clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); |
| 439 | |
| 440 | /* |
| 441 | * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 |
| 442 | * sets termination values for read/idle cycles and drive strength |
| 443 | * for write cycles for DQS |
| 444 | */ |
| 445 | clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); |
| 446 | clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); |
| 447 | clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); |
| 448 | clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); |
| 449 | |
| 450 | /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ |
| 451 | reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); |
| 452 | clrsetbits_le32(&denali_phy[544], 0xff, reg_value); |
| 453 | clrsetbits_le32(&denali_phy[672], 0xff, reg_value); |
| 454 | clrsetbits_le32(&denali_phy[800], 0xff, reg_value); |
| 455 | |
| 456 | /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ |
| 457 | clrsetbits_le32(&denali_phy[928], 0xff, reg_value); |
| 458 | |
| 459 | /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ |
| 460 | clrsetbits_le32(&denali_phy[937], 0xff, reg_value); |
| 461 | |
| 462 | /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ |
| 463 | clrsetbits_le32(&denali_phy[935], 0xff, reg_value); |
| 464 | |
| 465 | /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ |
| 466 | clrsetbits_le32(&denali_phy[939], 0xff, reg_value); |
| 467 | |
| 468 | /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ |
| 469 | clrsetbits_le32(&denali_phy[929], 0xff, reg_value); |
| 470 | |
| 471 | /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ |
| 472 | clrsetbits_le32(&denali_phy[924], 0xff, |
| 473 | tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4)); |
| 474 | clrsetbits_le32(&denali_phy[925], 0xff, |
| 475 | tsel_rd_select_n | (tsel_rd_select_p << 4)); |
| 476 | |
| 477 | /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ |
| 478 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 479 | << 16; |
| 480 | clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); |
| 481 | clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); |
| 482 | clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); |
| 483 | clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); |
| 484 | |
| 485 | /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ |
| 486 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 487 | << 24; |
| 488 | clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); |
| 489 | clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); |
| 490 | clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); |
| 491 | clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); |
| 492 | |
| 493 | /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ |
| 494 | reg_value = tsel_wr_en << 8; |
| 495 | clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); |
| 496 | clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); |
| 497 | clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); |
| 498 | |
| 499 | /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ |
| 500 | reg_value = tsel_wr_en << 17; |
| 501 | clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); |
| 502 | /* |
| 503 | * pad_rst/cke/cs/clk_term tsel 1bits |
| 504 | * DENALI_PHY_938/936/940/934 offset_17 |
| 505 | */ |
| 506 | clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); |
| 507 | clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); |
| 508 | clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); |
| 509 | clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); |
| 510 | |
| 511 | /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ |
| 512 | clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); |
| 513 | |
| 514 | phy_io_config(chan, params); |
| 515 | } |
| 516 | |
| 517 | static void pctl_start(struct dram_info *dram, u8 channel) |
| 518 | { |
| 519 | const struct chan_info *chan = &dram->chan[channel]; |
| 520 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 521 | u32 *denali_phy = chan->publ->denali_phy; |
| 522 | u32 *ddrc0_con = get_ddrc0_con(dram, channel); |
| 523 | u32 count = 0; |
| 524 | u32 byte, tmp; |
| 525 | |
| 526 | writel(0x01000000, &ddrc0_con); |
| 527 | |
| 528 | clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); |
| 529 | |
| 530 | while (!(readl(&denali_ctl[203]) & (1 << 3))) { |
| 531 | if (count > 1000) { |
| 532 | printf("%s: Failed to init pctl for channel %d\n", |
| 533 | __func__, channel); |
| 534 | while (1) |
| 535 | ; |
| 536 | } |
| 537 | |
| 538 | udelay(1); |
| 539 | count++; |
| 540 | } |
| 541 | |
| 542 | writel(0x01000100, &ddrc0_con); |
| 543 | |
| 544 | for (byte = 0; byte < 4; byte++) { |
| 545 | tmp = 0x820; |
| 546 | writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]); |
| 547 | writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]); |
| 548 | writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]); |
| 549 | writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]); |
| 550 | writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]); |
| 551 | |
| 552 | clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp); |
| 553 | } |
| 554 | |
| 555 | clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, |
| 556 | dram->pwrup_srefresh_exit[channel]); |
| 557 | } |
| 558 | |
Jagan Teki | fe42d4a | 2019-07-15 23:58:44 +0530 | [diff] [blame] | 559 | static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, |
| 560 | u32 channel, const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 561 | { |
| 562 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 563 | u32 *denali_pi = chan->pi->denali_pi; |
| 564 | u32 *denali_phy = chan->publ->denali_phy; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 565 | const u32 *params_ctl = params->pctl_regs.denali_ctl; |
| 566 | const u32 *params_phy = params->phy_regs.denali_phy; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 567 | u32 tmp, tmp1, tmp2; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 568 | |
| 569 | /* |
| 570 | * work around controller bug: |
| 571 | * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed |
| 572 | */ |
| 573 | copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], |
| 574 | sizeof(struct rk3399_ddr_pctl_regs) - 4); |
| 575 | writel(params_ctl[0], &denali_ctl[0]); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 576 | |
Jagan Teki | 47627c8 | 2019-07-16 17:27:13 +0530 | [diff] [blame] | 577 | /* |
| 578 | * two channel init at the same time, then ZQ Cal Start |
| 579 | * at the same time, it will use the same RZQ, but cannot |
| 580 | * start at the same time. |
| 581 | * |
| 582 | * So, increase tINIT3 for channel 1, will avoid two |
| 583 | * channel ZQ Cal Start at the same time |
| 584 | */ |
| 585 | if (params->base.dramtype == LPDDR4 && channel == 1) { |
| 586 | tmp = ((params->base.ddr_freq * MHz + 999) / 1000); |
| 587 | tmp1 = readl(&denali_ctl[14]); |
| 588 | writel(tmp + tmp1, &denali_ctl[14]); |
| 589 | } |
| 590 | |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 591 | copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 592 | sizeof(struct rk3399_ddr_pi_regs)); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 593 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 594 | /* rank count need to set for init */ |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 595 | set_memory_map(chan, channel, params); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 596 | |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 597 | writel(params->phy_regs.denali_phy[910], &denali_phy[910]); |
| 598 | writel(params->phy_regs.denali_phy[911], &denali_phy[911]); |
| 599 | writel(params->phy_regs.denali_phy[912], &denali_phy[912]); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 600 | |
Jagan Teki | 009fe1b | 2019-07-16 17:27:14 +0530 | [diff] [blame] | 601 | if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { |
| 602 | writel(params->phy_regs.denali_phy[898], &denali_phy[898]); |
| 603 | writel(params->phy_regs.denali_phy[919], &denali_phy[919]); |
| 604 | } |
| 605 | |
Jagan Teki | a0aebe8 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 606 | dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & |
| 607 | PWRUP_SREFRESH_EXIT; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 608 | clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); |
| 609 | |
| 610 | /* PHY_DLL_RST_EN */ |
| 611 | clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); |
| 612 | |
| 613 | setbits_le32(&denali_pi[0], START); |
| 614 | setbits_le32(&denali_ctl[0], START); |
| 615 | |
Jagan Teki | 5cbc866 | 2019-07-16 17:27:12 +0530 | [diff] [blame] | 616 | /** |
| 617 | * LPDDR4 use PLL bypass mode for init |
| 618 | * not need to wait for the PLL to lock |
| 619 | */ |
| 620 | if (params->base.dramtype != LPDDR4) { |
| 621 | /* Waiting for phy DLL lock */ |
| 622 | while (1) { |
| 623 | tmp = readl(&denali_phy[920]); |
| 624 | tmp1 = readl(&denali_phy[921]); |
| 625 | tmp2 = readl(&denali_phy[922]); |
| 626 | if ((((tmp >> 16) & 0x1) == 0x1) && |
| 627 | (((tmp1 >> 16) & 0x1) == 0x1) && |
| 628 | (((tmp1 >> 0) & 0x1) == 0x1) && |
| 629 | (((tmp2 >> 0) & 0x1) == 0x1)) |
| 630 | break; |
| 631 | } |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); |
| 635 | copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); |
| 636 | copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4); |
| 637 | copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4); |
| 638 | copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4); |
| 639 | copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); |
| 640 | copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); |
| 641 | copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 642 | set_ds_odt(chan, params); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 643 | |
| 644 | /* |
| 645 | * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 |
| 646 | * dqs_tsel_wr_end[7:4] add Half cycle |
| 647 | */ |
| 648 | tmp = (readl(&denali_phy[84]) >> 8) & 0xff; |
| 649 | clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); |
| 650 | tmp = (readl(&denali_phy[212]) >> 8) & 0xff; |
| 651 | clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); |
| 652 | tmp = (readl(&denali_phy[340]) >> 8) & 0xff; |
| 653 | clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); |
| 654 | tmp = (readl(&denali_phy[468]) >> 8) & 0xff; |
| 655 | clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); |
| 656 | |
| 657 | /* |
| 658 | * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 |
| 659 | * dq_tsel_wr_end[7:4] add Half cycle |
| 660 | */ |
| 661 | tmp = (readl(&denali_phy[83]) >> 16) & 0xff; |
| 662 | clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); |
| 663 | tmp = (readl(&denali_phy[211]) >> 16) & 0xff; |
| 664 | clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); |
| 665 | tmp = (readl(&denali_phy[339]) >> 16) & 0xff; |
| 666 | clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); |
| 667 | tmp = (readl(&denali_phy[467]) >> 16) & 0xff; |
| 668 | clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); |
| 669 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 670 | return 0; |
| 671 | } |
| 672 | |
| 673 | static void select_per_cs_training_index(const struct chan_info *chan, |
| 674 | u32 rank) |
| 675 | { |
| 676 | u32 *denali_phy = chan->publ->denali_phy; |
| 677 | |
| 678 | /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ |
Jagan Teki | 63f4d71 | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 679 | if ((readl(&denali_phy[84]) >> 16) & 1) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 680 | /* |
| 681 | * PHY_8/136/264/392 |
| 682 | * phy_per_cs_training_index_X 1bit offset_24 |
| 683 | */ |
| 684 | clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); |
| 685 | clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); |
| 686 | clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); |
| 687 | clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); |
| 688 | } |
| 689 | } |
| 690 | |
| 691 | static void override_write_leveling_value(const struct chan_info *chan) |
| 692 | { |
| 693 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 694 | u32 *denali_phy = chan->publ->denali_phy; |
| 695 | u32 byte; |
| 696 | |
| 697 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
| 698 | setbits_le32(&denali_phy[896], 1); |
| 699 | |
| 700 | /* |
| 701 | * PHY_8/136/264/392 |
| 702 | * phy_per_cs_training_multicast_en_X 1bit offset_16 |
| 703 | */ |
| 704 | clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); |
| 705 | clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); |
| 706 | clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); |
| 707 | clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); |
| 708 | |
| 709 | for (byte = 0; byte < 4; byte++) |
| 710 | clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, |
| 711 | 0x200 << 16); |
| 712 | |
| 713 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
| 714 | clrbits_le32(&denali_phy[896], 1); |
| 715 | |
| 716 | /* CTL_200 ctrlupd_req 1bit offset_8 */ |
| 717 | clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); |
| 718 | } |
| 719 | |
| 720 | static int data_training_ca(const struct chan_info *chan, u32 channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 721 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 722 | { |
| 723 | u32 *denali_pi = chan->pi->denali_pi; |
| 724 | u32 *denali_phy = chan->publ->denali_phy; |
| 725 | u32 i, tmp; |
| 726 | u32 obs_0, obs_1, obs_2, obs_err = 0; |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 727 | u32 rank = params->ch[channel].cap_info.rank; |
Jagan Teki | 708e9a7 | 2019-07-15 23:58:41 +0530 | [diff] [blame] | 728 | u32 rank_mask; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 729 | |
Jagan Teki | 01976ae | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 730 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 731 | writel(0x00003f7c, (&denali_pi[175])); |
| 732 | |
Jagan Teki | 3dae87d | 2019-07-16 17:27:09 +0530 | [diff] [blame] | 733 | if (params->base.dramtype == LPDDR4) |
| 734 | rank_mask = (rank == 1) ? 0x5 : 0xf; |
| 735 | else |
| 736 | rank_mask = (rank == 1) ? 0x1 : 0x3; |
Jagan Teki | 708e9a7 | 2019-07-15 23:58:41 +0530 | [diff] [blame] | 737 | |
| 738 | for (i = 0; i < 4; i++) { |
| 739 | if (!(rank_mask & (1 << i))) |
| 740 | continue; |
| 741 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 742 | select_per_cs_training_index(chan, i); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 743 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 744 | /* PI_100 PI_CALVL_EN:RW:8:2 */ |
| 745 | clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 746 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 747 | /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ |
| 748 | clrsetbits_le32(&denali_pi[92], |
| 749 | (0x1 << 16) | (0x3 << 24), |
| 750 | (0x1 << 16) | (i << 24)); |
| 751 | |
| 752 | /* Waiting for training complete */ |
| 753 | while (1) { |
| 754 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 755 | tmp = readl(&denali_pi[174]) >> 8; |
| 756 | /* |
| 757 | * check status obs |
| 758 | * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 |
| 759 | */ |
| 760 | obs_0 = readl(&denali_phy[532]); |
| 761 | obs_1 = readl(&denali_phy[660]); |
| 762 | obs_2 = readl(&denali_phy[788]); |
| 763 | if (((obs_0 >> 30) & 0x3) || |
| 764 | ((obs_1 >> 30) & 0x3) || |
| 765 | ((obs_2 >> 30) & 0x3)) |
| 766 | obs_err = 1; |
| 767 | if ((((tmp >> 11) & 0x1) == 0x1) && |
| 768 | (((tmp >> 13) & 0x1) == 0x1) && |
| 769 | (((tmp >> 5) & 0x1) == 0x0) && |
Jagan Teki | 63f4d71 | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 770 | obs_err == 0) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 771 | break; |
| 772 | else if ((((tmp >> 5) & 0x1) == 0x1) || |
| 773 | (obs_err == 1)) |
| 774 | return -EIO; |
| 775 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 776 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 777 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 778 | writel(0x00003f7c, (&denali_pi[175])); |
| 779 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 780 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 781 | clrbits_le32(&denali_pi[100], 0x3 << 8); |
| 782 | |
| 783 | return 0; |
| 784 | } |
| 785 | |
| 786 | static int data_training_wl(const struct chan_info *chan, u32 channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 787 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 788 | { |
| 789 | u32 *denali_pi = chan->pi->denali_pi; |
| 790 | u32 *denali_phy = chan->publ->denali_phy; |
| 791 | u32 i, tmp; |
| 792 | u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 793 | u32 rank = params->ch[channel].cap_info.rank; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 794 | |
Jagan Teki | 01976ae | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 795 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 796 | writel(0x00003f7c, (&denali_pi[175])); |
| 797 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 798 | for (i = 0; i < rank; i++) { |
| 799 | select_per_cs_training_index(chan, i); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 800 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 801 | /* PI_60 PI_WRLVL_EN:RW:8:2 */ |
| 802 | clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 803 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 804 | /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ |
| 805 | clrsetbits_le32(&denali_pi[59], |
| 806 | (0x1 << 8) | (0x3 << 16), |
| 807 | (0x1 << 8) | (i << 16)); |
| 808 | |
| 809 | /* Waiting for training complete */ |
| 810 | while (1) { |
| 811 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 812 | tmp = readl(&denali_pi[174]) >> 8; |
| 813 | |
| 814 | /* |
| 815 | * check status obs, if error maybe can not |
| 816 | * get leveling done PHY_40/168/296/424 |
| 817 | * phy_wrlvl_status_obs_X:0:13 |
| 818 | */ |
| 819 | obs_0 = readl(&denali_phy[40]); |
| 820 | obs_1 = readl(&denali_phy[168]); |
| 821 | obs_2 = readl(&denali_phy[296]); |
| 822 | obs_3 = readl(&denali_phy[424]); |
| 823 | if (((obs_0 >> 12) & 0x1) || |
| 824 | ((obs_1 >> 12) & 0x1) || |
| 825 | ((obs_2 >> 12) & 0x1) || |
| 826 | ((obs_3 >> 12) & 0x1)) |
| 827 | obs_err = 1; |
| 828 | if ((((tmp >> 10) & 0x1) == 0x1) && |
| 829 | (((tmp >> 13) & 0x1) == 0x1) && |
| 830 | (((tmp >> 4) & 0x1) == 0x0) && |
Jagan Teki | 63f4d71 | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 831 | obs_err == 0) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 832 | break; |
| 833 | else if ((((tmp >> 4) & 0x1) == 0x1) || |
| 834 | (obs_err == 1)) |
| 835 | return -EIO; |
| 836 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 837 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 838 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 839 | writel(0x00003f7c, (&denali_pi[175])); |
| 840 | } |
| 841 | |
| 842 | override_write_leveling_value(chan); |
| 843 | clrbits_le32(&denali_pi[60], 0x3 << 8); |
| 844 | |
| 845 | return 0; |
| 846 | } |
| 847 | |
| 848 | static int data_training_rg(const struct chan_info *chan, u32 channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 849 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 850 | { |
| 851 | u32 *denali_pi = chan->pi->denali_pi; |
| 852 | u32 *denali_phy = chan->publ->denali_phy; |
| 853 | u32 i, tmp; |
| 854 | u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 855 | u32 rank = params->ch[channel].cap_info.rank; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 856 | |
Jagan Teki | 01976ae | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 857 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 858 | writel(0x00003f7c, (&denali_pi[175])); |
| 859 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 860 | for (i = 0; i < rank; i++) { |
| 861 | select_per_cs_training_index(chan, i); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 862 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 863 | /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ |
| 864 | clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 865 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 866 | /* |
| 867 | * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 |
| 868 | * PI_RDLVL_CS:RW:24:2 |
| 869 | */ |
| 870 | clrsetbits_le32(&denali_pi[74], |
| 871 | (0x1 << 16) | (0x3 << 24), |
| 872 | (0x1 << 16) | (i << 24)); |
| 873 | |
| 874 | /* Waiting for training complete */ |
| 875 | while (1) { |
| 876 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 877 | tmp = readl(&denali_pi[174]) >> 8; |
| 878 | |
| 879 | /* |
| 880 | * check status obs |
| 881 | * PHY_43/171/299/427 |
| 882 | * PHY_GTLVL_STATUS_OBS_x:16:8 |
| 883 | */ |
| 884 | obs_0 = readl(&denali_phy[43]); |
| 885 | obs_1 = readl(&denali_phy[171]); |
| 886 | obs_2 = readl(&denali_phy[299]); |
| 887 | obs_3 = readl(&denali_phy[427]); |
| 888 | if (((obs_0 >> (16 + 6)) & 0x3) || |
| 889 | ((obs_1 >> (16 + 6)) & 0x3) || |
| 890 | ((obs_2 >> (16 + 6)) & 0x3) || |
| 891 | ((obs_3 >> (16 + 6)) & 0x3)) |
| 892 | obs_err = 1; |
| 893 | if ((((tmp >> 9) & 0x1) == 0x1) && |
| 894 | (((tmp >> 13) & 0x1) == 0x1) && |
| 895 | (((tmp >> 3) & 0x1) == 0x0) && |
Jagan Teki | 63f4d71 | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 896 | obs_err == 0) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 897 | break; |
| 898 | else if ((((tmp >> 3) & 0x1) == 0x1) || |
| 899 | (obs_err == 1)) |
| 900 | return -EIO; |
| 901 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 902 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 903 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 904 | writel(0x00003f7c, (&denali_pi[175])); |
| 905 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 906 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 907 | clrbits_le32(&denali_pi[80], 0x3 << 24); |
| 908 | |
| 909 | return 0; |
| 910 | } |
| 911 | |
| 912 | static int data_training_rl(const struct chan_info *chan, u32 channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 913 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 914 | { |
| 915 | u32 *denali_pi = chan->pi->denali_pi; |
| 916 | u32 i, tmp; |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 917 | u32 rank = params->ch[channel].cap_info.rank; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 918 | |
Jagan Teki | 01976ae | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 919 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 920 | writel(0x00003f7c, (&denali_pi[175])); |
| 921 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 922 | for (i = 0; i < rank; i++) { |
| 923 | select_per_cs_training_index(chan, i); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 924 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 925 | /* PI_80 PI_RDLVL_EN:RW:16:2 */ |
| 926 | clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 927 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 928 | /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ |
| 929 | clrsetbits_le32(&denali_pi[74], |
| 930 | (0x1 << 8) | (0x3 << 24), |
| 931 | (0x1 << 8) | (i << 24)); |
| 932 | |
| 933 | /* Waiting for training complete */ |
| 934 | while (1) { |
| 935 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 936 | tmp = readl(&denali_pi[174]) >> 8; |
| 937 | |
| 938 | /* |
| 939 | * make sure status obs not report error bit |
| 940 | * PHY_46/174/302/430 |
| 941 | * phy_rdlvl_status_obs_X:16:8 |
| 942 | */ |
| 943 | if ((((tmp >> 8) & 0x1) == 0x1) && |
| 944 | (((tmp >> 13) & 0x1) == 0x1) && |
| 945 | (((tmp >> 2) & 0x1) == 0x0)) |
| 946 | break; |
| 947 | else if (((tmp >> 2) & 0x1) == 0x1) |
| 948 | return -EIO; |
| 949 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 950 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 951 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 952 | writel(0x00003f7c, (&denali_pi[175])); |
| 953 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 954 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 955 | clrbits_le32(&denali_pi[80], 0x3 << 16); |
| 956 | |
| 957 | return 0; |
| 958 | } |
| 959 | |
| 960 | static int data_training_wdql(const struct chan_info *chan, u32 channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 961 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 962 | { |
| 963 | u32 *denali_pi = chan->pi->denali_pi; |
| 964 | u32 i, tmp; |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 965 | u32 rank = params->ch[channel].cap_info.rank; |
Jagan Teki | 21cf392 | 2019-07-15 23:58:42 +0530 | [diff] [blame] | 966 | u32 rank_mask; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 967 | |
Jagan Teki | 01976ae | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 968 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 969 | writel(0x00003f7c, (&denali_pi[175])); |
| 970 | |
Jagan Teki | c716bf6 | 2019-07-16 17:27:10 +0530 | [diff] [blame] | 971 | if (params->base.dramtype == LPDDR4) |
| 972 | rank_mask = (rank == 1) ? 0x5 : 0xf; |
| 973 | else |
| 974 | rank_mask = (rank == 1) ? 0x1 : 0x3; |
Jagan Teki | 21cf392 | 2019-07-15 23:58:42 +0530 | [diff] [blame] | 975 | |
| 976 | for (i = 0; i < 4; i++) { |
| 977 | if (!(rank_mask & (1 << i))) |
| 978 | continue; |
| 979 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 980 | select_per_cs_training_index(chan, i); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 981 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 982 | /* |
| 983 | * disable PI_WDQLVL_VREF_EN before wdq leveling? |
| 984 | * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 |
| 985 | */ |
| 986 | clrbits_le32(&denali_pi[181], 0x1 << 8); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 987 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 988 | /* PI_124 PI_WDQLVL_EN:RW:16:2 */ |
| 989 | clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 990 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 991 | /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ |
| 992 | clrsetbits_le32(&denali_pi[121], |
| 993 | (0x1 << 8) | (0x3 << 16), |
| 994 | (0x1 << 8) | (i << 16)); |
| 995 | |
| 996 | /* Waiting for training complete */ |
| 997 | while (1) { |
| 998 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 999 | tmp = readl(&denali_pi[174]) >> 8; |
| 1000 | if ((((tmp >> 12) & 0x1) == 0x1) && |
| 1001 | (((tmp >> 13) & 0x1) == 0x1) && |
| 1002 | (((tmp >> 6) & 0x1) == 0x0)) |
| 1003 | break; |
| 1004 | else if (((tmp >> 6) & 0x1) == 0x1) |
| 1005 | return -EIO; |
| 1006 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1007 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1008 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1009 | writel(0x00003f7c, (&denali_pi[175])); |
| 1010 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1011 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1012 | clrbits_le32(&denali_pi[124], 0x3 << 16); |
| 1013 | |
| 1014 | return 0; |
| 1015 | } |
| 1016 | |
| 1017 | static int data_training(const struct chan_info *chan, u32 channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1018 | const struct rk3399_sdram_params *params, |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1019 | u32 training_flag) |
| 1020 | { |
| 1021 | u32 *denali_phy = chan->publ->denali_phy; |
Jagan Teki | 02fad6f | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1022 | int ret; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1023 | |
| 1024 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
| 1025 | setbits_le32(&denali_phy[927], (1 << 22)); |
| 1026 | |
| 1027 | if (training_flag == PI_FULL_TRAINING) { |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1028 | if (params->base.dramtype == LPDDR4) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1029 | training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | |
| 1030 | PI_READ_GATE_TRAINING | |
| 1031 | PI_READ_LEVELING | PI_WDQ_LEVELING; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1032 | } else if (params->base.dramtype == LPDDR3) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1033 | training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | |
| 1034 | PI_READ_GATE_TRAINING; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1035 | } else if (params->base.dramtype == DDR3) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1036 | training_flag = PI_WRITE_LEVELING | |
| 1037 | PI_READ_GATE_TRAINING | |
| 1038 | PI_READ_LEVELING; |
| 1039 | } |
| 1040 | } |
| 1041 | |
| 1042 | /* ca training(LPDDR4,LPDDR3 support) */ |
Jagan Teki | 02fad6f | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1043 | if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { |
| 1044 | ret = data_training_ca(chan, channel, params); |
| 1045 | if (ret < 0) { |
| 1046 | debug("%s: data training ca failed\n", __func__); |
| 1047 | return ret; |
| 1048 | } |
| 1049 | } |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1050 | |
| 1051 | /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ |
Jagan Teki | 02fad6f | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1052 | if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { |
| 1053 | ret = data_training_wl(chan, channel, params); |
| 1054 | if (ret < 0) { |
| 1055 | debug("%s: data training wl failed\n", __func__); |
| 1056 | return ret; |
| 1057 | } |
| 1058 | } |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1059 | |
| 1060 | /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ |
Jagan Teki | 02fad6f | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1061 | if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { |
| 1062 | ret = data_training_rg(chan, channel, params); |
| 1063 | if (ret < 0) { |
| 1064 | debug("%s: data training rg failed\n", __func__); |
| 1065 | return ret; |
| 1066 | } |
| 1067 | } |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1068 | |
| 1069 | /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ |
Jagan Teki | 02fad6f | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1070 | if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { |
| 1071 | ret = data_training_rl(chan, channel, params); |
| 1072 | if (ret < 0) { |
| 1073 | debug("%s: data training rl failed\n", __func__); |
| 1074 | return ret; |
| 1075 | } |
| 1076 | } |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1077 | |
| 1078 | /* wdq leveling(LPDDR4 support) */ |
Jagan Teki | 02fad6f | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1079 | if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { |
| 1080 | ret = data_training_wdql(chan, channel, params); |
| 1081 | if (ret < 0) { |
| 1082 | debug("%s: data training wdql failed\n", __func__); |
| 1083 | return ret; |
| 1084 | } |
| 1085 | } |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1086 | |
| 1087 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
| 1088 | clrbits_le32(&denali_phy[927], (1 << 22)); |
| 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
| 1093 | static void set_ddrconfig(const struct chan_info *chan, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1094 | const struct rk3399_sdram_params *params, |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1095 | unsigned char channel, u32 ddrconfig) |
| 1096 | { |
| 1097 | /* only need to set ddrconfig */ |
| 1098 | struct rk3399_msch_regs *ddr_msch_regs = chan->msch; |
| 1099 | unsigned int cs0_cap = 0; |
| 1100 | unsigned int cs1_cap = 0; |
| 1101 | |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1102 | cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row |
| 1103 | + params->ch[channel].cap_info.col |
| 1104 | + params->ch[channel].cap_info.bk |
| 1105 | + params->ch[channel].cap_info.bw - 20)); |
| 1106 | if (params->ch[channel].cap_info.rank > 1) |
| 1107 | cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row |
| 1108 | - params->ch[channel].cap_info.cs1_row); |
| 1109 | if (params->ch[channel].cap_info.row_3_4) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1110 | cs0_cap = cs0_cap * 3 / 4; |
| 1111 | cs1_cap = cs1_cap * 3 / 4; |
| 1112 | } |
| 1113 | |
| 1114 | writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); |
| 1115 | writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), |
| 1116 | &ddr_msch_regs->ddrsize); |
| 1117 | } |
| 1118 | |
| 1119 | static void dram_all_config(struct dram_info *dram, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1120 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1121 | { |
Jagan Teki | e0ddb0b | 2019-07-16 17:27:00 +0530 | [diff] [blame] | 1122 | u32 sys_reg2 = 0; |
Jagan Teki | 01cc103 | 2019-07-16 17:27:01 +0530 | [diff] [blame] | 1123 | u32 sys_reg3 = 0; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1124 | unsigned int channel, idx; |
| 1125 | |
Jagan Teki | e0ddb0b | 2019-07-16 17:27:00 +0530 | [diff] [blame] | 1126 | sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); |
| 1127 | sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1128 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1129 | for (channel = 0, idx = 0; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1130 | (idx < params->base.num_channels) && (channel < 2); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1131 | channel++) { |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1132 | const struct rk3399_sdram_channel *info = ¶ms->ch[channel]; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1133 | struct rk3399_msch_regs *ddr_msch_regs; |
| 1134 | const struct rk3399_msch_timings *noc_timing; |
| 1135 | |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1136 | if (params->ch[channel].cap_info.col == 0) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1137 | continue; |
| 1138 | idx++; |
Jagan Teki | e0ddb0b | 2019-07-16 17:27:00 +0530 | [diff] [blame] | 1139 | sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); |
| 1140 | sys_reg2 |= SYS_REG_ENC_CHINFO(channel); |
| 1141 | sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); |
| 1142 | sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); |
| 1143 | sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); |
Jagan Teki | e0ddb0b | 2019-07-16 17:27:00 +0530 | [diff] [blame] | 1144 | sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); |
| 1145 | sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); |
Jagan Teki | 01cc103 | 2019-07-16 17:27:01 +0530 | [diff] [blame] | 1146 | SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel); |
| 1147 | if (info->cap_info.cs1_row) |
| 1148 | SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2, |
| 1149 | sys_reg3, channel); |
| 1150 | sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel); |
Jagan Teki | b713e02 | 2019-07-16 17:27:04 +0530 | [diff] [blame] | 1151 | sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1152 | |
| 1153 | ddr_msch_regs = dram->chan[channel].msch; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1154 | noc_timing = ¶ms->ch[channel].noc_timings; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1155 | writel(noc_timing->ddrtiminga0, |
| 1156 | &ddr_msch_regs->ddrtiminga0); |
| 1157 | writel(noc_timing->ddrtimingb0, |
| 1158 | &ddr_msch_regs->ddrtimingb0); |
Jagan Teki | ed77ce7 | 2019-07-16 17:27:05 +0530 | [diff] [blame] | 1159 | writel(noc_timing->ddrtimingc0.d32, |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1160 | &ddr_msch_regs->ddrtimingc0); |
| 1161 | writel(noc_timing->devtodev0, |
| 1162 | &ddr_msch_regs->devtodev0); |
Jagan Teki | a735550 | 2019-07-16 17:27:06 +0530 | [diff] [blame] | 1163 | writel(noc_timing->ddrmode.d32, |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1164 | &ddr_msch_regs->ddrmode); |
| 1165 | |
| 1166 | /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ |
Jagan Teki | 355490d | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1167 | if (params->ch[channel].cap_info.rank == 1) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1168 | setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], |
| 1169 | 1 << 17); |
| 1170 | } |
| 1171 | |
Jagan Teki | e0ddb0b | 2019-07-16 17:27:00 +0530 | [diff] [blame] | 1172 | writel(sys_reg2, &dram->pmugrf->os_reg2); |
Jagan Teki | 01cc103 | 2019-07-16 17:27:01 +0530 | [diff] [blame] | 1173 | writel(sys_reg3, &dram->pmugrf->os_reg3); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1174 | rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1175 | params->base.stride << 10); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1176 | |
| 1177 | /* reboot hold register set */ |
| 1178 | writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | |
| 1179 | PRESET_GPIO1_HOLD(1), |
| 1180 | &dram->pmucru->pmucru_rstnhold_con[1]); |
| 1181 | clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); |
| 1182 | } |
| 1183 | |
| 1184 | static int switch_to_phy_index1(struct dram_info *dram, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1185 | const struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1186 | { |
| 1187 | u32 channel; |
| 1188 | u32 *denali_phy; |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1189 | u32 ch_count = params->base.num_channels; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1190 | int ret; |
| 1191 | int i = 0; |
| 1192 | |
| 1193 | writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, |
| 1194 | 1 << 4 | 1 << 2 | 1), |
| 1195 | &dram->cic->cic_ctrl0); |
| 1196 | while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { |
| 1197 | mdelay(10); |
| 1198 | i++; |
| 1199 | if (i > 10) { |
| 1200 | debug("index1 frequency change overtime\n"); |
| 1201 | return -ETIME; |
| 1202 | } |
| 1203 | } |
| 1204 | |
| 1205 | i = 0; |
| 1206 | writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); |
| 1207 | while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { |
| 1208 | mdelay(10); |
Heinrich Schuchardt | 2ebc80e | 2018-03-18 12:10:55 +0100 | [diff] [blame] | 1209 | i++; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1210 | if (i > 10) { |
| 1211 | debug("index1 frequency done overtime\n"); |
| 1212 | return -ETIME; |
| 1213 | } |
| 1214 | } |
| 1215 | |
| 1216 | for (channel = 0; channel < ch_count; channel++) { |
| 1217 | denali_phy = dram->chan[channel].publ->denali_phy; |
| 1218 | clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); |
| 1219 | ret = data_training(&dram->chan[channel], channel, |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1220 | params, PI_FULL_TRAINING); |
Jagan Teki | 02fad6f | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1221 | if (ret < 0) { |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1222 | debug("index1 training failed\n"); |
| 1223 | return ret; |
| 1224 | } |
| 1225 | } |
| 1226 | |
| 1227 | return 0; |
| 1228 | } |
| 1229 | |
Jagan Teki | 4b09719 | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 1230 | static unsigned char calculate_stride(struct rk3399_sdram_params *params) |
| 1231 | { |
| 1232 | unsigned int stride = params->base.stride; |
| 1233 | unsigned int channel, chinfo = 0; |
| 1234 | unsigned int ch_cap[2] = {0, 0}; |
| 1235 | u64 cap; |
| 1236 | |
| 1237 | for (channel = 0; channel < 2; channel++) { |
| 1238 | unsigned int cs0_cap = 0; |
| 1239 | unsigned int cs1_cap = 0; |
| 1240 | struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info; |
| 1241 | |
| 1242 | if (cap_info->col == 0) |
| 1243 | continue; |
| 1244 | |
| 1245 | cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + |
| 1246 | cap_info->bk + cap_info->bw - 20)); |
| 1247 | if (cap_info->rank > 1) |
| 1248 | cs1_cap = cs0_cap >> (cap_info->cs0_row |
| 1249 | - cap_info->cs1_row); |
| 1250 | if (cap_info->row_3_4) { |
| 1251 | cs0_cap = cs0_cap * 3 / 4; |
| 1252 | cs1_cap = cs1_cap * 3 / 4; |
| 1253 | } |
| 1254 | ch_cap[channel] = cs0_cap + cs1_cap; |
| 1255 | chinfo |= 1 << channel; |
| 1256 | } |
| 1257 | |
Jagan Teki | 1ff5283 | 2019-07-15 23:58:53 +0530 | [diff] [blame] | 1258 | /* stride calculation for 1 channel */ |
| 1259 | if (params->base.num_channels == 1 && chinfo & 1) |
| 1260 | return 0x17; /* channel a */ |
| 1261 | |
Jagan Teki | 4b09719 | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 1262 | /* stride calculation for 2 channels, default gstride type is 256B */ |
| 1263 | if (ch_cap[0] == ch_cap[1]) { |
| 1264 | cap = ch_cap[0] + ch_cap[1]; |
| 1265 | switch (cap) { |
| 1266 | /* 512MB */ |
| 1267 | case 512: |
| 1268 | stride = 0; |
| 1269 | break; |
| 1270 | /* 1GB */ |
| 1271 | case 1024: |
| 1272 | stride = 0x5; |
| 1273 | break; |
| 1274 | /* |
| 1275 | * 768MB + 768MB same as total 2GB memory |
| 1276 | * useful space: 0-768MB 1GB-1792MB |
| 1277 | */ |
| 1278 | case 1536: |
| 1279 | /* 2GB */ |
| 1280 | case 2048: |
| 1281 | stride = 0x9; |
| 1282 | break; |
| 1283 | /* 1536MB + 1536MB */ |
| 1284 | case 3072: |
| 1285 | stride = 0x11; |
| 1286 | break; |
| 1287 | /* 4GB */ |
| 1288 | case 4096: |
| 1289 | stride = 0xD; |
| 1290 | break; |
| 1291 | default: |
| 1292 | printf("%s: Unable to calculate stride for ", __func__); |
| 1293 | print_size((cap * (1 << 20)), " capacity\n"); |
| 1294 | break; |
| 1295 | } |
| 1296 | } |
| 1297 | |
Jagan Teki | a9191b8 | 2019-07-15 23:58:55 +0530 | [diff] [blame] | 1298 | sdram_print_stride(stride); |
| 1299 | |
Jagan Teki | 4b09719 | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 1300 | return stride; |
| 1301 | } |
| 1302 | |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1303 | static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel) |
| 1304 | { |
| 1305 | params->ch[channel].cap_info.rank = 0; |
| 1306 | params->ch[channel].cap_info.col = 0; |
| 1307 | params->ch[channel].cap_info.bk = 0; |
| 1308 | params->ch[channel].cap_info.bw = 32; |
| 1309 | params->ch[channel].cap_info.dbw = 32; |
| 1310 | params->ch[channel].cap_info.row_3_4 = 0; |
| 1311 | params->ch[channel].cap_info.cs0_row = 0; |
| 1312 | params->ch[channel].cap_info.cs1_row = 0; |
| 1313 | params->ch[channel].cap_info.ddrconfig = 0; |
| 1314 | } |
| 1315 | |
| 1316 | static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params) |
| 1317 | { |
| 1318 | int channel; |
| 1319 | int ret; |
| 1320 | |
| 1321 | for (channel = 0; channel < 2; channel++) { |
| 1322 | const struct chan_info *chan = &dram->chan[channel]; |
| 1323 | struct rk3399_cru *cru = dram->cru; |
| 1324 | struct rk3399_ddr_publ_regs *publ = chan->publ; |
| 1325 | |
| 1326 | phy_pctrl_reset(cru, channel); |
| 1327 | phy_dll_bypass_set(publ, params->base.ddr_freq); |
| 1328 | |
| 1329 | ret = pctl_cfg(dram, chan, channel, params); |
| 1330 | if (ret < 0) { |
| 1331 | printf("%s: pctl config failed\n", __func__); |
| 1332 | return ret; |
| 1333 | } |
| 1334 | |
| 1335 | /* start to trigger initialization */ |
| 1336 | pctl_start(dram, channel); |
| 1337 | } |
| 1338 | |
| 1339 | return 0; |
| 1340 | } |
| 1341 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1342 | static int sdram_init(struct dram_info *dram, |
Jagan Teki | 4b09719 | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 1343 | struct rk3399_sdram_params *params) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1344 | { |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1345 | unsigned char dramtype = params->base.dramtype; |
| 1346 | unsigned int ddr_freq = params->base.ddr_freq; |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1347 | u32 training_flag = PI_READ_GATE_TRAINING; |
| 1348 | int channel, ch, rank; |
Jagan Teki | d4b4bb4 | 2019-07-15 23:50:59 +0530 | [diff] [blame] | 1349 | int ret; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1350 | |
| 1351 | debug("Starting SDRAM initialization...\n"); |
| 1352 | |
Philipp Tomsich | fcb2158 | 2017-05-31 18:16:35 +0200 | [diff] [blame] | 1353 | if ((dramtype == DDR3 && ddr_freq > 933) || |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1354 | (dramtype == LPDDR3 && ddr_freq > 933) || |
| 1355 | (dramtype == LPDDR4 && ddr_freq > 800)) { |
| 1356 | debug("SDRAM frequency is to high!"); |
| 1357 | return -E2BIG; |
| 1358 | } |
| 1359 | |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1360 | for (ch = 0; ch < 2; ch++) { |
| 1361 | params->ch[ch].cap_info.rank = 2; |
| 1362 | for (rank = 2; rank != 0; rank--) { |
| 1363 | ret = pctl_init(dram, params); |
| 1364 | if (ret < 0) { |
| 1365 | printf("%s: pctl init failed\n", __func__); |
| 1366 | return ret; |
| 1367 | } |
| 1368 | |
| 1369 | /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ |
| 1370 | if (dramtype == LPDDR3) |
| 1371 | udelay(10); |
| 1372 | |
| 1373 | params->ch[ch].cap_info.rank = rank; |
| 1374 | |
| 1375 | /* |
| 1376 | * LPDDR3 CA training msut be trigger before |
| 1377 | * other training. |
| 1378 | * DDR3 is not have CA training. |
| 1379 | */ |
| 1380 | if (params->base.dramtype == LPDDR3) |
| 1381 | training_flag |= PI_CA_TRAINING; |
| 1382 | |
| 1383 | if (!(data_training(&dram->chan[ch], ch, |
| 1384 | params, training_flag))) |
| 1385 | break; |
| 1386 | } |
| 1387 | /* Computed rank with associated channel number */ |
| 1388 | params->ch[ch].cap_info.rank = rank; |
| 1389 | } |
| 1390 | |
| 1391 | params->base.num_channels = 0; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1392 | for (channel = 0; channel < 2; channel++) { |
| 1393 | const struct chan_info *chan = &dram->chan[channel]; |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1394 | struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info; |
| 1395 | u8 training_flag = PI_FULL_TRAINING; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1396 | |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1397 | if (cap_info->rank == 0) { |
| 1398 | clear_channel_params(params, channel); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1399 | continue; |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1400 | } else { |
| 1401 | params->base.num_channels++; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1402 | } |
| 1403 | |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1404 | debug("Channel "); |
| 1405 | debug(channel ? "1: " : "0: "); |
Jagan Teki | a0aebe8 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 1406 | |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1407 | /* LPDDR3 should have write and read gate training */ |
| 1408 | if (params->base.dramtype == LPDDR3) |
| 1409 | training_flag = PI_WRITE_LEVELING | |
| 1410 | PI_READ_GATE_TRAINING; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1411 | |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1412 | if (params->base.dramtype != LPDDR4) { |
| 1413 | ret = data_training(dram, channel, params, |
| 1414 | training_flag); |
| 1415 | if (!ret) { |
| 1416 | debug("%s: data train failed for channel %d\n", |
| 1417 | __func__, ret); |
| 1418 | continue; |
| 1419 | } |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1420 | } |
| 1421 | |
Jagan Teki | a9191b8 | 2019-07-15 23:58:55 +0530 | [diff] [blame] | 1422 | sdram_print_ddr_info(cap_info, ¶ms->base); |
| 1423 | |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1424 | set_ddrconfig(chan, params, channel, cap_info->ddrconfig); |
| 1425 | } |
| 1426 | |
| 1427 | if (params->base.num_channels == 0) { |
| 1428 | printf("%s: ", __func__); |
Jagan Teki | a9191b8 | 2019-07-15 23:58:55 +0530 | [diff] [blame] | 1429 | sdram_print_dram_type(params->base.dramtype); |
Jagan Teki | d0ba88f | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 1430 | printf(" - %dMHz failed!\n", params->base.ddr_freq); |
| 1431 | return -EINVAL; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1432 | } |
Jagan Teki | 4b09719 | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 1433 | |
| 1434 | params->base.stride = calculate_stride(params); |
Jagan Teki | fde7f45 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1435 | dram_all_config(dram, params); |
| 1436 | switch_to_phy_index1(dram, params); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1437 | |
| 1438 | debug("Finish SDRAM initialization...\n"); |
| 1439 | return 0; |
| 1440 | } |
| 1441 | |
| 1442 | static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) |
| 1443 | { |
| 1444 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 1445 | struct rockchip_dmc_plat *plat = dev_get_platdata(dev); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1446 | int ret; |
| 1447 | |
Philipp Tomsich | 8f1034e | 2017-06-07 18:46:03 +0200 | [diff] [blame] | 1448 | ret = dev_read_u32_array(dev, "rockchip,sdram-params", |
| 1449 | (u32 *)&plat->sdram_params, |
| 1450 | sizeof(plat->sdram_params) / sizeof(u32)); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1451 | if (ret) { |
| 1452 | printf("%s: Cannot read rockchip,sdram-params %d\n", |
| 1453 | __func__, ret); |
| 1454 | return ret; |
| 1455 | } |
Masahiro Yamada | d358123 | 2018-04-19 12:14:03 +0900 | [diff] [blame] | 1456 | ret = regmap_init_mem(dev_ofnode(dev), &plat->map); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1457 | if (ret) |
| 1458 | printf("%s: regmap failed %d\n", __func__, ret); |
| 1459 | |
| 1460 | #endif |
| 1461 | return 0; |
| 1462 | } |
| 1463 | |
| 1464 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 1465 | static int conv_of_platdata(struct udevice *dev) |
| 1466 | { |
| 1467 | struct rockchip_dmc_plat *plat = dev_get_platdata(dev); |
| 1468 | struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; |
| 1469 | int ret; |
| 1470 | |
| 1471 | ret = regmap_init_mem_platdata(dev, dtplat->reg, |
Jagan Teki | 63f4d71 | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 1472 | ARRAY_SIZE(dtplat->reg) / 2, |
| 1473 | &plat->map); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1474 | if (ret) |
| 1475 | return ret; |
| 1476 | |
| 1477 | return 0; |
| 1478 | } |
| 1479 | #endif |
| 1480 | |
| 1481 | static int rk3399_dmc_init(struct udevice *dev) |
| 1482 | { |
| 1483 | struct dram_info *priv = dev_get_priv(dev); |
| 1484 | struct rockchip_dmc_plat *plat = dev_get_platdata(dev); |
| 1485 | int ret; |
| 1486 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 1487 | struct rk3399_sdram_params *params = &plat->sdram_params; |
| 1488 | #else |
| 1489 | struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; |
| 1490 | struct rk3399_sdram_params *params = |
| 1491 | (void *)dtplat->rockchip_sdram_params; |
| 1492 | |
| 1493 | ret = conv_of_platdata(dev); |
| 1494 | if (ret) |
| 1495 | return ret; |
| 1496 | #endif |
| 1497 | |
| 1498 | priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); |
Jagan Teki | a0aebe8 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 1499 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1500 | priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
| 1501 | priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); |
| 1502 | priv->pmucru = rockchip_get_pmucru(); |
| 1503 | priv->cru = rockchip_get_cru(); |
| 1504 | priv->chan[0].pctl = regmap_get_range(plat->map, 0); |
| 1505 | priv->chan[0].pi = regmap_get_range(plat->map, 1); |
| 1506 | priv->chan[0].publ = regmap_get_range(plat->map, 2); |
| 1507 | priv->chan[0].msch = regmap_get_range(plat->map, 3); |
| 1508 | priv->chan[1].pctl = regmap_get_range(plat->map, 4); |
| 1509 | priv->chan[1].pi = regmap_get_range(plat->map, 5); |
| 1510 | priv->chan[1].publ = regmap_get_range(plat->map, 6); |
| 1511 | priv->chan[1].msch = regmap_get_range(plat->map, 7); |
| 1512 | |
| 1513 | debug("con reg %p %p %p %p %p %p %p %p\n", |
| 1514 | priv->chan[0].pctl, priv->chan[0].pi, |
| 1515 | priv->chan[0].publ, priv->chan[0].msch, |
| 1516 | priv->chan[1].pctl, priv->chan[1].pi, |
| 1517 | priv->chan[1].publ, priv->chan[1].msch); |
| 1518 | debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, |
| 1519 | priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1520 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1521 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 1522 | ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); |
| 1523 | #else |
| 1524 | ret = clk_get_by_index(dev, 0, &priv->ddr_clk); |
| 1525 | #endif |
| 1526 | if (ret) { |
| 1527 | printf("%s clk get failed %d\n", __func__, ret); |
| 1528 | return ret; |
| 1529 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1530 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1531 | ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); |
| 1532 | if (ret < 0) { |
| 1533 | printf("%s clk set failed %d\n", __func__, ret); |
| 1534 | return ret; |
| 1535 | } |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1536 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1537 | ret = sdram_init(priv, params); |
| 1538 | if (ret < 0) { |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1539 | printf("%s DRAM init failed %d\n", __func__, ret); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1540 | return ret; |
| 1541 | } |
| 1542 | |
| 1543 | return 0; |
| 1544 | } |
| 1545 | #endif |
| 1546 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1547 | static int rk3399_dmc_probe(struct udevice *dev) |
| 1548 | { |
Kever Yang | 8276334 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 1549 | #if defined(CONFIG_TPL_BUILD) || \ |
| 1550 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1551 | if (rk3399_dmc_init(dev)) |
| 1552 | return 0; |
| 1553 | #else |
| 1554 | struct dram_info *priv = dev_get_priv(dev); |
| 1555 | |
| 1556 | priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
Jagan Teki | 3eaf539 | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1557 | debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); |
Kever Yang | 7805cdf | 2017-06-23 16:11:06 +0800 | [diff] [blame] | 1558 | priv->info.base = CONFIG_SYS_SDRAM_BASE; |
Jagan Teki | 63f4d71 | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 1559 | priv->info.size = |
| 1560 | rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1561 | #endif |
| 1562 | return 0; |
| 1563 | } |
| 1564 | |
| 1565 | static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) |
| 1566 | { |
| 1567 | struct dram_info *priv = dev_get_priv(dev); |
| 1568 | |
Kever Yang | 76e1693 | 2017-04-19 16:01:14 +0800 | [diff] [blame] | 1569 | *info = priv->info; |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1570 | |
| 1571 | return 0; |
| 1572 | } |
| 1573 | |
| 1574 | static struct ram_ops rk3399_dmc_ops = { |
| 1575 | .get_info = rk3399_dmc_get_info, |
| 1576 | }; |
| 1577 | |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1578 | static const struct udevice_id rk3399_dmc_ids[] = { |
| 1579 | { .compatible = "rockchip,rk3399-dmc" }, |
| 1580 | { } |
| 1581 | }; |
| 1582 | |
| 1583 | U_BOOT_DRIVER(dmc_rk3399) = { |
| 1584 | .name = "rockchip_rk3399_dmc", |
| 1585 | .id = UCLASS_RAM, |
| 1586 | .of_match = rk3399_dmc_ids, |
| 1587 | .ops = &rk3399_dmc_ops, |
Kever Yang | 8276334 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 1588 | #if defined(CONFIG_TPL_BUILD) || \ |
| 1589 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1590 | .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, |
| 1591 | #endif |
| 1592 | .probe = rk3399_dmc_probe, |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1593 | .priv_auto_alloc_size = sizeof(struct dram_info), |
Kever Yang | 8276334 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 1594 | #if defined(CONFIG_TPL_BUILD) || \ |
| 1595 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | fa43743 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1596 | .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), |
| 1597 | #endif |
| 1598 | }; |