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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 9a8bcabd8adac3382bc23bef450a6793e5144110 / . / arch / sandbox / dts / test.dts
blob: 70356461959d34691e8d867341a4904869429170 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]17 pci0 = &pci0;
18 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]19 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]20 remoteproc1 = &rproc_1;
21 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]22 rtc0 = &rtc_0;
23 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]24 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]25 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]26 testbus3 = "/some-bus";
27 testfdt0 = "/some-bus/c-test@0";
28 testfdt1 = "/some-bus/c-test@1";
29 testfdt3 = "/b-test";
30 testfdt5 = "/some-bus/c-test@5";
31 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]32 fdt-dummy0 = "/translation-test@8000/dev@0,0";
33 fdt-dummy1 = "/translation-test@8000/dev@1,100";
34 fdt-dummy2 = "/translation-test@8000/dev@2,200";
35 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]36 usb0 = &usb_0;
37 usb1 = &usb_1;
38 usb2 = &usb_2;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]39 };
40
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]41 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]42 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]43 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]44 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]45 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]46 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]47 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
48 <0>, <&gpio_a 12>;
49 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
50 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
51 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]52 };
53
54 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]55 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]56 compatible = "not,compatible";
57 };
58
59 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]60 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]61 };
62
63 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]64 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]65 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]66 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]67 ping-add = <3>;
68 };
69
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]70 phy_provider0: gen_phy@0 {
71 compatible = "sandbox,phy";
72 #phy-cells = <1>;
73 };
74
75 phy_provider1: gen_phy@1 {
76 compatible = "sandbox,phy";
77 #phy-cells = <0>;
78 broken;
79 };
80
81 gen_phy_user: gen_phy_user {
82 compatible = "simple-bus";
83 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
84 phy-names = "phy1", "phy2", "phy3";
85 };
86
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]87 some-bus {
88 #address-cells = <1>;
89 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]90 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]91 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]92 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]93 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]94 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]95 compatible = "denx,u-boot-fdt-test";
96 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]97 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]98 ping-add = <5>;
99 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]100 c-test@0 {
101 compatible = "denx,u-boot-fdt-test";
102 reg = <0>;
103 ping-expect = <6>;
104 ping-add = <6>;
105 };
106 c-test@1 {
107 compatible = "denx,u-boot-fdt-test";
108 reg = <1>;
109 ping-expect = <7>;
110 ping-add = <7>;
111 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]112 };
113
114 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]115 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]116 ping-expect = <6>;
117 ping-add = <6>;
118 compatible = "google,another-fdt-test";
119 };
120
121 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]122 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]123 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]124 ping-add = <6>;
125 compatible = "google,another-fdt-test";
126 };
127
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]128 f-test {
129 compatible = "denx,u-boot-fdt-test";
130 };
131
132 g-test {
133 compatible = "denx,u-boot-fdt-test";
134 };
135
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]136 clocks {
137 clk_fixed: clk-fixed {
138 compatible = "fixed-clock";
139 #clock-cells = <0>;
140 clock-frequency = <1234>;
141 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]142 };
143
144 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]145 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]146 #clock-cells = <1>;
147 };
148
149 clk-test {
150 compatible = "sandbox,clk-test";
151 clocks = <&clk_fixed>,
152 <&clk_sandbox 1>,
153 <&clk_sandbox 0>;
154 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]155 };
156
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]157 eth@10002000 {
158 compatible = "sandbox,eth";
159 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]160 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]161 };
162
163 eth_5: eth@10003000 {
164 compatible = "sandbox,eth";
165 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]166 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]167 };
168
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]169 eth_3: sbe5 {
170 compatible = "sandbox,eth";
171 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]172 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]173 };
174
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]175 eth@10004000 {
176 compatible = "sandbox,eth";
177 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]178 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]179 };
180
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]181 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]182 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]183 gpio-controller;
184 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]185 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]186 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]187 };
188
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]189 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]190 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]191 gpio-controller;
192 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]193 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]194 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]195 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]196
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]197 i2c@0 {
198 #address-cells = <1>;
199 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]200 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]201 compatible = "sandbox,i2c";
202 clock-frequency = <100000>;
203 eeprom@2c {
204 reg = <0x2c>;
205 compatible = "i2c-eeprom";
206 emul {
207 compatible = "sandbox,i2c-eeprom";
208 sandbox,filename = "i2c.bin";
209 sandbox,size = <256>;
210 };
211 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]212
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]213 rtc_0: rtc@43 {
214 reg = <0x43>;
215 compatible = "sandbox-rtc";
216 emul {
217 compatible = "sandbox,i2c-rtc";
218 };
219 };
220
221 rtc_1: rtc@61 {
222 reg = <0x61>;
223 compatible = "sandbox-rtc";
224 emul {
225 compatible = "sandbox,i2c-rtc";
226 };
227 };
228
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]229 sandbox_pmic: sandbox_pmic {
230 reg = <0x40>;
231 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]232
233 mc34708: pmic@41 {
234 reg = <0x41>;
235 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]236 };
237
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]238 adc@0 {
239 compatible = "sandbox,adc";
240 vdd-supply = <&buck2>;
241 vss-microvolts = <0>;
242 };
243
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]244 lcd {
245 u-boot,dm-pre-reloc;
246 compatible = "sandbox,lcd-sdl";
247 xres = <1366>;
248 yres = <768>;
249 };
250
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]251 leds {
252 compatible = "gpio-leds";
253
254 iracibble {
255 gpios = <&gpio_a 1 0>;
256 label = "sandbox:red";
257 };
258
259 martinet {
260 gpios = <&gpio_a 2 0>;
261 label = "sandbox:green";
262 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]263
264 default_on {
265 gpios = <&gpio_a 5 0>;
266 label = "sandbox:default_on";
267 default-state = "on";
268 };
269
270 default_off {
271 gpios = <&gpio_a 6 0>;
272 label = "sandbox:default_off";
273 default-state = "off";
274 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]275 };
276
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]277 mbox: mbox {
278 compatible = "sandbox,mbox";
279 #mbox-cells = <1>;
280 };
281
282 mbox-test {
283 compatible = "sandbox,mbox-test";
284 mboxes = <&mbox 100>, <&mbox 1>;
285 mbox-names = "other", "test";
286 };
287
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]288 mmc2 {
289 compatible = "sandbox,mmc";
290 };
291
292 mmc1 {
293 compatible = "sandbox,mmc";
294 };
295
296 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]297 compatible = "sandbox,mmc";
298 };
299
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]300 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]301 compatible = "sandbox,pci";
302 device_type = "pci";
303 #address-cells = <3>;
304 #size-cells = <2>;
305 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
306 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]307 pci@0,0 {
308 compatible = "pci-generic";
309 reg = <0x0000 0 0 0 0>;
310 emul@0,0 {
311 compatible = "sandbox,swap-case";
312 };
313 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]314 pci@1f,0 {
315 compatible = "pci-generic";
316 reg = <0xf800 0 0 0 0>;
317 emul@1f,0 {
318 compatible = "sandbox,swap-case";
319 };
320 };
321 };
322
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]323 pci1: pci-controller1 {
324 compatible = "sandbox,pci";
325 device_type = "pci";
326 #address-cells = <3>;
327 #size-cells = <2>;
328 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
329 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]330 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
331 0x0c 0x00 0x1234 0x5678>;
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]332 };
333
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]334 pci2: pci-controller2 {
335 compatible = "sandbox,pci";
336 device_type = "pci";
337 #address-cells = <3>;
338 #size-cells = <2>;
339 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
340 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
341 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
342 pci@1f,0 {
343 compatible = "pci-generic";
344 reg = <0xf800 0 0 0 0>;
345 emul@1f,0 {
346 compatible = "sandbox,swap-case";
347 };
348 };
349 };
350
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]351 probing {
352 compatible = "simple-bus";
353 test1 {
354 compatible = "denx,u-boot-probe-test";
355 };
356
357 test2 {
358 compatible = "denx,u-boot-probe-test";
359 };
360
361 test3 {
362 compatible = "denx,u-boot-probe-test";
363 };
364
365 test4 {
366 compatible = "denx,u-boot-probe-test";
367 };
368 };
369
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]370 pwrdom: power-domain {
371 compatible = "sandbox,power-domain";
372 #power-domain-cells = <1>;
373 };
374
375 power-domain-test {
376 compatible = "sandbox,power-domain-test";
377 power-domains = <&pwrdom 2>;
378 };
379
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]380 pwm {
381 compatible = "sandbox,pwm";
382 };
383
384 pwm2 {
385 compatible = "sandbox,pwm";
386 };
387
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]388 ram {
389 compatible = "sandbox,ram";
390 };
391
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]392 reset@0 {
393 compatible = "sandbox,warm-reset";
394 };
395
396 reset@1 {
397 compatible = "sandbox,reset";
398 };
399
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]400 resetc: reset-ctl {
401 compatible = "sandbox,reset-ctl";
402 #reset-cells = <1>;
403 };
404
405 reset-ctl-test {
406 compatible = "sandbox,reset-ctl-test";
407 resets = <&resetc 100>, <&resetc 2>;
408 reset-names = "other", "test";
409 };
410
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]411 rproc_1: rproc@1 {
412 compatible = "sandbox,test-processor";
413 remoteproc-name = "remoteproc-test-dev1";
414 };
415
416 rproc_2: rproc@2 {
417 compatible = "sandbox,test-processor";
418 internal-memory-mapped;
419 remoteproc-name = "remoteproc-test-dev2";
420 };
421
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]422 smem@0 {
423 compatible = "sandbox,smem";
424 };
425
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]426 spi@0 {
427 #address-cells = <1>;
428 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]429 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]430 compatible = "sandbox,spi";
431 cs-gpios = <0>, <&gpio_a 0>;
432 spi.bin@0 {
433 reg = <0>;
434 compatible = "spansion,m25p16", "spi-flash";
435 spi-max-frequency = <40000000>;
436 sandbox,filename = "spi.bin";
437 };
438 };
439
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]440 syscon@0 {
441 compatible = "sandbox,syscon0";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]442 reg = <0x10 4>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]443 };
444
445 syscon@1 {
446 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]447 reg = <0x20 5
448 0x28 6
449 0x30 7
450 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]451 };
452
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]453 syscon@2 {
454 compatible = "simple-mfd", "syscon";
455 reg = <0x40 5
456 0x48 6
457 0x50 7
458 0x58 8>;
459 };
460
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]461 timer {
462 compatible = "sandbox,timer";
463 clock-frequency = <1000000>;
464 };
465
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]466 tpm2 {
467 compatible = "sandbox,tpm2";
468 };
469
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]470 uart0: serial {
471 compatible = "sandbox,serial";
472 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]473 };
474
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]475 usb_0: usb@0 {
476 compatible = "sandbox,usb";
477 status = "disabled";
478 hub {
479 compatible = "sandbox,usb-hub";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 flash-stick {
483 reg = <0>;
484 compatible = "sandbox,usb-flash";
485 };
486 };
487 };
488
489 usb_1: usb@1 {
490 compatible = "sandbox,usb";
491 hub {
492 compatible = "usb-hub";
493 usb,device-class = <9>;
494 hub-emul {
495 compatible = "sandbox,usb-hub";
496 #address-cells = <1>;
497 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]498 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]499 reg = <0>;
500 compatible = "sandbox,usb-flash";
501 sandbox,filepath = "testflash.bin";
502 };
503
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]504 flash-stick@1 {
505 reg = <1>;
506 compatible = "sandbox,usb-flash";
507 sandbox,filepath = "testflash1.bin";
508 };
509
510 flash-stick@2 {
511 reg = <2>;
512 compatible = "sandbox,usb-flash";
513 sandbox,filepath = "testflash2.bin";
514 };
515
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]516 keyb@3 {
517 reg = <3>;
518 compatible = "sandbox,usb-keyb";
519 };
520
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]521 };
522 };
523 };
524
525 usb_2: usb@2 {
526 compatible = "sandbox,usb";
527 status = "disabled";
528 };
529
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]530 spmi: spmi@0 {
531 compatible = "sandbox,spmi";
532 #address-cells = <0x1>;
533 #size-cells = <0x1>;
534 pm8916@0 {
535 compatible = "qcom,spmi-pmic";
536 reg = <0x0 0x1>;
537 #address-cells = <0x1>;
538 #size-cells = <0x1>;
539
540 spmi_gpios: gpios@c000 {
541 compatible = "qcom,pm8916-gpio";
542 reg = <0xc000 0x400>;
543 gpio-controller;
544 gpio-count = <4>;
545 #gpio-cells = <2>;
546 gpio-bank-name="spmi";
547 };
548 };
549 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]550
551 wdt0: wdt@0 {
552 compatible = "sandbox,wdt";
553 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]554
555 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]556 #address-cells = <1>;
557 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]558 chosen-test {
559 compatible = "denx,u-boot-fdt-test";
560 reg = <9 1>;
561 };
562 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]563
564 translation-test@8000 {
565 compatible = "simple-bus";
566 reg = <0x8000 0x4000>;
567
568 #address-cells = <0x2>;
569 #size-cells = <0x1>;
570
571 ranges = <0 0x0 0x8000 0x1000
572 1 0x100 0x9000 0x1000
573 2 0x200 0xA000 0x1000
574 3 0x300 0xB000 0x1000
575 >;
576
577 dev@0,0 {
578 compatible = "denx,u-boot-fdt-dummy";
579 reg = <0 0x0 0x1000>;
580 };
581
582 dev@1,100 {
583 compatible = "denx,u-boot-fdt-dummy";
584 reg = <1 0x100 0x1000>;
585
586 };
587
588 dev@2,200 {
589 compatible = "denx,u-boot-fdt-dummy";
590 reg = <2 0x200 0x1000>;
591 };
592
593
594 noxlatebus@3,300 {
595 compatible = "simple-bus";
596 reg = <3 0x300 0x1000>;
597
598 #address-cells = <0x1>;
599 #size-cells = <0x0>;
600
601 dev@42 {
602 compatible = "denx,u-boot-fdt-dummy";
603 reg = <0x42>;
604 };
605 };
606 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]607};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]608
609#include "sandbox_pmic.dtsi"