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Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goede44d8ae52015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbell2c7e3b92014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergera26cd042015-05-12 14:46:23 -050021 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010022
Ian Campbellc3be2792014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbellc3be2792014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbellc3be2792014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080038 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020040 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020041 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080042 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010043
Ian Campbellc3be2792014-10-24 21:20:45 +010044config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010045 bool "sun7i (Allwinner A20)"
46 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020049 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010050 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020051 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010052
Hans de Goede5e6bacd2015-04-06 20:55:39 +020053config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010054 bool "sun8i (Allwinner A23)"
55 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080056 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020058 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010059 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080060 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010061
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053062config MACH_SUN8I_A33
63 bool "sun8i (Allwinner A33)"
64 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053067 select SUNXI_GEN_SUN6I
68 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080069 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053070
Jens Kuske1c27b7d2015-11-17 15:12:58 +010071config MACH_SUN8I_H3
72 bool "sun8i (Allwinner H3)"
73 select CPU_V7
74 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +010075 select SUPPORT_SPL
Jens Kuske1c27b7d2015-11-17 15:12:58 +010076
vishnupatekar762e24a2015-11-29 01:07:19 +080077config MACH_SUN8I_A83T
78 bool "sun8i (Allwinner A83T)"
79 select CPU_V7
80 select SUNXI_GEN_SUN6I
81 select SUPPORT_SPL
82
Hans de Goede1871a8c2015-01-13 19:25:06 +010083config MACH_SUN9I
84 bool "sun9i (Allwinner A80)"
85 select CPU_V7
86 select SUNXI_GEN_SUN6I
87
Ian Campbell2c7e3b92014-10-24 21:20:44 +010088endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +080089
Hans de Goede5e6bacd2015-04-06 20:55:39 +020090# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
91config MACH_SUN8I
92 bool
vishnupatekar762e24a2015-11-29 01:07:19 +080093 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +020094
95
Hans de Goede37781a12014-11-15 19:46:39 +010096config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +010097 int "sunxi dram clock speed"
98 default 312 if MACH_SUN6I || MACH_SUN8I
99 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100100 ---help---
101 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +0100102 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +0100103
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200104if MACH_SUN5I || MACH_SUN7I
105config DRAM_MBUS_CLK
106 int "sunxi mbus clock speed"
107 default 300
108 ---help---
109 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
110
111endif
112
Hans de Goede37781a12014-11-15 19:46:39 +0100113config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100114 int "sunxi dram zq value"
115 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
116 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100117 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100118 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100119
Hans de Goede8975cdf2015-05-13 15:00:46 +0200120config DRAM_ODT_EN
121 bool "sunxi dram odt enable"
122 default n if !MACH_SUN8I_A23
123 default y if MACH_SUN8I_A23
124 ---help---
125 Select this to enable dram odt (on die termination).
126
Hans de Goede8ffc4872015-01-17 14:24:55 +0100127if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
128config DRAM_EMR1
129 int "sunxi dram emr1 value"
130 default 0 if MACH_SUN4I
131 default 4 if MACH_SUN5I || MACH_SUN7I
132 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100133 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200134
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200135config DRAM_TPR3
136 hex "sunxi dram tpr3 value"
137 default 0
138 ---help---
139 Set the dram controller tpr3 parameter. This parameter configures
140 the delay on the command lane and also phase shifts, which are
141 applied for sampling incoming read data. The default value 0
142 means that no phase/delay adjustments are necessary. Properly
143 configuring this parameter increases reliability at high DRAM
144 clock speeds.
145
146config DRAM_DQS_GATING_DELAY
147 hex "sunxi dram dqs_gating_delay value"
148 default 0
149 ---help---
150 Set the dram controller dqs_gating_delay parmeter. Each byte
151 encodes the DQS gating delay for each byte lane. The delay
152 granularity is 1/4 cycle. For example, the value 0x05060606
153 means that the delay is 5 quarter-cycles for one lane (1.25
154 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
155 The default value 0 means autodetection. The results of hardware
156 autodetection are not very reliable and depend on the chip
157 temperature (sometimes producing different results on cold start
158 and warm reboot). But the accuracy of hardware autodetection
159 is usually good enough, unless running at really high DRAM
160 clocks speeds (up to 600MHz). If unsure, keep as 0.
161
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200162choice
163 prompt "sunxi dram timings"
164 default DRAM_TIMINGS_VENDOR_MAGIC
165 ---help---
166 Select the timings of the DDR3 chips.
167
168config DRAM_TIMINGS_VENDOR_MAGIC
169 bool "Magic vendor timings from Android"
170 ---help---
171 The same DRAM timings as in the Allwinner boot0 bootloader.
172
173config DRAM_TIMINGS_DDR3_1066F_1333H
174 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
175 ---help---
176 Use the timings of the standard JEDEC DDR3-1066F speed bin for
177 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
178 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
179 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
180 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
181 that down binning to DDR3-1066F is supported (because DDR3-1066F
182 uses a bit faster timings than DDR3-1333H).
183
184config DRAM_TIMINGS_DDR3_800E_1066G_1333J
185 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
186 ---help---
187 Use the timings of the slowest possible JEDEC speed bin for the
188 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
189 DDR3-800E, DDR3-1066G or DDR3-1333J.
190
191endchoice
192
Hans de Goede37781a12014-11-15 19:46:39 +0100193endif
194
Hans de Goede8975cdf2015-05-13 15:00:46 +0200195if MACH_SUN8I_A23
196config DRAM_ODT_CORRECTION
197 int "sunxi dram odt correction value"
198 default 0
199 ---help---
200 Set the dram odt correction value (range -255 - 255). In allwinner
201 fex files, this option is found in bits 8-15 of the u32 odt_en variable
202 in the [dram] section. When bit 31 of the odt_en variable is set
203 then the correction is negative. Usually the value for this is 0.
204endif
205
Iain Patone71b4222015-03-28 10:26:38 +0000206config SYS_CLK_FREQ
207 default 912000000 if MACH_SUN7I
208 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
209
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800210config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100211 default "sun4i" if MACH_SUN4I
212 default "sun5i" if MACH_SUN5I
213 default "sun6i" if MACH_SUN6I
214 default "sun7i" if MACH_SUN7I
215 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100216 default "sun9i" if MACH_SUN9I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200217
Masahiro Yamadadd840582014-07-30 14:08:14 +0900218config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900219 default "sunxi"
220
221config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900222 default "sunxi"
223
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200224config UART0_PORT_F
225 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200226 default n
227 ---help---
228 Repurpose the SD card slot for getting access to the UART0 serial
229 console. Primarily useful only for low level u-boot debugging on
230 tablets, where normal UART0 is difficult to access and requires
231 device disassembly and/or soldering. As the SD card can't be used
232 at the same time, the system can be only booted in the FEL mode.
233 Only enable this if you really know what you are doing.
234
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200235config OLD_SUNXI_KERNEL_COMPAT
236 boolean "Enable workarounds for booting old kernels"
237 default n
238 ---help---
239 Set this to enable various workarounds for old kernels, this results in
240 sub-optimal settings for newer kernels, only enable if needed.
241
Maxime Ripard44c79872015-10-15 22:04:07 +0200242config MMC
243 depends on !UART0_PORT_F
244 default y if ARCH_SUNXI
245
Hans de Goedecd821132014-10-02 20:29:26 +0200246config MMC0_CD_PIN
247 string "Card detect pin for mmc0"
248 default ""
249 ---help---
250 Set the card detect pin for mmc0, leave empty to not use cd. This
251 takes a string in the format understood by sunxi_name_to_gpio, e.g.
252 PH1 for pin 1 of port H.
253
254config MMC1_CD_PIN
255 string "Card detect pin for mmc1"
256 default ""
257 ---help---
258 See MMC0_CD_PIN help text.
259
260config MMC2_CD_PIN
261 string "Card detect pin for mmc2"
262 default ""
263 ---help---
264 See MMC0_CD_PIN help text.
265
266config MMC3_CD_PIN
267 string "Card detect pin for mmc3"
268 default ""
269 ---help---
270 See MMC0_CD_PIN help text.
271
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100272config MMC1_PINS
273 string "Pins for mmc1"
274 default ""
275 ---help---
276 Set the pins used for mmc1, when applicable. This takes a string in the
277 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
278
279config MMC2_PINS
280 string "Pins for mmc2"
281 default ""
282 ---help---
283 See MMC1_PINS help text.
284
285config MMC3_PINS
286 string "Pins for mmc3"
287 default ""
288 ---help---
289 See MMC1_PINS help text.
290
Hans de Goede2ccfac02014-10-02 20:43:50 +0200291config MMC_SUNXI_SLOT_EXTRA
292 int "mmc extra slot number"
293 default -1
294 ---help---
295 sunxi builds always enable mmc0, some boards also have a second sdcard
296 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
297 support for this.
298
Hans de Goede4458b7a2015-01-07 15:26:06 +0100299config USB0_VBUS_PIN
300 string "Vbus enable pin for usb0 (otg)"
301 default ""
302 ---help---
303 Set the Vbus enable pin for usb0 (otg). This takes a string in the
304 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
305
Hans de Goede52defe82015-02-16 22:13:43 +0100306config USB0_VBUS_DET
307 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100308 default ""
309 ---help---
310 Set the Vbus detect pin for usb0 (otg). This takes a string in the
311 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
312
Hans de Goede48c06c92015-06-14 17:29:53 +0200313config USB0_ID_DET
314 string "ID detect pin for usb0 (otg)"
315 default ""
316 ---help---
317 Set the ID detect pin for usb0 (otg). This takes a string in the
318 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
319
Hans de Goede115200c2014-11-07 16:09:00 +0100320config USB1_VBUS_PIN
321 string "Vbus enable pin for usb1 (ehci0)"
322 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100323 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100324 ---help---
325 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
326 a string in the format understood by sunxi_name_to_gpio, e.g.
327 PH1 for pin 1 of port H.
328
329config USB2_VBUS_PIN
330 string "Vbus enable pin for usb2 (ehci1)"
331 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100332 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100333 ---help---
334 See USB1_VBUS_PIN help text.
335
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200336config I2C0_ENABLE
337 bool "Enable I2C/TWI controller 0"
338 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
339 default n if MACH_SUN6I || MACH_SUN8I
340 ---help---
341 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
342 its clock and setting up the bus. This is especially useful on devices
343 with slaves connected to the bus or with pins exposed through e.g. an
344 expansion port/header.
345
346config I2C1_ENABLE
347 bool "Enable I2C/TWI controller 1"
348 default n
349 ---help---
350 See I2C0_ENABLE help text.
351
352config I2C2_ENABLE
353 bool "Enable I2C/TWI controller 2"
354 default n
355 ---help---
356 See I2C0_ENABLE help text.
357
358if MACH_SUN6I || MACH_SUN7I
359config I2C3_ENABLE
360 bool "Enable I2C/TWI controller 3"
361 default n
362 ---help---
363 See I2C0_ENABLE help text.
364endif
365
366if MACH_SUN7I
367config I2C4_ENABLE
368 bool "Enable I2C/TWI controller 4"
369 default n
370 ---help---
371 See I2C0_ENABLE help text.
372endif
373
Hans de Goede2fcf0332015-04-25 17:25:14 +0200374config AXP_GPIO
375 boolean "Enable support for gpio-s on axp PMICs"
376 default n
377 ---help---
378 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
379
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200380config VIDEO
Hans de Goede2dae8002014-12-21 16:28:32 +0100381 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
vishnupatekar762e24a2015-11-29 01:07:19 +0800382 depends on !MACH_SUN8I_A83T
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200383 default y
384 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100385 Say Y here to add support for using a cfb console on the HDMI, LCD
386 or VGA output found on most sunxi devices. See doc/README.video for
387 info on how to select the video output and mode.
388
Hans de Goede2fbf0912014-12-23 23:04:35 +0100389config VIDEO_HDMI
390 boolean "HDMI output support"
391 depends on VIDEO && !MACH_SUN8I
392 default y
393 ---help---
394 Say Y here to add support for outputting video over HDMI.
395
Hans de Goeded9786d22014-12-25 13:58:06 +0100396config VIDEO_VGA
397 boolean "VGA output support"
398 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
399 default n
400 ---help---
401 Say Y here to add support for outputting video over VGA.
402
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100403config VIDEO_VGA_VIA_LCD
404 boolean "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800405 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100406 default n
407 ---help---
408 Say Y here to add support for external DACs connected to the parallel
409 LCD interface driving a VGA connector, such as found on the
410 Olimex A13 boards.
411
Hans de Goedefb75d972015-01-25 15:33:07 +0100412config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
413 boolean "Force sync active high for VGA via LCD controller support"
414 depends on VIDEO_VGA_VIA_LCD
415 default n
416 ---help---
417 Say Y here if you've a board which uses opendrain drivers for the vga
418 hsync and vsync signals. Opendrain drivers cannot generate steep enough
419 positive edges for a stable video output, so on boards with opendrain
420 drivers the sync signals must always be active high.
421
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800422config VIDEO_VGA_EXTERNAL_DAC_EN
423 string "LCD panel power enable pin"
424 depends on VIDEO_VGA_VIA_LCD
425 default ""
426 ---help---
427 Set the enable pin for the external VGA DAC. This takes a string in the
428 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
429
Hans de Goede39920c82015-08-03 19:20:26 +0200430config VIDEO_COMPOSITE
431 boolean "Composite video output support"
432 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
433 default n
434 ---help---
435 Say Y here to add support for outputting composite video.
436
Hans de Goede2dae8002014-12-21 16:28:32 +0100437config VIDEO_LCD_MODE
438 string "LCD panel timing details"
439 depends on VIDEO
440 default ""
441 ---help---
442 LCD panel timing details string, leave empty if there is no LCD panel.
443 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
444 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200445 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100446
Hans de Goede65150322015-01-13 13:21:46 +0100447config VIDEO_LCD_DCLK_PHASE
448 int "LCD panel display clock phase"
449 depends on VIDEO
450 default 1
451 ---help---
452 Select LCD panel display clock phase shift, range 0-3.
453
Hans de Goede2dae8002014-12-21 16:28:32 +0100454config VIDEO_LCD_POWER
455 string "LCD panel power enable pin"
456 depends on VIDEO
457 default ""
458 ---help---
459 Set the power enable pin for the LCD panel. This takes a string in the
460 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
461
Hans de Goede242e3d82015-02-16 17:26:41 +0100462config VIDEO_LCD_RESET
463 string "LCD panel reset pin"
464 depends on VIDEO
465 default ""
466 ---help---
467 Set the reset pin for the LCD panel. This takes a string in the format
468 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
469
Hans de Goede2dae8002014-12-21 16:28:32 +0100470config VIDEO_LCD_BL_EN
471 string "LCD panel backlight enable pin"
472 depends on VIDEO
473 default ""
474 ---help---
475 Set the backlight enable pin for the LCD panel. This takes a string in the
476 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
477 port H.
478
479config VIDEO_LCD_BL_PWM
480 string "LCD panel backlight pwm pin"
481 depends on VIDEO
482 default ""
483 ---help---
484 Set the backlight pwm pin for the LCD panel. This takes a string in the
485 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200486
Hans de Goedea7403ae2015-01-22 21:02:42 +0100487config VIDEO_LCD_BL_PWM_ACTIVE_LOW
488 bool "LCD panel backlight pwm is inverted"
489 depends on VIDEO
490 default y
491 ---help---
492 Set this if the backlight pwm output is active low.
493
Hans de Goede55410082015-02-16 17:23:25 +0100494config VIDEO_LCD_PANEL_I2C
495 bool "LCD panel needs to be configured via i2c"
496 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100497 default n
Hans de Goede55410082015-02-16 17:23:25 +0100498 ---help---
499 Say y here if the LCD panel needs to be configured via i2c. This
500 will add a bitbang i2c controller using gpios to talk to the LCD.
501
502config VIDEO_LCD_PANEL_I2C_SDA
503 string "LCD panel i2c interface SDA pin"
504 depends on VIDEO_LCD_PANEL_I2C
505 default "PG12"
506 ---help---
507 Set the SDA pin for the LCD i2c interface. This takes a string in the
508 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
509
510config VIDEO_LCD_PANEL_I2C_SCL
511 string "LCD panel i2c interface SCL pin"
512 depends on VIDEO_LCD_PANEL_I2C
513 default "PG10"
514 ---help---
515 Set the SCL pin for the LCD i2c interface. This takes a string in the
516 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
517
Hans de Goede213480e2015-01-01 22:04:34 +0100518
519# Note only one of these may be selected at a time! But hidden choices are
520# not supported by Kconfig
521config VIDEO_LCD_IF_PARALLEL
522 bool
523
524config VIDEO_LCD_IF_LVDS
525 bool
526
527
528choice
529 prompt "LCD panel support"
530 depends on VIDEO
531 ---help---
532 Select which type of LCD panel to support.
533
534config VIDEO_LCD_PANEL_PARALLEL
535 bool "Generic parallel interface LCD panel"
536 select VIDEO_LCD_IF_PARALLEL
537
538config VIDEO_LCD_PANEL_LVDS
539 bool "Generic lvds interface LCD panel"
540 select VIDEO_LCD_IF_LVDS
541
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200542config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
543 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
544 select VIDEO_LCD_SSD2828
545 select VIDEO_LCD_IF_PARALLEL
546 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200547 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
548
549config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
550 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
551 select VIDEO_LCD_ANX9804
552 select VIDEO_LCD_IF_PARALLEL
553 select VIDEO_LCD_PANEL_I2C
554 ---help---
555 Select this for eDP LCD panels with 4 lanes running at 1.62G,
556 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200557
Hans de Goede27515b22015-01-20 09:23:36 +0100558config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
559 bool "Hitachi tx18d42vm LCD panel"
560 select VIDEO_LCD_HITACHI_TX18D42VM
561 select VIDEO_LCD_IF_LVDS
562 ---help---
563 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
564
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100565config VIDEO_LCD_TL059WV5C0
566 bool "tl059wv5c0 LCD panel"
567 select VIDEO_LCD_PANEL_I2C
568 select VIDEO_LCD_IF_PARALLEL
569 ---help---
570 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
571 Aigo M60/M608/M606 tablets.
572
Hans de Goede213480e2015-01-01 22:04:34 +0100573endchoice
574
575
Hans de Goedec13f60d2015-01-25 12:10:48 +0100576config GMAC_TX_DELAY
577 int "GMAC Transmit Clock Delay Chain"
578 default 0
579 ---help---
580 Set the GMAC Transmit Clock Delay Chain value.
581
Hans de Goedeff42d102015-09-13 13:02:48 +0200582config SPL_STACK_R_ADDR
583 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
584 default 0x2fe00000 if MACH_SUN9I
585
Masahiro Yamadadd840582014-07-30 14:08:14 +0900586endif