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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk71f95112003-06-15 22:40:42 +00002/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00003 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05004 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00007 */
8
9#ifndef _MMC_H_
10#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000011
Simon Glasscd93d622020-05-10 11:40:13 -060012#include <linux/bitops.h>
Andy Fleming272cc702008-10-30 16:41:01 -050013#include <linux/list.h>
Peng Fan3697e592016-09-01 11:13:38 +080014#include <linux/sizes.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000015#include <linux/compiler.h>
Masahiro Yamadaa7b2b6c2020-02-14 16:40:25 +090016#include <linux/dma-direction.h>
Mateusz Zalega07a2d422014-04-30 13:04:15 +020017#include <part.h>
Andy Fleming272cc702008-10-30 16:41:01 -050018
Masahiro Yamadabd602c52020-02-25 02:25:30 +090019struct bd_info;
20
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010021#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
22#define MMC_SUPPORTS_TUNING
23#endif
24#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
25#define MMC_SUPPORTS_TUNING
26#endif
27
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020028/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
29#define SD_VERSION_SD (1U << 31)
30#define MMC_VERSION_MMC (1U << 30)
31
32#define MAKE_SDMMC_VERSION(a, b, c) \
33 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
34#define MAKE_SD_VERSION(a, b, c) \
35 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
36#define MAKE_MMC_VERSION(a, b, c) \
37 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
38
39#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
40 (((u32)(x) >> 16) & 0xff)
41#define EXTRACT_SDMMC_MINOR_VERSION(x) \
42 (((u32)(x) >> 8) & 0xff)
43#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
44 ((u32)(x) & 0xff)
45
46#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
47#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
48#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
49#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
50
51#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
52#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
53#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
54#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
55#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
56#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
57#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
58#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
59#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
Jean-Jacques Hiblotace1bed2018-02-09 12:09:28 +010060#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020061#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
62#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
63#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
Stefan Wahren1a3619c2016-06-16 17:54:06 +000064#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
Andy Fleming272cc702008-10-30 16:41:01 -050065
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020066#define MMC_CAP(mode) (1 << mode)
67#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
68#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
69#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +020070#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
Peng Fan3dd26262018-08-10 14:07:54 +080071#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
Peng Fan44acd492019-07-10 14:43:07 +080072#define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020073
T Karthik Reddy86a94e72019-06-25 13:39:02 +020074#define MMC_CAP_NONREMOVABLE BIT(14)
75#define MMC_CAP_NEEDS_POLL BIT(15)
76#define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
77
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020078#define MMC_MODE_8BIT BIT(30)
79#define MMC_MODE_4BIT BIT(29)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +020080#define MMC_MODE_1BIT BIT(28)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020081#define MMC_MODE_SPI BIT(27)
82
Ɓukasz Majewski62722032012-03-12 22:07:18 +000083
Andy Fleming272cc702008-10-30 16:41:01 -050084#define SD_DATA_4BIT 0x00040000
85
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020086#define IS_SD(x) ((x)->version & SD_VERSION_SD)
Andrew Gabbasov3f2da752015-03-19 07:44:02 -050087#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
Andy Fleming272cc702008-10-30 16:41:01 -050088
89#define MMC_DATA_READ 1
90#define MMC_DATA_WRITE 2
91
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020092#define MMC_CMD_GO_IDLE_STATE 0
93#define MMC_CMD_SEND_OP_COND 1
94#define MMC_CMD_ALL_SEND_CID 2
95#define MMC_CMD_SET_RELATIVE_ADDR 3
96#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050097#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020098#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050099#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200100#define MMC_CMD_SEND_CSD 9
101#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -0500102#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200103#define MMC_CMD_SEND_STATUS 13
104#define MMC_CMD_SET_BLOCKLEN 16
105#define MMC_CMD_READ_SINGLE_BLOCK 17
106#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200107#define MMC_CMD_SEND_TUNING_BLOCK 19
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200108#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200109#define MMC_CMD_SET_BLOCK_COUNT 23
Andy Fleming272cc702008-10-30 16:41:01 -0500110#define MMC_CMD_WRITE_SINGLE_BLOCK 24
111#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +0000112#define MMC_CMD_ERASE_GROUP_START 35
113#define MMC_CMD_ERASE_GROUP_END 36
114#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200115#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +0000116#define MMC_CMD_SPI_READ_OCR 58
117#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar3690d6d2013-04-27 11:42:58 +0530118#define MMC_CMD_RES_MAN 62
119
120#define MMC_CMD62_ARG1 0xefac62ec
121#define MMC_CMD62_ARG2 0xcbaea7
122
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200123
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200124#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -0500125#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200126#define SD_CMD_SEND_IF_COND 8
Otavio Salvadorf022d362015-02-17 10:42:43 -0200127#define SD_CMD_SWITCH_UHS18V 11
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200128
129#define SD_CMD_APP_SET_BUS_WIDTH 6
Peng Fan3697e592016-09-01 11:13:38 +0800130#define SD_CMD_APP_SD_STATUS 13
Lei Wene6f99a52011-06-22 17:03:31 +0000131#define SD_CMD_ERASE_WR_BLK_START 32
132#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200133#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -0500134#define SD_CMD_APP_SEND_SCR 51
135
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200136static inline bool mmc_is_tuning_cmd(uint cmdidx)
137{
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200138 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
139 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200140 return true;
141 return false;
142}
143
Andy Fleming272cc702008-10-30 16:41:01 -0500144/* SCR definitions in different words */
145#define SD_HIGHSPEED_BUSY 0x00020000
146#define SD_HIGHSPEED_SUPPORTED 0x00020000
147
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200148#define UHS_SDR12_BUS_SPEED 0
149#define HIGH_SPEED_BUS_SPEED 1
150#define UHS_SDR25_BUS_SPEED 1
151#define UHS_SDR50_BUS_SPEED 2
152#define UHS_SDR104_BUS_SPEED 3
153#define UHS_DDR50_BUS_SPEED 4
154
155#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
156#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
157#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
158#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
159#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
160
Thomas Chouabe2c932011-04-19 03:48:31 +0000161#define OCR_BUSY 0x80000000
162#define OCR_HCS 0x40000000
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200163#define OCR_S18R 0x1000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000164#define OCR_VOLTAGE_MASK 0x007FFF80
165#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500166
Eric Nelson1aa2d072015-12-07 07:50:01 -0700167#define MMC_ERASE_ARG 0x00000000
168#define MMC_SECURE_ERASE_ARG 0x80000000
169#define MMC_TRIM_ARG 0x00000001
170#define MMC_DISCARD_ARG 0x00000003
171#define MMC_SECURE_TRIM1_ARG 0x80000001
172#define MMC_SECURE_TRIM2_ARG 0x80008000
Lei Wene6f99a52011-06-22 17:03:31 +0000173
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000174#define MMC_STATUS_MASK (~0x0206BF7F)
Andrew Gabbasov6b2221b2014-04-03 04:34:32 -0500175#define MMC_STATUS_SWITCH_ERROR (1 << 7)
Thomas Chouabe2c932011-04-19 03:48:31 +0000176#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
177#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000178#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000179
Jan Kloetzked617c422012-02-05 22:29:12 +0000180#define MMC_STATE_PRG (7 << 9)
181
Andy Fleming272cc702008-10-30 16:41:01 -0500182#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
183#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
184#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
185#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
186#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
187#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
188#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
189#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
190#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
191#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
192#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
193#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
194#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
195#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
196#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
197#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
198#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
199
200#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
201#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
202 addressed by index which are
203 1 in value field */
204#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
205 addressed by index, which are
206 1 in value field */
207#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
208
209#define SD_SWITCH_CHECK 0
210#define SD_SWITCH_SWITCH 1
211
212/*
213 * EXT_CSD fields
214 */
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100215#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
216#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600217#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Markus Niebeld7b29122014-11-18 15:11:42 +0100218#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
Oliver Metz1937e5a2013-10-01 20:32:07 +0200219#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100220#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
Lei Wen0560db12011-10-03 20:35:10 +0000221#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Tom Rini33ace362014-02-07 14:15:20 -0500222#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Tomas Melincd3d4882016-11-25 11:01:03 +0200223#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100224#define EXT_CSD_WR_REL_PARAM 166 /* R */
225#define EXT_CSD_WR_REL_SET 167 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600226#define EXT_CSD_RPMB_MULT 168 /* RO */
Heinrich Schuchardt9abfe332020-03-30 07:24:16 +0200227#define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */
228#define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
229#define EXT_CSD_BOOT_WP_STATUS 174 /* R */
Lei Wen0560db12011-10-03 20:35:10 +0000230#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar3690d6d2013-04-27 11:42:58 +0530231#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen0560db12011-10-03 20:35:10 +0000232#define EXT_CSD_PART_CONF 179 /* R/W */
233#define EXT_CSD_BUS_WIDTH 183 /* R/W */
Peng Fan44acd492019-07-10 14:43:07 +0800234#define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
Lei Wen0560db12011-10-03 20:35:10 +0000235#define EXT_CSD_HS_TIMING 185 /* R/W */
236#define EXT_CSD_REV 192 /* RO */
237#define EXT_CSD_CARD_TYPE 196 /* RO */
Jean-Jacques Hiblot513e00b2019-07-02 10:53:55 +0200238#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000239#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrenf866a462013-06-11 15:14:01 -0600240#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000241#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000242#define EXT_CSD_BOOT_MULT 226 /* RO */
Jean-Jacques Hiblot39320c52019-07-02 10:53:54 +0200243#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
Tomas Melincd3d4882016-11-25 11:01:03 +0200244#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500245
246/*
247 * EXT_CSD field definitions
248 */
249
Thomas Chouabe2c932011-04-19 03:48:31 +0000250#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
251#define EXT_CSD_CMD_SET_SECURE (1 << 1)
252#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500253
Thomas Chouabe2c932011-04-19 03:48:31 +0000254#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
255#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900256#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
257#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
258#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
259 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Andy Fleming272cc702008-10-30 16:41:01 -0500260
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200261#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
262 /* SDR mode @1.8V I/O */
263#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
264 /* SDR mode @1.2V I/O */
265#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
266 EXT_CSD_CARD_TYPE_HS200_1_2V)
Peng Fan3dd26262018-08-10 14:07:54 +0800267#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
268#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
269#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
270 EXT_CSD_CARD_TYPE_HS400_1_2V)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200271
Andy Fleming272cc702008-10-30 16:41:01 -0500272#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
273#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
274#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900275#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
276#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200277#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
Peng Fan44acd492019-07-10 14:43:07 +0800278#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200279
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200280#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
281#define EXT_CSD_TIMING_HS 1 /* HS */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200282#define EXT_CSD_TIMING_HS200 2 /* HS200 */
Peng Fan3dd26262018-08-10 14:07:54 +0800283#define EXT_CSD_TIMING_HS400 3 /* HS400 */
Peng Fan44acd492019-07-10 14:43:07 +0800284#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200285
Amar3690d6d2013-04-27 11:42:58 +0530286#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
287#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
288#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
289#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
290
291#define EXT_CSD_BOOT_ACK(x) (x << 6)
292#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
293#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
294
Angelo Dureghellobdb60992017-08-01 14:27:10 +0200295#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
296#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
297#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
298
Tom Rini5a99b9d2014-02-05 10:24:22 -0500299#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
300#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
301#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar3690d6d2013-04-27 11:42:58 +0530302
Markus Niebeld7b29122014-11-18 15:11:42 +0100303#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
304
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100305#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
306#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
307
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100308#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
309
310#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
311#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
312
Andy Fleming1de97f92008-10-30 16:31:39 -0500313#define R1_ILLEGAL_COMMAND (1 << 22)
314#define R1_APP_CMD (1 << 5)
315
Andy Fleming272cc702008-10-30 16:41:01 -0500316#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000317#define MMC_RSP_136 (1 << 1) /* 136 bit response */
318#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
319#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
320#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500321
Thomas Chouabe2c932011-04-19 03:48:31 +0000322#define MMC_RSP_NONE (0)
323#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500324#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
325 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000326#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
327#define MMC_RSP_R3 (MMC_RSP_PRESENT)
328#define MMC_RSP_R4 (MMC_RSP_PRESENT)
329#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
330#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
331#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500332
Lei Wenbc897b12011-05-02 16:26:26 +0000333#define MMCPART_NOAVAILABLE (0xff)
334#define PART_ACCESS_MASK (0x7)
335#define PART_SUPPORT (0x1)
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100336#define ENHNCD_SUPPORT (0x2)
Oliver Metz1937e5a2013-10-01 20:32:07 +0200337#define PART_ENH_ATTRIB (0x1f)
wdenk71f95112003-06-15 22:40:42 +0000338
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200339#define MMC_QUIRK_RETRY_SEND_CID BIT(0)
340#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
Joel Johnsond4a5fa32020-01-11 09:08:14 -0700341#define MMC_QUIRK_RETRY_APP_CMD BIT(2)
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200342
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200343enum mmc_voltage {
344 MMC_SIGNAL_VOLTAGE_000 = 0,
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200345 MMC_SIGNAL_VOLTAGE_120 = 1,
346 MMC_SIGNAL_VOLTAGE_180 = 2,
347 MMC_SIGNAL_VOLTAGE_330 = 4,
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200348};
349
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200350#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
351 MMC_SIGNAL_VOLTAGE_180 |\
352 MMC_SIGNAL_VOLTAGE_330)
353
Simon Glass8bfa1952013-04-03 08:54:30 +0000354/* Maximum block size for MMC */
355#define MMC_MAX_BLOCK_LEN 512
356
Amar3690d6d2013-04-27 11:42:58 +0530357/* The number of MMC physical partitions. These consist of:
358 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
359 */
360#define MMC_NUM_BOOT_PARTITION 2
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200361#define MMC_PART_RPMB 3 /* RPMB partition number */
Amar3690d6d2013-04-27 11:42:58 +0530362
Simon Glasse7ecf7c2015-06-23 15:38:48 -0600363/* Driver model support */
364
365/**
366 * struct mmc_uclass_priv - Holds information about a device used by the uclass
367 */
368struct mmc_uclass_priv {
369 struct mmc *mmc;
370};
371
372/**
373 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
374 *
375 * Provided that the device is already probed and ready for use, this value
376 * will be available.
377 *
378 * @dev: Device
379 * @return associated mmc struct pointer if available, else NULL
380 */
Simon Glass3a905cd2020-04-08 08:33:00 -0600381struct mmc *mmc_get_mmc_dev(const struct udevice *dev);
Simon Glasse7ecf7c2015-06-23 15:38:48 -0600382
383/* End of driver model support */
384
Andy Fleming1de97f92008-10-30 16:31:39 -0500385struct mmc_cid {
386 unsigned long psn;
387 unsigned short oid;
388 unsigned char mid;
389 unsigned char prv;
390 unsigned char mdt;
391 char pnm[7];
392};
393
Andy Fleming272cc702008-10-30 16:41:01 -0500394struct mmc_cmd {
395 ushort cmdidx;
396 uint resp_type;
397 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530398 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500399};
400
401struct mmc_data {
402 union {
403 char *dest;
404 const char *src; /* src buffers don't get written to */
405 };
406 uint flags;
407 uint blocks;
408 uint blocksize;
409};
410
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200411/* forward decl. */
412struct mmc;
413
Simon Glasse7881d82017-07-29 11:35:31 -0600414#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass8ca51e52016-06-12 23:30:22 -0600415struct dm_mmc_ops {
416 /**
Faiz Abbas32860bd2020-02-26 13:44:30 +0530417 * deferred_probe() - Some configurations that need to be deferred
418 * to just before enumerating the device
419 *
420 * @dev: Device to init
421 * @return 0 if Ok, -ve if error
422 */
423 int (*deferred_probe)(struct udevice *dev);
424 /**
Simon Glass8ca51e52016-06-12 23:30:22 -0600425 * send_cmd() - Send a command to the MMC device
426 *
427 * @dev: Device to receive the command
428 * @cmd: Command to send
429 * @data: Additional data to send/receive
430 * @return 0 if OK, -ve on error
431 */
432 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
433 struct mmc_data *data);
434
435 /**
436 * set_ios() - Set the I/O speed/width for an MMC device
437 *
438 * @dev: Device to update
439 * @return 0 if OK, -ve on error
440 */
441 int (*set_ios)(struct udevice *dev);
442
443 /**
444 * get_cd() - See whether a card is present
445 *
446 * @dev: Device to check
447 * @return 0 if not present, 1 if present, -ve on error
448 */
449 int (*get_cd)(struct udevice *dev);
450
451 /**
452 * get_wp() - See whether a card has write-protect enabled
453 *
454 * @dev: Device to check
455 * @return 0 if write-enabled, 1 if write-protected, -ve on error
456 */
457 int (*get_wp)(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200458
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100459#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200460 /**
461 * execute_tuning() - Start the tuning process
462 *
463 * @dev: Device to start the tuning
464 * @opcode: Command opcode to send
465 * @return 0 if OK, -ve on error
466 */
467 int (*execute_tuning)(struct udevice *dev, uint opcode);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100468#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200469
470 /**
471 * wait_dat0() - wait until dat0 is in the target state
472 * (CLK must be running during the wait)
473 *
474 * @dev: Device to check
475 * @state: target state
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300476 * @timeout_us: timeout in us
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200477 * @return 0 if dat0 is in the target state, -ve on error
478 */
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300479 int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
Peng Fan44acd492019-07-10 14:43:07 +0800480
481#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
482 /* set_enhanced_strobe() - set HS400 enhanced strobe */
483 int (*set_enhanced_strobe)(struct udevice *dev);
484#endif
Yann Gautier3602a562019-09-19 17:56:12 +0200485
486 /**
487 * host_power_cycle - host specific tasks in power cycle sequence
488 * Called between mmc_power_off() and
489 * mmc_power_on()
490 *
491 * @dev: Device to check
492 * @return 0 if not present, 1 if present, -ve on error
493 */
494 int (*host_power_cycle)(struct udevice *dev);
Marek Vasut145429a2020-04-04 12:45:05 +0200495
496 /**
497 * get_b_max - get maximum length of single transfer
498 * Called before reading blocks from the card,
499 * useful for system which have e.g. DMA limits
500 * on various memory ranges.
501 *
502 * @dev: Device to check
503 * @dst: Destination buffer in memory
504 * @blkcnt: Total number of blocks in this transfer
505 * @return maximum number of blocks for this transfer
506 */
507 int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
Simon Glass8ca51e52016-06-12 23:30:22 -0600508};
509
510#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
511
512int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
513 struct mmc_data *data);
514int dm_mmc_set_ios(struct udevice *dev);
515int dm_mmc_get_cd(struct udevice *dev);
516int dm_mmc_get_wp(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200517int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300518int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
Yann Gautier3602a562019-09-19 17:56:12 +0200519int dm_mmc_host_power_cycle(struct udevice *dev);
Faiz Abbas32860bd2020-02-26 13:44:30 +0530520int dm_mmc_deferred_probe(struct udevice *dev);
Marek Vasut145429a2020-04-04 12:45:05 +0200521int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
Simon Glass8ca51e52016-06-12 23:30:22 -0600522
523/* Transition functions for compatibility */
524int mmc_set_ios(struct mmc *mmc);
525int mmc_getcd(struct mmc *mmc);
526int mmc_getwp(struct mmc *mmc);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200527int mmc_execute_tuning(struct mmc *mmc, uint opcode);
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300528int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
Peng Fan44acd492019-07-10 14:43:07 +0800529int mmc_set_enhanced_strobe(struct mmc *mmc);
Yann Gautier3602a562019-09-19 17:56:12 +0200530int mmc_host_power_cycle(struct mmc *mmc);
Faiz Abbas32860bd2020-02-26 13:44:30 +0530531int mmc_deferred_probe(struct mmc *mmc);
Marek Vasut145429a2020-04-04 12:45:05 +0200532int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
Simon Glass8ca51e52016-06-12 23:30:22 -0600533
534#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200535struct mmc_ops {
536 int (*send_cmd)(struct mmc *mmc,
537 struct mmc_cmd *cmd, struct mmc_data *data);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900538 int (*set_ios)(struct mmc *mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200539 int (*init)(struct mmc *mmc);
540 int (*getcd)(struct mmc *mmc);
541 int (*getwp)(struct mmc *mmc);
Yann Gautier3602a562019-09-19 17:56:12 +0200542 int (*host_power_cycle)(struct mmc *mmc);
Marek Vasut145429a2020-04-04 12:45:05 +0200543 int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200544};
Simon Glass8ca51e52016-06-12 23:30:22 -0600545#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200546
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200547struct mmc_config {
548 const char *name;
Simon Glasse7881d82017-07-29 11:35:31 -0600549#if !CONFIG_IS_ENABLED(DM_MMC)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200550 const struct mmc_ops *ops;
Simon Glass8ca51e52016-06-12 23:30:22 -0600551#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200552 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500553 uint voltages;
Andy Fleming272cc702008-10-30 16:41:01 -0500554 uint f_min;
555 uint f_max;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200556 uint b_max;
557 unsigned char part_type;
558};
559
Peng Fan3697e592016-09-01 11:13:38 +0800560struct sd_ssr {
561 unsigned int au; /* In sectors */
562 unsigned int erase_timeout; /* In milliseconds */
563 unsigned int erase_offset; /* In milliseconds */
564};
565
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200566enum bus_mode {
567 MMC_LEGACY,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200568 MMC_HS,
569 SD_HS,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100570 MMC_HS_52,
571 MMC_DDR_52,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200572 UHS_SDR12,
573 UHS_SDR25,
574 UHS_SDR50,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200575 UHS_DDR50,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100576 UHS_SDR104,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200577 MMC_HS_200,
Peng Fan3dd26262018-08-10 14:07:54 +0800578 MMC_HS_400,
Peng Fan44acd492019-07-10 14:43:07 +0800579 MMC_HS_400_ES,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200580 MMC_MODES_END
581};
582
583const char *mmc_mode_name(enum bus_mode mode);
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +0200584void mmc_dump_capabilities(const char *text, uint caps);
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200585
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200586static inline bool mmc_is_mode_ddr(enum bus_mode mode)
587{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100588 if (mode == MMC_DDR_52)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200589 return true;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100590#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
591 else if (mode == UHS_DDR50)
592 return true;
593#endif
Peng Fan3dd26262018-08-10 14:07:54 +0800594#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
595 else if (mode == MMC_HS_400)
596 return true;
597#endif
Peng Fan44acd492019-07-10 14:43:07 +0800598#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
599 else if (mode == MMC_HS_400_ES)
600 return true;
601#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200602 else
603 return false;
604}
605
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200606#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
607 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
608 MMC_CAP(UHS_DDR50))
609
610static inline bool supports_uhs(uint caps)
611{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100612#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200613 return (caps & UHS_CAPS) ? true : false;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100614#else
615 return false;
616#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200617}
618
Simon Glass8ca51e52016-06-12 23:30:22 -0600619/*
620 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
621 * with mmc_get_mmc_dev().
622 *
623 * TODO struct mmc should be in mmc_private but it's hard to fix right now
624 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200625struct mmc {
Simon Glassc4d660d2017-07-04 13:31:19 -0600626#if !CONFIG_IS_ENABLED(BLK)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200627 struct list_head link;
Simon Glass33fb2112016-05-01 13:52:41 -0600628#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200629 const struct mmc_config *cfg; /* provided configuration */
630 uint version;
631 void *priv;
632 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500633 int high_capacity;
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200634 bool clk_disable; /* true if the clock can be turned off */
Andy Fleming272cc702008-10-30 16:41:01 -0500635 uint bus_width;
636 uint clock;
Faiz Abbas0d3c8582020-02-26 13:44:29 +0530637 uint saved_clock;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200638 enum mmc_voltage signal_voltage;
Andy Fleming272cc702008-10-30 16:41:01 -0500639 uint card_caps;
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +0200640 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500641 uint ocr;
Markus Niebelab711882013-12-16 13:40:46 +0100642 uint dsr;
643 uint dsr_imp;
Andy Fleming272cc702008-10-30 16:41:01 -0500644 uint scr[2];
645 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530646 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500647 ushort rca;
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100648 u8 part_support;
649 u8 part_attr;
Diego Santa Cruz9e41a002014-12-23 10:50:33 +0100650 u8 wr_rel_set;
Tom Rini7ca0d3d2017-05-10 15:20:16 -0400651 u8 part_config;
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300652 u8 gen_cmd6_time; /* units: 10 ms */
653 u8 part_switch_time; /* units: 10 ms */
Andy Fleming272cc702008-10-30 16:41:01 -0500654 uint tran_speed;
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200655 uint legacy_speed; /* speed for the legacy mode provided by the card */
Andy Fleming272cc702008-10-30 16:41:01 -0500656 uint read_bl_len;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100657#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Fleming272cc702008-10-30 16:41:01 -0500658 uint write_bl_len;
Diego Santa Cruza4ff9f82014-12-23 10:50:24 +0100659 uint erase_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100660#endif
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100661#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruz037dc0a2014-12-23 10:50:25 +0100662 uint hc_wp_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100663#endif
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100664#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fan3697e592016-09-01 11:13:38 +0800665 struct sd_ssr ssr; /* SD status register */
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100666#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500667 u64 capacity;
Stephen Warrenf866a462013-06-11 15:14:01 -0600668 u64 capacity_user;
669 u64 capacity_boot;
670 u64 capacity_rpmb;
671 u64 capacity_gp[4];
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100672#ifndef CONFIG_SPL_BUILD
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100673 u64 enh_user_start;
674 u64 enh_user_size;
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100675#endif
Simon Glassc4d660d2017-07-04 13:31:19 -0600676#if !CONFIG_IS_ENABLED(BLK)
Simon Glass4101f682016-02-29 15:25:34 -0700677 struct blk_desc block_dev;
Simon Glass33fb2112016-05-01 13:52:41 -0600678#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +0000679 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
680 char init_in_progress; /* 1 if we have done mmc_start_init() */
681 char preinit; /* start init as early as possible */
Andrew Gabbasov786e8f82014-12-01 06:59:09 -0600682 int ddr_mode;
Simon Glassc4d660d2017-07-04 13:31:19 -0600683#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glasscffe5d82016-05-01 13:52:34 -0600684 struct udevice *dev; /* Device for this MMC controller */
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +0200685#if CONFIG_IS_ENABLED(DM_REGULATOR)
686 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
687 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
688#endif
Simon Glasscffe5d82016-05-01 13:52:34 -0600689#endif
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +0200690 u8 *ext_csd;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200691 u32 cardtype; /* cardtype read from the MMC */
692 enum mmc_voltage current_voltage;
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200693 enum bus_mode selected_mode; /* mode currently used */
694 enum bus_mode best_mode; /* best mode is the supported mode with the
695 * highest bandwidth. It may not always be the
696 * operating mode due to limitations when
697 * accessing the boot partitions
698 */
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200699 u32 quirks;
Andy Fleming272cc702008-10-30 16:41:01 -0500700};
701
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100702struct mmc_hwpart_conf {
703 struct {
704 uint enh_start; /* in 512-byte sectors */
705 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100706 unsigned wr_rel_change : 1;
707 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100708 } user;
709 struct {
710 uint size; /* in 512-byte sectors */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100711 unsigned enhanced : 1;
712 unsigned wr_rel_change : 1;
713 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100714 } gp_part[4];
715};
716
717enum mmc_hwpart_conf_mode {
718 MMC_HWPART_CONF_CHECK,
719 MMC_HWPART_CONF_SET,
720 MMC_HWPART_CONF_COMPLETE,
721};
722
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200723struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
Simon Glassad27dd52016-05-01 13:52:40 -0600724
725/**
726 * mmc_bind() - Set up a new MMC device ready for probing
727 *
728 * A child block device is bound with the IF_TYPE_MMC interface type. This
729 * allows the device to be used with CONFIG_BLK
730 *
731 * @dev: MMC device to set up
732 * @mmc: MMC struct
733 * @cfg: MMC configuration
734 * @return 0 if OK, -ve on error
735 */
736int mmc_bind(struct udevice *dev, struct mmc *mmc,
737 const struct mmc_config *cfg);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200738void mmc_destroy(struct mmc *mmc);
Simon Glassad27dd52016-05-01 13:52:40 -0600739
740/**
741 * mmc_unbind() - Unbind a MMC device's child block device
742 *
743 * @dev: MMC device
744 * @return 0 if OK, -ve on error
745 */
746int mmc_unbind(struct udevice *dev);
Masahiro Yamadabd602c52020-02-25 02:25:30 +0900747int mmc_initialize(struct bd_info *bis);
Lokesh Vutla80f02012019-09-09 14:40:36 +0530748int mmc_init_device(int num);
Andy Fleming272cc702008-10-30 16:41:01 -0500749int mmc_init(struct mmc *mmc);
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200750int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100751
Marek Vasutfceea992019-01-29 04:45:51 +0100752#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
753 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
754 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
755int mmc_deinit(struct mmc *mmc);
756#endif
757
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100758/**
759 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
760 *
761 * @dev: MMC device
762 * @cfg: MMC configuration
763 * @return 0 if OK, -ve on error
764 */
765int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
766
Andy Fleming272cc702008-10-30 16:41:01 -0500767int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200768
769/**
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200770 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
771 *
772 * @voltage: The mmc_voltage to convert
773 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
774 */
775int mmc_voltage_to_mv(enum mmc_voltage voltage);
776
777/**
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200778 * mmc_set_clock() - change the bus clock
779 * @mmc: MMC struct
780 * @clock: bus frequency in Hz
781 * @disable: flag indicating if the clock must on or off
782 * @return 0 if OK, -ve on error
783 */
784int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
785
Jaehoon Chung65117182018-01-26 19:25:29 +0900786#define MMC_CLK_ENABLE false
787#define MMC_CLK_DISABLE true
788
Andy Fleming272cc702008-10-30 16:41:01 -0500789struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700790int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500791void print_mmc_devices(char separator);
Kever Yang46683f32016-07-22 17:22:50 +0800792
793/**
794 * get_mmc_num() - get the total MMC device number
795 *
796 * @return 0 if there is no MMC device, else the number of devices
797 */
Lei Wenea6ebe22011-05-02 16:26:25 +0000798int get_mmc_num(void);
Marek Vasutb5b838f2016-12-01 02:06:33 +0100799int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100800int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
801 enum mmc_hwpart_conf_mode mode);
Simon Glass8ca51e52016-06-12 23:30:22 -0600802
Simon Glasse7881d82017-07-29 11:35:31 -0600803#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Reding48972d92012-01-02 01:15:37 +0000804int mmc_getcd(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200805int board_mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000806int mmc_getwp(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200807int board_mmc_getwp(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600808#endif
809
Markus Niebelab711882013-12-16 13:40:46 +0100810int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar3690d6d2013-04-27 11:42:58 +0530811/* Function to change the size of boot partition and rpmb partitions */
812int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
813 unsigned long rpmbsize);
Tom Rini792970b2014-02-05 10:24:21 -0500814/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
815int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini5a99b9d2014-02-05 10:24:22 -0500816/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
817int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Tom Rini33ace362014-02-07 14:15:20 -0500818/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
819int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200820/* Functions to read / write the RPMB partition */
821int mmc_rpmb_set_key(struct mmc *mmc, void *key);
822int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
823int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
824 unsigned short cnt, unsigned char *key);
825int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
826 unsigned short cnt, unsigned char *key);
Jens Wiklander4853ad32018-09-25 16:40:08 +0200827
828/**
829 * mmc_rpmb_route_frames() - route RPMB data frames
830 * @mmc Pointer to a MMC device struct
831 * @req Request data frames
832 * @reqlen Length of data frames in bytes
833 * @rsp Supplied buffer for response data frames
834 * @rsplen Length of supplied buffer for response data frames
835 *
836 * The RPMB data frames are routed to/from some external entity, for
837 * example a Trusted Exectuion Environment in an arm TrustZone protected
838 * secure world. It's expected that it's the external entity who is in
839 * control of the RPMB key.
840 *
841 * Returns 0 on success, < 0 on error.
842 */
843int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
844 void *rsp, unsigned long rsplen);
845
Tomas Melincd3d4882016-11-25 11:01:03 +0200846#ifdef CONFIG_CMD_BKOPS_ENABLE
847int mmc_set_bkops_enable(struct mmc *mmc);
848#endif
849
Che-Liang Chioue9550442012-11-28 15:21:13 +0000850/**
851 * Start device initialization and return immediately; it does not block on
Jon Nettleton6c09eba2018-06-11 15:26:19 +0300852 * polling OCR (operation condition register) status. Useful for checking
853 * the presence of SD/eMMC when no card detect logic is available.
854 *
855 * @param mmc Pointer to a MMC device struct
856 * @return 0 on success, <0 on error.
857 */
858int mmc_get_op_cond(struct mmc *mmc);
859
860/**
861 * Start device initialization and return immediately; it does not block on
Che-Liang Chioue9550442012-11-28 15:21:13 +0000862 * polling OCR (operation condition register) status. Then you should call
863 * mmc_init, which would block on polling OCR status and complete the device
864 * initializatin.
865 *
866 * @param mmc Pointer to a MMC device struct
Baruch Siach31d95002018-06-11 15:26:18 +0300867 * @return 0 on success, <0 on error.
Che-Liang Chioue9550442012-11-28 15:21:13 +0000868 */
869int mmc_start_init(struct mmc *mmc);
870
871/**
872 * Set preinit flag of mmc device.
873 *
874 * This will cause the device to be pre-inited during mmc_initialize(),
875 * which may save boot time if the device is not accessed until later.
876 * Some eMMC devices take 200-300ms to init, but unfortunately they
877 * must be sent a series of commands to even get them to start preparing
878 * for operation.
879 *
880 * @param mmc Pointer to a MMC device struct
881 * @param preinit preinit flag value
882 */
883void mmc_set_preinit(struct mmc *mmc, int preinit);
884
Paul Burton8687d5c2013-09-04 16:12:26 +0100885#ifdef CONFIG_MMC_SPI
Tom Rini0b2da7e2014-03-28 16:55:29 -0400886#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
Paul Burton8687d5c2013-09-04 16:12:26 +0100887#else
888#define mmc_host_is_spi(mmc) 0
889#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200890
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +0100891void board_mmc_power_init(void);
Masahiro Yamadabd602c52020-02-25 02:25:30 +0900892int board_mmc_init(struct bd_info *bis);
893int cpu_mmc_init(struct bd_info *bis);
Jeroen Hofsteeaeb80552014-10-08 22:58:05 +0200894int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
Rajesh Bhagat43d17c42019-01-12 07:30:51 +0000895# ifdef CONFIG_SYS_MMC_ENV_PART
896extern uint mmc_get_env_part(struct mmc *mmc);
897# endif
Clemens Gruberaa844fe2016-01-26 16:20:38 +0100898int mmc_get_env_dev(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200899
Jean-Jacques Hiblot513e00b2019-07-02 10:53:55 +0200900/* Minimum partition switch timeout in units of 10-milliseconds */
901#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
902
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200903/* Set block count limit because of 16 bit register limit on some hardware*/
904#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
905#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
906#endif
907
Simon Glasscb5ec332016-05-01 13:52:27 -0600908/**
909 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
910 *
911 * @mmc: MMC device
912 * @return block device if found, else NULL
913 */
914struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
915
Heinrich Schuchardt1601ea22020-03-30 07:24:17 +0200916/**
917 * mmc_send_ext_csd() - read the extended CSD register
918 *
919 * @mmc: MMC device
920 * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
921 * the caller, e.g. using
922 * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
923 * Return: 0 for success
924 */
925int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
926
Heinrich Schuchardt0469d842020-03-30 07:24:19 +0200927/**
928 * mmc_boot_wp() - power on write protect boot partitions
929 *
930 * The boot partitions are write protected until the next power cycle.
931 *
932 * Return: 0 for success
933 */
934int mmc_boot_wp(struct mmc *mmc);
935
Masahiro Yamadaa7b2b6c2020-02-14 16:40:25 +0900936static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
937{
938 return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
939}
940
wdenk71f95112003-06-15 22:40:42 +0000941#endif /* _MMC_H_ */