blob: ad429f49c992849a4b011fb0316f1ad95d2e64ba [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming272cc702008-10-30 16:41:01 -05002/*
3 * Copyright 2008, Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based vaguely on the Linux code
Andy Fleming272cc702008-10-30 16:41:01 -05007 */
8
9#include <config.h>
10#include <common.h>
11#include <command.h>
Sjoerd Simons8e3332e2015-08-30 16:55:45 -060012#include <dm.h>
13#include <dm/device-internal.h>
Stephen Warrend4622df2014-05-23 12:47:06 -060014#include <errno.h>
Andy Fleming272cc702008-10-30 16:41:01 -050015#include <mmc.h>
16#include <part.h>
Peng Fan2051aef2016-10-11 15:08:43 +080017#include <power/regulator.h>
Andy Fleming272cc702008-10-30 16:41:01 -050018#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060019#include <memalign.h>
Andy Fleming272cc702008-10-30 16:41:01 -050020#include <linux/list.h>
Rabin Vincent9b1f9422009-04-05 13:30:54 +053021#include <div64.h>
Paul Burtonda61fa52013-09-09 15:30:26 +010022#include "mmc_private.h"
Andy Fleming272cc702008-10-30 16:41:01 -050023
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +020024static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +020025static int mmc_power_cycle(struct mmc *mmc);
Marek Vasut62d77ce2018-04-15 00:37:11 +020026#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +020027static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
Marek Vasutb5b838f2016-12-01 02:06:33 +010028#endif
29
Simon Glasse7881d82017-07-29 11:35:31 -060030#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020031
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010032#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020033static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
34{
35 return -ENOSYS;
36}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010037#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +020038
Jeroen Hofstee750121c2014-07-12 21:24:08 +020039__weak int board_mmc_getwp(struct mmc *mmc)
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +000040{
41 return -1;
42}
43
44int mmc_getwp(struct mmc *mmc)
45{
46 int wp;
47
48 wp = board_mmc_getwp(mmc);
49
Peter Korsgaardd4e1da42013-03-21 04:00:03 +000050 if (wp < 0) {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020051 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
Peter Korsgaardd4e1da42013-03-21 04:00:03 +000053 else
54 wp = 0;
55 }
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +000056
57 return wp;
58}
59
Jeroen Hofsteecee9ab72014-07-10 22:46:28 +020060__weak int board_mmc_getcd(struct mmc *mmc)
61{
Stefano Babic11fdade2010-02-05 15:04:43 +010062 return -1;
63}
Simon Glass8ca51e52016-06-12 23:30:22 -060064#endif
Stefano Babic11fdade2010-02-05 15:04:43 +010065
Marek Vasut8635ff92012-03-15 18:41:35 +000066#ifdef CONFIG_MMC_TRACE
Simon Glassc0c76eb2016-06-12 23:30:20 -060067void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
68{
69 printf("CMD_SEND:%d\n", cmd->cmdidx);
70 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
71}
72
73void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
74{
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +000075 int i;
76 u8 *ptr;
77
Bin Meng7863ce52016-03-17 21:53:14 -070078 if (ret) {
79 printf("\t\tRET\t\t\t %d\n", ret);
80 } else {
81 switch (cmd->resp_type) {
82 case MMC_RSP_NONE:
83 printf("\t\tMMC_RSP_NONE\n");
84 break;
85 case MMC_RSP_R1:
86 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
87 cmd->response[0]);
88 break;
89 case MMC_RSP_R1b:
90 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
91 cmd->response[0]);
92 break;
93 case MMC_RSP_R2:
94 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
95 cmd->response[0]);
96 printf("\t\t \t\t 0x%08X \n",
97 cmd->response[1]);
98 printf("\t\t \t\t 0x%08X \n",
99 cmd->response[2]);
100 printf("\t\t \t\t 0x%08X \n",
101 cmd->response[3]);
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +0000102 printf("\n");
Bin Meng7863ce52016-03-17 21:53:14 -0700103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
105 int j;
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
108 ptr += 3;
109 for (j = 0; j < 4; j++)
110 printf("%02X ", *ptr--);
111 printf("\n");
112 }
113 break;
114 case MMC_RSP_R3:
115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
116 cmd->response[0]);
117 break;
118 default:
119 printf("\t\tERROR MMC rsp not supported\n");
120 break;
Bin Meng53e8e402016-03-17 21:53:13 -0700121 }
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +0000122 }
Simon Glassc0c76eb2016-06-12 23:30:20 -0600123}
124
125void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
126{
127 int status;
128
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
131}
Raffaele Recalcati5db2fe32011-03-11 02:01:14 +0000132#endif
Simon Glassc0c76eb2016-06-12 23:30:20 -0600133
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200134#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135const char *mmc_mode_name(enum bus_mode mode)
136{
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
139 [SD_LEGACY] = "SD Legacy",
140 [MMC_HS] = "MMC High Speed (26MHz)",
141 [SD_HS] = "SD High Speed (50MHz)",
142 [UHS_SDR12] = "UHS SDR12 (25MHz)",
143 [UHS_SDR25] = "UHS SDR25 (50MHz)",
144 [UHS_SDR50] = "UHS SDR50 (100MHz)",
145 [UHS_SDR104] = "UHS SDR104 (208MHz)",
146 [UHS_DDR50] = "UHS DDR50 (50MHz)",
147 [MMC_HS_52] = "MMC High Speed (52MHz)",
148 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
149 [MMC_HS_200] = "HS200 (200MHz)",
150 };
151
152 if (mode >= MMC_MODES_END)
153 return "Unknown mode";
154 else
155 return names[mode];
156}
157#endif
158
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200159static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
160{
161 static const int freqs[] = {
Jaehoon Chung1b313aa2018-01-30 14:10:16 +0900162 [MMC_LEGACY] = 25000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200163 [SD_LEGACY] = 25000000,
164 [MMC_HS] = 26000000,
165 [SD_HS] = 50000000,
Jaehoon Chung1b313aa2018-01-30 14:10:16 +0900166 [MMC_HS_52] = 52000000,
167 [MMC_DDR_52] = 52000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200168 [UHS_SDR12] = 25000000,
169 [UHS_SDR25] = 50000000,
170 [UHS_SDR50] = 100000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200171 [UHS_DDR50] = 50000000,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100172 [UHS_SDR104] = 208000000,
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200173 [MMC_HS_200] = 200000000,
174 };
175
176 if (mode == MMC_LEGACY)
177 return mmc->legacy_speed;
178 else if (mode >= MMC_MODES_END)
179 return 0;
180 else
181 return freqs[mode];
182}
183
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200184static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
185{
186 mmc->selected_mode = mode;
Jean-Jacques Hiblot05038572017-09-21 16:29:55 +0200187 mmc->tran_speed = mmc_mode2freq(mmc, mode);
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200188 mmc->ddr_mode = mmc_is_mode_ddr(mode);
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900189 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
190 mmc->tran_speed / 1000000);
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200191 return 0;
192}
193
Simon Glasse7881d82017-07-29 11:35:31 -0600194#if !CONFIG_IS_ENABLED(DM_MMC)
Simon Glassc0c76eb2016-06-12 23:30:20 -0600195int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
196{
197 int ret;
198
199 mmmc_trace_before_send(mmc, cmd);
200 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
201 mmmc_trace_after_send(mmc, cmd, ret);
202
Marek Vasut8635ff92012-03-15 18:41:35 +0000203 return ret;
Andy Fleming272cc702008-10-30 16:41:01 -0500204}
Simon Glass8ca51e52016-06-12 23:30:22 -0600205#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500206
Paul Burtonda61fa52013-09-09 15:30:26 +0100207int mmc_send_status(struct mmc *mmc, int timeout)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000208{
209 struct mmc_cmd cmd;
Jan Kloetzked617c422012-02-05 22:29:12 +0000210 int err, retries = 5;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000211
212 cmd.cmdidx = MMC_CMD_SEND_STATUS;
213 cmd.resp_type = MMC_RSP_R1;
Marek Vasutaaf3d412011-08-10 09:24:48 +0200214 if (!mmc_host_is_spi(mmc))
215 cmd.cmdarg = mmc->rca << 16;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000216
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500217 while (1) {
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000218 err = mmc_send_cmd(mmc, &cmd, NULL);
Jan Kloetzked617c422012-02-05 22:29:12 +0000219 if (!err) {
220 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
221 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
222 MMC_STATE_PRG)
223 break;
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +0200224
225 if (cmd.response[0] & MMC_STATUS_MASK) {
Paul Burton56196822013-09-04 16:12:25 +0100226#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100227 pr_err("Status Error: 0x%08X\n",
228 cmd.response[0]);
Paul Burton56196822013-09-04 16:12:25 +0100229#endif
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900230 return -ECOMM;
Jan Kloetzked617c422012-02-05 22:29:12 +0000231 }
232 } else if (--retries < 0)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000233 return err;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000234
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500235 if (timeout-- <= 0)
236 break;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000237
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500238 udelay(1000);
239 }
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000240
Simon Glassc0c76eb2016-06-12 23:30:20 -0600241 mmc_trace_state(mmc, &cmd);
Jongman Heo5b0c9422012-06-03 21:32:13 +0000242 if (timeout <= 0) {
Paul Burton56196822013-09-04 16:12:25 +0100243#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100244 pr_err("Timeout waiting card ready\n");
Paul Burton56196822013-09-04 16:12:25 +0100245#endif
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900246 return -ETIMEDOUT;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000247 }
248
249 return 0;
250}
251
Paul Burtonda61fa52013-09-09 15:30:26 +0100252int mmc_set_blocklen(struct mmc *mmc, int len)
Andy Fleming272cc702008-10-30 16:41:01 -0500253{
254 struct mmc_cmd cmd;
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200255 int err;
Andy Fleming272cc702008-10-30 16:41:01 -0500256
Andrew Gabbasov786e8f82014-12-01 06:59:09 -0600257 if (mmc->ddr_mode)
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900258 return 0;
259
Andy Fleming272cc702008-10-30 16:41:01 -0500260 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
261 cmd.resp_type = MMC_RSP_R1;
262 cmd.cmdarg = len;
Andy Fleming272cc702008-10-30 16:41:01 -0500263
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200264 err = mmc_send_cmd(mmc, &cmd, NULL);
265
266#ifdef CONFIG_MMC_QUIRKS
267 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
268 int retries = 4;
269 /*
270 * It has been seen that SET_BLOCKLEN may fail on the first
271 * attempt, let's try a few more time
272 */
273 do {
274 err = mmc_send_cmd(mmc, &cmd, NULL);
275 if (!err)
276 break;
277 } while (retries--);
278 }
279#endif
280
281 return err;
Andy Fleming272cc702008-10-30 16:41:01 -0500282}
283
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100284#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200285static const u8 tuning_blk_pattern_4bit[] = {
286 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
287 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
288 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
289 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
290 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
291 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
292 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
293 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
294};
295
296static const u8 tuning_blk_pattern_8bit[] = {
297 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
298 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
299 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
300 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
301 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
302 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
303 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
304 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
305 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
306 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
307 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
308 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
309 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
310 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
311 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
312 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
313};
314
315int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
316{
317 struct mmc_cmd cmd;
318 struct mmc_data data;
319 const u8 *tuning_block_pattern;
320 int size, err;
321
322 if (mmc->bus_width == 8) {
323 tuning_block_pattern = tuning_blk_pattern_8bit;
324 size = sizeof(tuning_blk_pattern_8bit);
325 } else if (mmc->bus_width == 4) {
326 tuning_block_pattern = tuning_blk_pattern_4bit;
327 size = sizeof(tuning_blk_pattern_4bit);
328 } else {
329 return -EINVAL;
330 }
331
332 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
333
334 cmd.cmdidx = opcode;
335 cmd.cmdarg = 0;
336 cmd.resp_type = MMC_RSP_R1;
337
338 data.dest = (void *)data_buf;
339 data.blocks = 1;
340 data.blocksize = size;
341 data.flags = MMC_DATA_READ;
342
343 err = mmc_send_cmd(mmc, &cmd, &data);
344 if (err)
345 return err;
346
347 if (memcmp(data_buf, tuning_block_pattern, size))
348 return -EIO;
349
350 return 0;
351}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100352#endif
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200353
Sascha Silbeff8fef52013-06-14 13:07:25 +0200354static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
Kim Phillipsfdbb8732012-10-29 13:34:43 +0000355 lbaint_t blkcnt)
Andy Fleming272cc702008-10-30 16:41:01 -0500356{
357 struct mmc_cmd cmd;
358 struct mmc_data data;
359
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700360 if (blkcnt > 1)
361 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
362 else
363 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
Andy Fleming272cc702008-10-30 16:41:01 -0500364
365 if (mmc->high_capacity)
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700366 cmd.cmdarg = start;
Andy Fleming272cc702008-10-30 16:41:01 -0500367 else
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700368 cmd.cmdarg = start * mmc->read_bl_len;
Andy Fleming272cc702008-10-30 16:41:01 -0500369
370 cmd.resp_type = MMC_RSP_R1;
Andy Fleming272cc702008-10-30 16:41:01 -0500371
372 data.dest = dst;
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700373 data.blocks = blkcnt;
Andy Fleming272cc702008-10-30 16:41:01 -0500374 data.blocksize = mmc->read_bl_len;
375 data.flags = MMC_DATA_READ;
376
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700377 if (mmc_send_cmd(mmc, &cmd, &data))
378 return 0;
Andy Fleming272cc702008-10-30 16:41:01 -0500379
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700380 if (blkcnt > 1) {
381 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
382 cmd.cmdarg = 0;
383 cmd.resp_type = MMC_RSP_R1b;
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700384 if (mmc_send_cmd(mmc, &cmd, NULL)) {
Paul Burton56196822013-09-04 16:12:25 +0100385#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100386 pr_err("mmc fail to send stop cmd\n");
Paul Burton56196822013-09-04 16:12:25 +0100387#endif
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700388 return 0;
389 }
Andy Fleming272cc702008-10-30 16:41:01 -0500390 }
391
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700392 return blkcnt;
Andy Fleming272cc702008-10-30 16:41:01 -0500393}
394
Simon Glassc4d660d2017-07-04 13:31:19 -0600395#if CONFIG_IS_ENABLED(BLK)
Simon Glass7dba0b92016-06-12 23:30:15 -0600396ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
Simon Glass33fb2112016-05-01 13:52:41 -0600397#else
Simon Glass7dba0b92016-06-12 23:30:15 -0600398ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
399 void *dst)
Simon Glass33fb2112016-05-01 13:52:41 -0600400#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500401{
Simon Glassc4d660d2017-07-04 13:31:19 -0600402#if CONFIG_IS_ENABLED(BLK)
Simon Glass33fb2112016-05-01 13:52:41 -0600403 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
404#endif
Simon Glassbcce53d2016-02-29 15:25:51 -0700405 int dev_num = block_dev->devnum;
Stephen Warren873cc1d2015-12-07 11:38:49 -0700406 int err;
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700407 lbaint_t cur, blocks_todo = blkcnt;
Andy Fleming272cc702008-10-30 16:41:01 -0500408
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700409 if (blkcnt == 0)
410 return 0;
411
412 struct mmc *mmc = find_mmc_device(dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500413 if (!mmc)
414 return 0;
415
Marek Vasutb5b838f2016-12-01 02:06:33 +0100416 if (CONFIG_IS_ENABLED(MMC_TINY))
417 err = mmc_switch_part(mmc, block_dev->hwpart);
418 else
419 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
420
Stephen Warren873cc1d2015-12-07 11:38:49 -0700421 if (err < 0)
422 return 0;
423
Simon Glassc40fdca2016-05-01 13:52:35 -0600424 if ((start + blkcnt) > block_dev->lba) {
Paul Burton56196822013-09-04 16:12:25 +0100425#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100426 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
427 start + blkcnt, block_dev->lba);
Paul Burton56196822013-09-04 16:12:25 +0100428#endif
Lei Wend2bf29e2010-09-13 22:07:27 +0800429 return 0;
430 }
Andy Fleming272cc702008-10-30 16:41:01 -0500431
Simon Glass11692992015-06-23 15:38:50 -0600432 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900433 pr_debug("%s: Failed to set blocklen\n", __func__);
Andy Fleming272cc702008-10-30 16:41:01 -0500434 return 0;
Simon Glass11692992015-06-23 15:38:50 -0600435 }
Andy Fleming272cc702008-10-30 16:41:01 -0500436
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700437 do {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200438 cur = (blocks_todo > mmc->cfg->b_max) ?
439 mmc->cfg->b_max : blocks_todo;
Simon Glass11692992015-06-23 15:38:50 -0600440 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900441 pr_debug("%s: Failed to read blocks\n", __func__);
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700442 return 0;
Simon Glass11692992015-06-23 15:38:50 -0600443 }
Alagu Sankar4a1a06b2010-10-25 07:23:56 -0700444 blocks_todo -= cur;
445 start += cur;
446 dst += cur * mmc->read_bl_len;
447 } while (blocks_todo > 0);
Andy Fleming272cc702008-10-30 16:41:01 -0500448
449 return blkcnt;
450}
451
Kim Phillipsfdbb8732012-10-29 13:34:43 +0000452static int mmc_go_idle(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -0500453{
454 struct mmc_cmd cmd;
455 int err;
456
457 udelay(1000);
458
459 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
460 cmd.cmdarg = 0;
461 cmd.resp_type = MMC_RSP_NONE;
Andy Fleming272cc702008-10-30 16:41:01 -0500462
463 err = mmc_send_cmd(mmc, &cmd, NULL);
464
465 if (err)
466 return err;
467
468 udelay(2000);
469
470 return 0;
471}
472
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100473#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200474static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
475{
476 struct mmc_cmd cmd;
477 int err = 0;
478
479 /*
480 * Send CMD11 only if the request is to switch the card to
481 * 1.8V signalling.
482 */
483 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
484 return mmc_set_signal_voltage(mmc, signal_voltage);
485
486 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
487 cmd.cmdarg = 0;
488 cmd.resp_type = MMC_RSP_R1;
489
490 err = mmc_send_cmd(mmc, &cmd, NULL);
491 if (err)
492 return err;
493
494 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
495 return -EIO;
496
497 /*
498 * The card should drive cmd and dat[0:3] low immediately
499 * after the response of cmd11, but wait 100 us to be sure
500 */
501 err = mmc_wait_dat0(mmc, 0, 100);
502 if (err == -ENOSYS)
503 udelay(100);
504 else if (err)
505 return -ETIMEDOUT;
506
507 /*
508 * During a signal voltage level switch, the clock must be gated
509 * for 5 ms according to the SD spec
510 */
Jaehoon Chung65117182018-01-26 19:25:29 +0900511 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200512
513 err = mmc_set_signal_voltage(mmc, signal_voltage);
514 if (err)
515 return err;
516
517 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
518 mdelay(10);
Jaehoon Chung65117182018-01-26 19:25:29 +0900519 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200520
521 /*
522 * Failure to switch is indicated by the card holding
523 * dat[0:3] low. Wait for at least 1 ms according to spec
524 */
525 err = mmc_wait_dat0(mmc, 1, 1000);
526 if (err == -ENOSYS)
527 udelay(1000);
528 else if (err)
529 return -ETIMEDOUT;
530
531 return 0;
532}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100533#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200534
535static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
Andy Fleming272cc702008-10-30 16:41:01 -0500536{
537 int timeout = 1000;
538 int err;
539 struct mmc_cmd cmd;
540
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500541 while (1) {
Andy Fleming272cc702008-10-30 16:41:01 -0500542 cmd.cmdidx = MMC_CMD_APP_CMD;
543 cmd.resp_type = MMC_RSP_R1;
544 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -0500545
546 err = mmc_send_cmd(mmc, &cmd, NULL);
547
548 if (err)
549 return err;
550
551 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
552 cmd.resp_type = MMC_RSP_R3;
Stefano Babic250de122010-01-20 18:20:39 +0100553
554 /*
555 * Most cards do not answer if some reserved bits
556 * in the ocr are set. However, Some controller
557 * can set bit 7 (reserved for low voltages), but
558 * how to manage low voltages SD card is not yet
559 * specified.
560 */
Thomas Choud52ebf12010-12-24 13:12:21 +0000561 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200562 (mmc->cfg->voltages & 0xff8000);
Andy Fleming272cc702008-10-30 16:41:01 -0500563
564 if (mmc->version == SD_VERSION_2)
565 cmd.cmdarg |= OCR_HCS;
566
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200567 if (uhs_en)
568 cmd.cmdarg |= OCR_S18R;
569
Andy Fleming272cc702008-10-30 16:41:01 -0500570 err = mmc_send_cmd(mmc, &cmd, NULL);
571
572 if (err)
573 return err;
574
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500575 if (cmd.response[0] & OCR_BUSY)
576 break;
Andy Fleming272cc702008-10-30 16:41:01 -0500577
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500578 if (timeout-- <= 0)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900579 return -EOPNOTSUPP;
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500580
581 udelay(1000);
582 }
Andy Fleming272cc702008-10-30 16:41:01 -0500583
584 if (mmc->version != SD_VERSION_2)
585 mmc->version = SD_VERSION_1_0;
586
Thomas Choud52ebf12010-12-24 13:12:21 +0000587 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
588 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
589 cmd.resp_type = MMC_RSP_R3;
590 cmd.cmdarg = 0;
Thomas Choud52ebf12010-12-24 13:12:21 +0000591
592 err = mmc_send_cmd(mmc, &cmd, NULL);
593
594 if (err)
595 return err;
596 }
597
Rabin Vincent998be3d2009-04-05 13:30:56 +0530598 mmc->ocr = cmd.response[0];
Andy Fleming272cc702008-10-30 16:41:01 -0500599
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100600#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200601 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
602 == 0x41000000) {
603 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
604 if (err)
605 return err;
606 }
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100607#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200608
Andy Fleming272cc702008-10-30 16:41:01 -0500609 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
610 mmc->rca = 0;
611
612 return 0;
613}
614
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500615static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
Andy Fleming272cc702008-10-30 16:41:01 -0500616{
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500617 struct mmc_cmd cmd;
Andy Fleming272cc702008-10-30 16:41:01 -0500618 int err;
619
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500620 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
621 cmd.resp_type = MMC_RSP_R3;
622 cmd.cmdarg = 0;
Rob Herring5a203972015-03-23 17:56:59 -0500623 if (use_arg && !mmc_host_is_spi(mmc))
624 cmd.cmdarg = OCR_HCS |
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200625 (mmc->cfg->voltages &
Andrew Gabbasova626c8d2015-03-19 07:44:03 -0500626 (mmc->ocr & OCR_VOLTAGE_MASK)) |
627 (mmc->ocr & OCR_ACCESS_MODE);
Che-Liang Chioue9550442012-11-28 15:21:13 +0000628
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500629 err = mmc_send_cmd(mmc, &cmd, NULL);
Che-Liang Chioue9550442012-11-28 15:21:13 +0000630 if (err)
631 return err;
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500632 mmc->ocr = cmd.response[0];
Che-Liang Chioue9550442012-11-28 15:21:13 +0000633 return 0;
634}
635
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200636static int mmc_send_op_cond(struct mmc *mmc)
Che-Liang Chioue9550442012-11-28 15:21:13 +0000637{
Che-Liang Chioue9550442012-11-28 15:21:13 +0000638 int err, i;
639
Andy Fleming272cc702008-10-30 16:41:01 -0500640 /* Some cards seem to need this */
641 mmc_go_idle(mmc);
642
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000643 /* Asking to the card its capabilities */
Che-Liang Chioue9550442012-11-28 15:21:13 +0000644 for (i = 0; i < 2; i++) {
Andrew Gabbasov5289b532015-03-19 07:44:04 -0500645 err = mmc_send_op_cond_iter(mmc, i != 0);
Andy Fleming272cc702008-10-30 16:41:01 -0500646 if (err)
647 return err;
648
Che-Liang Chioue9550442012-11-28 15:21:13 +0000649 /* exit if not busy (flag seems to be inverted) */
Andrew Gabbasova626c8d2015-03-19 07:44:03 -0500650 if (mmc->ocr & OCR_BUSY)
Andrew Gabbasovbd47c132015-03-19 07:44:07 -0500651 break;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000652 }
Andrew Gabbasovbd47c132015-03-19 07:44:07 -0500653 mmc->op_cond_pending = 1;
654 return 0;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000655}
Andy Fleming272cc702008-10-30 16:41:01 -0500656
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200657static int mmc_complete_op_cond(struct mmc *mmc)
Che-Liang Chioue9550442012-11-28 15:21:13 +0000658{
659 struct mmc_cmd cmd;
660 int timeout = 1000;
Vipul Kumar36332b62018-05-03 12:20:54 +0530661 ulong start;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000662 int err;
663
664 mmc->op_cond_pending = 0;
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500665 if (!(mmc->ocr & OCR_BUSY)) {
Yangbo Lud188b112016-08-02 15:33:18 +0800666 /* Some cards seem to need this */
667 mmc_go_idle(mmc);
668
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500669 start = get_timer(0);
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500670 while (1) {
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500671 err = mmc_send_op_cond_iter(mmc, 1);
672 if (err)
673 return err;
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500674 if (mmc->ocr & OCR_BUSY)
675 break;
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500676 if (get_timer(start) > timeout)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900677 return -EOPNOTSUPP;
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500678 udelay(100);
Andrew Gabbasov1677eef2015-03-19 07:44:06 -0500679 }
Andrew Gabbasovcc17c012015-03-19 07:44:05 -0500680 }
Andy Fleming272cc702008-10-30 16:41:01 -0500681
Thomas Choud52ebf12010-12-24 13:12:21 +0000682 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
683 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
684 cmd.resp_type = MMC_RSP_R3;
685 cmd.cmdarg = 0;
Thomas Choud52ebf12010-12-24 13:12:21 +0000686
687 err = mmc_send_cmd(mmc, &cmd, NULL);
688
689 if (err)
690 return err;
Andrew Gabbasova626c8d2015-03-19 07:44:03 -0500691
692 mmc->ocr = cmd.response[0];
Thomas Choud52ebf12010-12-24 13:12:21 +0000693 }
694
Andy Fleming272cc702008-10-30 16:41:01 -0500695 mmc->version = MMC_VERSION_UNKNOWN;
Andy Fleming272cc702008-10-30 16:41:01 -0500696
697 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
Stephen Warrendef816a2014-01-30 16:11:12 -0700698 mmc->rca = 1;
Andy Fleming272cc702008-10-30 16:41:01 -0500699
700 return 0;
701}
702
703
Kim Phillipsfdbb8732012-10-29 13:34:43 +0000704static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
Andy Fleming272cc702008-10-30 16:41:01 -0500705{
706 struct mmc_cmd cmd;
707 struct mmc_data data;
708 int err;
709
710 /* Get the Card Status Register */
711 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
712 cmd.resp_type = MMC_RSP_R1;
713 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -0500714
Yoshihiro Shimodacdfd1ac2012-06-07 19:09:11 +0000715 data.dest = (char *)ext_csd;
Andy Fleming272cc702008-10-30 16:41:01 -0500716 data.blocks = 1;
Simon Glass8bfa1952013-04-03 08:54:30 +0000717 data.blocksize = MMC_MAX_BLOCK_LEN;
Andy Fleming272cc702008-10-30 16:41:01 -0500718 data.flags = MMC_DATA_READ;
719
720 err = mmc_send_cmd(mmc, &cmd, &data);
721
722 return err;
723}
724
Simon Glassc40704f2016-06-12 23:30:18 -0600725int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
Andy Fleming272cc702008-10-30 16:41:01 -0500726{
727 struct mmc_cmd cmd;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000728 int timeout = 1000;
Maxime Riparda9003dc2016-11-04 16:18:08 +0100729 int retries = 3;
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000730 int ret;
Andy Fleming272cc702008-10-30 16:41:01 -0500731
732 cmd.cmdidx = MMC_CMD_SWITCH;
733 cmd.resp_type = MMC_RSP_R1b;
734 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000735 (index << 16) |
736 (value << 8);
Andy Fleming272cc702008-10-30 16:41:01 -0500737
Maxime Riparda9003dc2016-11-04 16:18:08 +0100738 while (retries > 0) {
739 ret = mmc_send_cmd(mmc, &cmd, NULL);
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000740
Maxime Riparda9003dc2016-11-04 16:18:08 +0100741 /* Waiting for the ready status */
742 if (!ret) {
743 ret = mmc_send_status(mmc, timeout);
744 return ret;
745 }
746
747 retries--;
748 }
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000749
750 return ret;
751
Andy Fleming272cc702008-10-30 16:41:01 -0500752}
753
Marek Vasut62d77ce2018-04-15 00:37:11 +0200754#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200755static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
Andy Fleming272cc702008-10-30 16:41:01 -0500756{
Andy Fleming272cc702008-10-30 16:41:01 -0500757 int err;
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200758 int speed_bits;
759
760 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
761
762 switch (mode) {
763 case MMC_HS:
764 case MMC_HS_52:
765 case MMC_DDR_52:
766 speed_bits = EXT_CSD_TIMING_HS;
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200767 break;
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100768#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200769 case MMC_HS_200:
770 speed_bits = EXT_CSD_TIMING_HS200;
771 break;
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100772#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200773 case MMC_LEGACY:
774 speed_bits = EXT_CSD_TIMING_LEGACY;
775 break;
776 default:
777 return -EINVAL;
778 }
779 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
780 speed_bits);
781 if (err)
782 return err;
783
784 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
785 /* Now check to see that it worked */
786 err = mmc_send_ext_csd(mmc, test_csd);
787 if (err)
788 return err;
789
790 /* No high-speed support */
791 if (!test_csd[EXT_CSD_HS_TIMING])
792 return -ENOTSUPP;
793 }
794
795 return 0;
796}
797
798static int mmc_get_capabilities(struct mmc *mmc)
799{
800 u8 *ext_csd = mmc->ext_csd;
801 char cardtype;
Andy Fleming272cc702008-10-30 16:41:01 -0500802
Jean-Jacques Hiblot00e446f2017-11-30 17:43:56 +0100803 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
Andy Fleming272cc702008-10-30 16:41:01 -0500804
Thomas Choud52ebf12010-12-24 13:12:21 +0000805 if (mmc_host_is_spi(mmc))
806 return 0;
807
Andy Fleming272cc702008-10-30 16:41:01 -0500808 /* Only version 4 supports high-speed */
809 if (mmc->version < MMC_VERSION_4)
810 return 0;
811
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200812 if (!ext_csd) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100813 pr_err("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200814 return -ENOTSUPP;
815 }
816
Andrew Gabbasovfc5b32f2014-12-25 10:22:25 -0600817 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
818
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200819 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200820 mmc->cardtype = cardtype;
Andy Fleming272cc702008-10-30 16:41:01 -0500821
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100822#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200823 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
824 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
825 mmc->card_caps |= MMC_MODE_HS200;
826 }
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +0100827#endif
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900828 if (cardtype & EXT_CSD_CARD_TYPE_52) {
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200829 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900830 mmc->card_caps |= MMC_MODE_DDR_52MHz;
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200831 mmc->card_caps |= MMC_MODE_HS_52MHz;
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900832 }
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200833 if (cardtype & EXT_CSD_CARD_TYPE_26)
834 mmc->card_caps |= MMC_MODE_HS;
Andy Fleming272cc702008-10-30 16:41:01 -0500835
836 return 0;
837}
Marek Vasut62d77ce2018-04-15 00:37:11 +0200838#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500839
Stephen Warrenf866a462013-06-11 15:14:01 -0600840static int mmc_set_capacity(struct mmc *mmc, int part_num)
841{
842 switch (part_num) {
843 case 0:
844 mmc->capacity = mmc->capacity_user;
845 break;
846 case 1:
847 case 2:
848 mmc->capacity = mmc->capacity_boot;
849 break;
850 case 3:
851 mmc->capacity = mmc->capacity_rpmb;
852 break;
853 case 4:
854 case 5:
855 case 6:
856 case 7:
857 mmc->capacity = mmc->capacity_gp[part_num - 4];
858 break;
859 default:
860 return -1;
861 }
862
Simon Glassc40fdca2016-05-01 13:52:35 -0600863 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Stephen Warrenf866a462013-06-11 15:14:01 -0600864
865 return 0;
866}
867
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100868#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200869static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
870{
871 int forbidden = 0;
872 bool change = false;
873
874 if (part_num & PART_ACCESS_MASK)
875 forbidden = MMC_CAP(MMC_HS_200);
876
877 if (MMC_CAP(mmc->selected_mode) & forbidden) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900878 pr_debug("selected mode (%s) is forbidden for part %d\n",
879 mmc_mode_name(mmc->selected_mode), part_num);
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200880 change = true;
881 } else if (mmc->selected_mode != mmc->best_mode) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +0900882 pr_debug("selected mode is not optimal\n");
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200883 change = true;
884 }
885
886 if (change)
887 return mmc_select_mode_and_width(mmc,
888 mmc->card_caps & ~forbidden);
889
890 return 0;
891}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100892#else
893static inline int mmc_boot_part_access_chk(struct mmc *mmc,
894 unsigned int part_num)
895{
896 return 0;
897}
898#endif
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200899
Simon Glass7dba0b92016-06-12 23:30:15 -0600900int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
Lei Wenbc897b12011-05-02 16:26:26 +0000901{
Stephen Warrenf866a462013-06-11 15:14:01 -0600902 int ret;
Lei Wenbc897b12011-05-02 16:26:26 +0000903
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200904 ret = mmc_boot_part_access_chk(mmc, part_num);
905 if (ret)
906 return ret;
907
Stephen Warrenf866a462013-06-11 15:14:01 -0600908 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
909 (mmc->part_config & ~PART_ACCESS_MASK)
910 | (part_num & PART_ACCESS_MASK));
Stephen Warrenf866a462013-06-11 15:14:01 -0600911
Peter Bigot6dc93e72014-09-02 18:31:23 -0500912 /*
913 * Set the capacity if the switch succeeded or was intended
914 * to return to representing the raw device.
915 */
Stephen Warren873cc1d2015-12-07 11:38:49 -0700916 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
Peter Bigot6dc93e72014-09-02 18:31:23 -0500917 ret = mmc_set_capacity(mmc, part_num);
Simon Glassfdbb1392016-05-01 13:52:37 -0600918 mmc_get_blk_desc(mmc)->hwpart = part_num;
Stephen Warren873cc1d2015-12-07 11:38:49 -0700919 }
Peter Bigot6dc93e72014-09-02 18:31:23 -0500920
921 return ret;
Lei Wenbc897b12011-05-02 16:26:26 +0000922}
923
Jean-Jacques Hiblotcf177892017-11-30 17:44:02 +0100924#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100925int mmc_hwpart_config(struct mmc *mmc,
926 const struct mmc_hwpart_conf *conf,
927 enum mmc_hwpart_conf_mode mode)
928{
929 u8 part_attrs = 0;
930 u32 enh_size_mult;
931 u32 enh_start_addr;
932 u32 gp_size_mult[4];
933 u32 max_enh_size_mult;
934 u32 tot_enh_size_mult = 0;
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100935 u8 wr_rel_set;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100936 int i, pidx, err;
937 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
938
939 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
940 return -EINVAL;
941
942 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100943 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100944 return -EMEDIUMTYPE;
945 }
946
947 if (!(mmc->part_support & PART_SUPPORT)) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100948 pr_err("Card does not support partitioning\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100949 return -EMEDIUMTYPE;
950 }
951
952 if (!mmc->hc_wp_grp_size) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100953 pr_err("Card does not define HC WP group size\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100954 return -EMEDIUMTYPE;
955 }
956
957 /* check partition alignment and total enhanced size */
958 if (conf->user.enh_size) {
959 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
960 conf->user.enh_start % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100961 pr_err("User data enhanced area not HC WP group "
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100962 "size aligned\n");
963 return -EINVAL;
964 }
965 part_attrs |= EXT_CSD_ENH_USR;
966 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
967 if (mmc->high_capacity) {
968 enh_start_addr = conf->user.enh_start;
969 } else {
970 enh_start_addr = (conf->user.enh_start << 9);
971 }
972 } else {
973 enh_size_mult = 0;
974 enh_start_addr = 0;
975 }
976 tot_enh_size_mult += enh_size_mult;
977
978 for (pidx = 0; pidx < 4; pidx++) {
979 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100980 pr_err("GP%i partition not HC WP group size "
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100981 "aligned\n", pidx+1);
982 return -EINVAL;
983 }
984 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
985 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
986 part_attrs |= EXT_CSD_ENH_GP(pidx);
987 tot_enh_size_mult += gp_size_mult[pidx];
988 }
989 }
990
991 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +0100992 pr_err("Card does not support enhanced attribute\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100993 return -EMEDIUMTYPE;
994 }
995
996 err = mmc_send_ext_csd(mmc, ext_csd);
997 if (err)
998 return err;
999
1000 max_enh_size_mult =
1001 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1002 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1003 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1004 if (tot_enh_size_mult > max_enh_size_mult) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001005 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001006 tot_enh_size_mult, max_enh_size_mult);
1007 return -EMEDIUMTYPE;
1008 }
1009
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +01001010 /* The default value of EXT_CSD_WR_REL_SET is device
1011 * dependent, the values can only be changed if the
1012 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1013 * changed only once and before partitioning is completed. */
1014 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1015 if (conf->user.wr_rel_change) {
1016 if (conf->user.wr_rel_set)
1017 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1018 else
1019 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1020 }
1021 for (pidx = 0; pidx < 4; pidx++) {
1022 if (conf->gp_part[pidx].wr_rel_change) {
1023 if (conf->gp_part[pidx].wr_rel_set)
1024 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1025 else
1026 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1027 }
1028 }
1029
1030 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1031 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1032 puts("Card does not support host controlled partition write "
1033 "reliability settings\n");
1034 return -EMEDIUMTYPE;
1035 }
1036
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001037 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1038 EXT_CSD_PARTITION_SETTING_COMPLETED) {
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001039 pr_err("Card already partitioned\n");
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001040 return -EPERM;
1041 }
1042
1043 if (mode == MMC_HWPART_CONF_CHECK)
1044 return 0;
1045
1046 /* Partitioning requires high-capacity size definitions */
1047 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1048 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1049 EXT_CSD_ERASE_GROUP_DEF, 1);
1050
1051 if (err)
1052 return err;
1053
1054 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1055
1056 /* update erase group size to be high-capacity */
1057 mmc->erase_grp_size =
1058 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1059
1060 }
1061
1062 /* all OK, write the configuration */
1063 for (i = 0; i < 4; i++) {
1064 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1065 EXT_CSD_ENH_START_ADDR+i,
1066 (enh_start_addr >> (i*8)) & 0xFF);
1067 if (err)
1068 return err;
1069 }
1070 for (i = 0; i < 3; i++) {
1071 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1072 EXT_CSD_ENH_SIZE_MULT+i,
1073 (enh_size_mult >> (i*8)) & 0xFF);
1074 if (err)
1075 return err;
1076 }
1077 for (pidx = 0; pidx < 4; pidx++) {
1078 for (i = 0; i < 3; i++) {
1079 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1080 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1081 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1082 if (err)
1083 return err;
1084 }
1085 }
1086 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1087 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1088 if (err)
1089 return err;
1090
1091 if (mode == MMC_HWPART_CONF_SET)
1092 return 0;
1093
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +01001094 /* The WR_REL_SET is a write-once register but shall be
1095 * written before setting PART_SETTING_COMPLETED. As it is
1096 * write-once we can only write it when completing the
1097 * partitioning. */
1098 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1099 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1100 EXT_CSD_WR_REL_SET, wr_rel_set);
1101 if (err)
1102 return err;
1103 }
1104
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001105 /* Setting PART_SETTING_COMPLETED confirms the partition
1106 * configuration but it only becomes effective after power
1107 * cycle, so we do not adjust the partition related settings
1108 * in the mmc struct. */
1109
1110 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1111 EXT_CSD_PARTITION_SETTING,
1112 EXT_CSD_PARTITION_SETTING_COMPLETED);
1113 if (err)
1114 return err;
1115
1116 return 0;
1117}
Jean-Jacques Hiblotcf177892017-11-30 17:44:02 +01001118#endif
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +01001119
Simon Glasse7881d82017-07-29 11:35:31 -06001120#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Reding48972d92012-01-02 01:15:37 +00001121int mmc_getcd(struct mmc *mmc)
1122{
1123 int cd;
1124
1125 cd = board_mmc_getcd(mmc);
1126
Peter Korsgaardd4e1da42013-03-21 04:00:03 +00001127 if (cd < 0) {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001128 if (mmc->cfg->ops->getcd)
1129 cd = mmc->cfg->ops->getcd(mmc);
Peter Korsgaardd4e1da42013-03-21 04:00:03 +00001130 else
1131 cd = 1;
1132 }
Thierry Reding48972d92012-01-02 01:15:37 +00001133
1134 return cd;
1135}
Simon Glass8ca51e52016-06-12 23:30:22 -06001136#endif
Thierry Reding48972d92012-01-02 01:15:37 +00001137
Marek Vasut62d77ce2018-04-15 00:37:11 +02001138#if !CONFIG_IS_ENABLED(MMC_TINY)
Kim Phillipsfdbb8732012-10-29 13:34:43 +00001139static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
Andy Fleming272cc702008-10-30 16:41:01 -05001140{
1141 struct mmc_cmd cmd;
1142 struct mmc_data data;
1143
1144 /* Switch the frequency */
1145 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1146 cmd.resp_type = MMC_RSP_R1;
1147 cmd.cmdarg = (mode << 31) | 0xffffff;
1148 cmd.cmdarg &= ~(0xf << (group * 4));
1149 cmd.cmdarg |= value << (group * 4);
Andy Fleming272cc702008-10-30 16:41:01 -05001150
1151 data.dest = (char *)resp;
1152 data.blocksize = 64;
1153 data.blocks = 1;
1154 data.flags = MMC_DATA_READ;
1155
1156 return mmc_send_cmd(mmc, &cmd, &data);
1157}
1158
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001159static int sd_get_capabilities(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05001160{
1161 int err;
1162 struct mmc_cmd cmd;
Suniel Mahesh18e7c8f2017-10-05 11:32:00 +05301163 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1164 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
Andy Fleming272cc702008-10-30 16:41:01 -05001165 struct mmc_data data;
1166 int timeout;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001167#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001168 u32 sd3_bus_mode;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001169#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001170
Jean-Jacques Hiblot00e446f2017-11-30 17:43:56 +01001171 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
Andy Fleming272cc702008-10-30 16:41:01 -05001172
Thomas Choud52ebf12010-12-24 13:12:21 +00001173 if (mmc_host_is_spi(mmc))
1174 return 0;
1175
Andy Fleming272cc702008-10-30 16:41:01 -05001176 /* Read the SCR to find out if this card supports higher speeds */
1177 cmd.cmdidx = MMC_CMD_APP_CMD;
1178 cmd.resp_type = MMC_RSP_R1;
1179 cmd.cmdarg = mmc->rca << 16;
Andy Fleming272cc702008-10-30 16:41:01 -05001180
1181 err = mmc_send_cmd(mmc, &cmd, NULL);
1182
1183 if (err)
1184 return err;
1185
1186 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1187 cmd.resp_type = MMC_RSP_R1;
1188 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -05001189
1190 timeout = 3;
1191
1192retry_scr:
Anton staaff781dd32011-10-03 13:54:59 +00001193 data.dest = (char *)scr;
Andy Fleming272cc702008-10-30 16:41:01 -05001194 data.blocksize = 8;
1195 data.blocks = 1;
1196 data.flags = MMC_DATA_READ;
1197
1198 err = mmc_send_cmd(mmc, &cmd, &data);
1199
1200 if (err) {
1201 if (timeout--)
1202 goto retry_scr;
1203
1204 return err;
1205 }
1206
Yauhen Kharuzhy4e3d89b2009-05-07 00:43:30 +03001207 mmc->scr[0] = __be32_to_cpu(scr[0]);
1208 mmc->scr[1] = __be32_to_cpu(scr[1]);
Andy Fleming272cc702008-10-30 16:41:01 -05001209
1210 switch ((mmc->scr[0] >> 24) & 0xf) {
Bin Meng53e8e402016-03-17 21:53:13 -07001211 case 0:
1212 mmc->version = SD_VERSION_1_0;
1213 break;
1214 case 1:
1215 mmc->version = SD_VERSION_1_10;
1216 break;
1217 case 2:
1218 mmc->version = SD_VERSION_2;
1219 if ((mmc->scr[0] >> 15) & 0x1)
1220 mmc->version = SD_VERSION_3;
1221 break;
1222 default:
1223 mmc->version = SD_VERSION_1_0;
1224 break;
Andy Fleming272cc702008-10-30 16:41:01 -05001225 }
1226
Alagu Sankarb44c7082010-05-12 15:08:24 +05301227 if (mmc->scr[0] & SD_DATA_4BIT)
1228 mmc->card_caps |= MMC_MODE_4BIT;
1229
Andy Fleming272cc702008-10-30 16:41:01 -05001230 /* Version 1.0 doesn't support switching */
1231 if (mmc->version == SD_VERSION_1_0)
1232 return 0;
1233
1234 timeout = 4;
1235 while (timeout--) {
1236 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
Anton staaff781dd32011-10-03 13:54:59 +00001237 (u8 *)switch_status);
Andy Fleming272cc702008-10-30 16:41:01 -05001238
1239 if (err)
1240 return err;
1241
1242 /* The high-speed function is busy. Try again */
Yauhen Kharuzhy4e3d89b2009-05-07 00:43:30 +03001243 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
Andy Fleming272cc702008-10-30 16:41:01 -05001244 break;
1245 }
1246
Andy Fleming272cc702008-10-30 16:41:01 -05001247 /* If high-speed isn't supported, we return */
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001248 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1249 mmc->card_caps |= MMC_CAP(SD_HS);
Andy Fleming272cc702008-10-30 16:41:01 -05001250
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001251#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001252 /* Version before 3.0 don't support UHS modes */
1253 if (mmc->version < SD_VERSION_3)
1254 return 0;
1255
1256 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1257 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1258 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1259 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1260 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1261 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1262 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1263 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1264 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1265 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1266 mmc->card_caps |= MMC_CAP(UHS_DDR50);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001267#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001268
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001269 return 0;
1270}
1271
1272static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1273{
1274 int err;
1275
1276 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001277 int speed;
Macpaul Lin2c3fbf42011-11-28 16:31:09 +00001278
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001279 switch (mode) {
1280 case SD_LEGACY:
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001281 speed = UHS_SDR12_BUS_SPEED;
1282 break;
1283 case SD_HS:
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +01001284 speed = HIGH_SPEED_BUS_SPEED;
1285 break;
1286#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1287 case UHS_SDR12:
1288 speed = UHS_SDR12_BUS_SPEED;
1289 break;
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001290 case UHS_SDR25:
1291 speed = UHS_SDR25_BUS_SPEED;
1292 break;
1293 case UHS_SDR50:
1294 speed = UHS_SDR50_BUS_SPEED;
1295 break;
1296 case UHS_DDR50:
1297 speed = UHS_DDR50_BUS_SPEED;
1298 break;
1299 case UHS_SDR104:
1300 speed = UHS_SDR104_BUS_SPEED;
1301 break;
Jean-Jacques Hiblotbaef2072018-01-04 15:23:30 +01001302#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001303 default:
1304 return -EINVAL;
1305 }
1306
1307 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
Andy Fleming272cc702008-10-30 16:41:01 -05001308 if (err)
1309 return err;
1310
Jean-Jacques Hiblota0276f32018-02-09 12:09:27 +01001311 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001312 return -ENOTSUPP;
1313
1314 return 0;
1315}
1316
Marek Vasutec360e62018-04-15 00:36:45 +02001317static int sd_select_bus_width(struct mmc *mmc, int w)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001318{
1319 int err;
1320 struct mmc_cmd cmd;
1321
1322 if ((w != 4) && (w != 1))
1323 return -EINVAL;
1324
1325 cmd.cmdidx = MMC_CMD_APP_CMD;
1326 cmd.resp_type = MMC_RSP_R1;
1327 cmd.cmdarg = mmc->rca << 16;
1328
1329 err = mmc_send_cmd(mmc, &cmd, NULL);
1330 if (err)
1331 return err;
1332
1333 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1334 cmd.resp_type = MMC_RSP_R1;
1335 if (w == 4)
1336 cmd.cmdarg = 2;
1337 else if (w == 1)
1338 cmd.cmdarg = 0;
1339 err = mmc_send_cmd(mmc, &cmd, NULL);
1340 if (err)
1341 return err;
Andy Fleming272cc702008-10-30 16:41:01 -05001342
1343 return 0;
1344}
Marek Vasut62d77ce2018-04-15 00:37:11 +02001345#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001346
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001347#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fan3697e592016-09-01 11:13:38 +08001348static int sd_read_ssr(struct mmc *mmc)
1349{
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001350 static const unsigned int sd_au_size[] = {
1351 0, SZ_16K / 512, SZ_32K / 512,
1352 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1353 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1354 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1355 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1356 SZ_64M / 512,
1357 };
Peng Fan3697e592016-09-01 11:13:38 +08001358 int err, i;
1359 struct mmc_cmd cmd;
1360 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1361 struct mmc_data data;
1362 int timeout = 3;
1363 unsigned int au, eo, et, es;
1364
1365 cmd.cmdidx = MMC_CMD_APP_CMD;
1366 cmd.resp_type = MMC_RSP_R1;
1367 cmd.cmdarg = mmc->rca << 16;
1368
1369 err = mmc_send_cmd(mmc, &cmd, NULL);
1370 if (err)
1371 return err;
1372
1373 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1374 cmd.resp_type = MMC_RSP_R1;
1375 cmd.cmdarg = 0;
1376
1377retry_ssr:
1378 data.dest = (char *)ssr;
1379 data.blocksize = 64;
1380 data.blocks = 1;
1381 data.flags = MMC_DATA_READ;
1382
1383 err = mmc_send_cmd(mmc, &cmd, &data);
1384 if (err) {
1385 if (timeout--)
1386 goto retry_ssr;
1387
1388 return err;
1389 }
1390
1391 for (i = 0; i < 16; i++)
1392 ssr[i] = be32_to_cpu(ssr[i]);
1393
1394 au = (ssr[2] >> 12) & 0xF;
1395 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1396 mmc->ssr.au = sd_au_size[au];
1397 es = (ssr[3] >> 24) & 0xFF;
1398 es |= (ssr[2] & 0xFF) << 8;
1399 et = (ssr[3] >> 18) & 0x3F;
1400 if (es && et) {
1401 eo = (ssr[3] >> 16) & 0x3;
1402 mmc->ssr.erase_timeout = (et * 1000) / es;
1403 mmc->ssr.erase_offset = eo * 1000;
1404 }
1405 } else {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001406 pr_debug("Invalid Allocation Unit Size.\n");
Peng Fan3697e592016-09-01 11:13:38 +08001407 }
1408
1409 return 0;
1410}
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001411#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001412/* frequency bases */
1413/* divided by 10 to be nice to platforms without floating point */
Mike Frysinger5f837c22010-10-20 01:15:53 +00001414static const int fbase[] = {
Andy Fleming272cc702008-10-30 16:41:01 -05001415 10000,
1416 100000,
1417 1000000,
1418 10000000,
1419};
1420
1421/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1422 * to platforms without floating point.
1423 */
Simon Glass61fe0762016-05-14 14:02:57 -06001424static const u8 multipliers[] = {
Andy Fleming272cc702008-10-30 16:41:01 -05001425 0, /* reserved */
1426 10,
1427 12,
1428 13,
1429 15,
1430 20,
1431 25,
1432 30,
1433 35,
1434 40,
1435 45,
1436 50,
1437 55,
1438 60,
1439 70,
1440 80,
1441};
1442
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001443static inline int bus_width(uint cap)
1444{
1445 if (cap == MMC_MODE_8BIT)
1446 return 8;
1447 if (cap == MMC_MODE_4BIT)
1448 return 4;
1449 if (cap == MMC_MODE_1BIT)
1450 return 1;
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001451 pr_warn("invalid bus witdh capability 0x%x\n", cap);
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001452 return 0;
1453}
1454
Simon Glasse7881d82017-07-29 11:35:31 -06001455#if !CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001456#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +02001457static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1458{
1459 return -ENOTSUPP;
1460}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001461#endif
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +02001462
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +02001463static void mmc_send_init_stream(struct mmc *mmc)
1464{
1465}
1466
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001467static int mmc_set_ios(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05001468{
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001469 int ret = 0;
1470
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001471 if (mmc->cfg->ops->set_ios)
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001472 ret = mmc->cfg->ops->set_ios(mmc);
1473
1474 return ret;
Andy Fleming272cc702008-10-30 16:41:01 -05001475}
Simon Glass8ca51e52016-06-12 23:30:22 -06001476#endif
Andy Fleming272cc702008-10-30 16:41:01 -05001477
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +02001478int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
Andy Fleming272cc702008-10-30 16:41:01 -05001479{
Jaehoon Chungc0fafe62018-01-23 14:04:30 +09001480 if (!disable) {
Jaehoon Chung9546eb92018-01-17 19:36:58 +09001481 if (clock > mmc->cfg->f_max)
1482 clock = mmc->cfg->f_max;
Andy Fleming272cc702008-10-30 16:41:01 -05001483
Jaehoon Chung9546eb92018-01-17 19:36:58 +09001484 if (clock < mmc->cfg->f_min)
1485 clock = mmc->cfg->f_min;
1486 }
Andy Fleming272cc702008-10-30 16:41:01 -05001487
1488 mmc->clock = clock;
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +02001489 mmc->clk_disable = disable;
Andy Fleming272cc702008-10-30 16:41:01 -05001490
Jaehoon Chungd2faadb2018-01-26 19:25:30 +09001491 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1492
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001493 return mmc_set_ios(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05001494}
1495
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001496static int mmc_set_bus_width(struct mmc *mmc, uint width)
Andy Fleming272cc702008-10-30 16:41:01 -05001497{
1498 mmc->bus_width = width;
1499
Kishon Vijay Abraham I2a4d2122017-09-21 16:29:59 +02001500 return mmc_set_ios(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05001501}
1502
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001503#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1504/*
1505 * helper function to display the capabilities in a human
1506 * friendly manner. The capabilities include bus width and
1507 * supported modes.
1508 */
1509void mmc_dump_capabilities(const char *text, uint caps)
1510{
1511 enum bus_mode mode;
1512
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001513 pr_debug("%s: widths [", text);
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001514 if (caps & MMC_MODE_8BIT)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001515 pr_debug("8, ");
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001516 if (caps & MMC_MODE_4BIT)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001517 pr_debug("4, ");
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001518 if (caps & MMC_MODE_1BIT)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001519 pr_debug("1, ");
1520 pr_debug("\b\b] modes [");
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001521 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1522 if (MMC_CAP(mode) & caps)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001523 pr_debug("%s, ", mmc_mode_name(mode));
1524 pr_debug("\b\b]\n");
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +02001525}
1526#endif
1527
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001528struct mode_width_tuning {
1529 enum bus_mode mode;
1530 uint widths;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001531#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001532 uint tuning;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001533#endif
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001534};
1535
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001536#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001537int mmc_voltage_to_mv(enum mmc_voltage voltage)
1538{
1539 switch (voltage) {
1540 case MMC_SIGNAL_VOLTAGE_000: return 0;
1541 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1542 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1543 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1544 }
1545 return -EINVAL;
1546}
1547
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001548static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1549{
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001550 int err;
1551
1552 if (mmc->signal_voltage == signal_voltage)
1553 return 0;
1554
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001555 mmc->signal_voltage = signal_voltage;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001556 err = mmc_set_ios(mmc);
1557 if (err)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001558 pr_debug("unable to set voltage (err %d)\n", err);
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001559
1560 return err;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001561}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001562#else
1563static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1564{
1565 return 0;
1566}
1567#endif
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02001568
Marek Vasut62d77ce2018-04-15 00:37:11 +02001569#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001570static const struct mode_width_tuning sd_modes_by_pref[] = {
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001571#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1572#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001573 {
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001574 .mode = UHS_SDR104,
1575 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1576 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1577 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001578#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001579 {
1580 .mode = UHS_SDR50,
1581 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1582 },
1583 {
1584 .mode = UHS_DDR50,
1585 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1586 },
1587 {
1588 .mode = UHS_SDR25,
1589 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1590 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001591#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001592 {
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001593 .mode = SD_HS,
1594 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1595 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001596#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001597 {
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001598 .mode = UHS_SDR12,
1599 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1600 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001601#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001602 {
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001603 .mode = SD_LEGACY,
1604 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1605 }
1606};
1607
1608#define for_each_sd_mode_by_pref(caps, mwt) \
1609 for (mwt = sd_modes_by_pref;\
1610 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1611 mwt++) \
1612 if (caps & MMC_CAP(mwt->mode))
1613
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02001614static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001615{
1616 int err;
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001617 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1618 const struct mode_width_tuning *mwt;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001619#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001620 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001621#else
1622 bool uhs_en = false;
1623#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001624 uint caps;
1625
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001626#ifdef DEBUG
1627 mmc_dump_capabilities("sd card", card_caps);
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001628 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001629#endif
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001630
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001631 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001632 caps = card_caps & mmc->host_caps;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001633
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001634 if (!uhs_en)
1635 caps &= ~UHS_CAPS;
1636
1637 for_each_sd_mode_by_pref(caps, mwt) {
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001638 uint *w;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001639
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001640 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001641 if (*w & caps & mwt->widths) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001642 pr_debug("trying mode %s width %d (at %d MHz)\n",
1643 mmc_mode_name(mwt->mode),
1644 bus_width(*w),
1645 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001646
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001647 /* configure the bus width (card + host) */
1648 err = sd_select_bus_width(mmc, bus_width(*w));
1649 if (err)
1650 goto error;
1651 mmc_set_bus_width(mmc, bus_width(*w));
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001652
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001653 /* configure the bus mode (card) */
1654 err = sd_set_card_speed(mmc, mwt->mode);
1655 if (err)
1656 goto error;
1657
1658 /* configure the bus mode (host) */
1659 mmc_select_mode(mmc, mwt->mode);
Jaehoon Chung65117182018-01-26 19:25:29 +09001660 mmc_set_clock(mmc, mmc->tran_speed,
1661 MMC_CLK_ENABLE);
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001662
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001663#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001664 /* execute tuning if needed */
1665 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1666 err = mmc_execute_tuning(mmc,
1667 mwt->tuning);
1668 if (err) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001669 pr_debug("tuning failed\n");
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001670 goto error;
1671 }
1672 }
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001673#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02001674
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001675#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001676 err = sd_read_ssr(mmc);
Peng Fan0a4c2b02018-03-05 16:20:40 +08001677 if (err)
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +01001678 pr_warn("unable to read ssr\n");
1679#endif
1680 if (!err)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001681 return 0;
1682
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001683error:
1684 /* revert to a safer bus speed */
1685 mmc_select_mode(mmc, SD_LEGACY);
Jaehoon Chung65117182018-01-26 19:25:29 +09001686 mmc_set_clock(mmc, mmc->tran_speed,
1687 MMC_CLK_ENABLE);
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001688 }
1689 }
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001690 }
1691
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001692 pr_err("unable to select a mode\n");
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +02001693 return -ENOTSUPP;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001694}
1695
Jean-Jacques Hiblot7382e692017-09-21 16:29:52 +02001696/*
1697 * read the compare the part of ext csd that is constant.
1698 * This can be used to check that the transfer is working
1699 * as expected.
1700 */
1701static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1702{
1703 int err;
1704 const u8 *ext_csd = mmc->ext_csd;
1705 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1706
Jean-Jacques Hiblot1de06b92017-11-30 17:43:58 +01001707 if (mmc->version < MMC_VERSION_4)
1708 return 0;
1709
Jean-Jacques Hiblot7382e692017-09-21 16:29:52 +02001710 err = mmc_send_ext_csd(mmc, test_csd);
1711 if (err)
1712 return err;
1713
1714 /* Only compare read only fields */
1715 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1716 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1717 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1718 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1719 ext_csd[EXT_CSD_REV]
1720 == test_csd[EXT_CSD_REV] &&
1721 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1722 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1723 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1724 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1725 return 0;
1726
1727 return -EBADMSG;
1728}
1729
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001730#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001731static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1732 uint32_t allowed_mask)
1733{
1734 u32 card_mask = 0;
1735
1736 switch (mode) {
1737 case MMC_HS_200:
1738 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1739 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1740 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1741 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1742 break;
1743 case MMC_DDR_52:
1744 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1745 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1746 MMC_SIGNAL_VOLTAGE_180;
1747 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1748 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1749 break;
1750 default:
1751 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1752 break;
1753 }
1754
1755 while (card_mask & allowed_mask) {
1756 enum mmc_voltage best_match;
1757
1758 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1759 if (!mmc_set_signal_voltage(mmc, best_match))
1760 return 0;
1761
1762 allowed_mask &= ~best_match;
1763 }
1764
1765 return -ENOTSUPP;
1766}
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001767#else
1768static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1769 uint32_t allowed_mask)
1770{
1771 return 0;
1772}
1773#endif
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001774
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001775static const struct mode_width_tuning mmc_modes_by_pref[] = {
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001776#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001777 {
1778 .mode = MMC_HS_200,
1779 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001780 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001781 },
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001782#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001783 {
1784 .mode = MMC_DDR_52,
1785 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1786 },
1787 {
1788 .mode = MMC_HS_52,
1789 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1790 },
1791 {
1792 .mode = MMC_HS,
1793 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1794 },
1795 {
1796 .mode = MMC_LEGACY,
1797 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1798 }
1799};
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001800
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001801#define for_each_mmc_mode_by_pref(caps, mwt) \
1802 for (mwt = mmc_modes_by_pref;\
1803 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1804 mwt++) \
1805 if (caps & MMC_CAP(mwt->mode))
1806
1807static const struct ext_csd_bus_width {
1808 uint cap;
1809 bool is_ddr;
1810 uint ext_csd_bits;
1811} ext_csd_bus_width[] = {
1812 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1813 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1814 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1815 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1816 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1817};
1818
1819#define for_each_supported_width(caps, ddr, ecbv) \
1820 for (ecbv = ext_csd_bus_width;\
1821 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1822 ecbv++) \
1823 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1824
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02001825static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001826{
1827 int err;
1828 const struct mode_width_tuning *mwt;
1829 const struct ext_csd_bus_width *ecbw;
1830
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001831#ifdef DEBUG
1832 mmc_dump_capabilities("mmc", card_caps);
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001833 mmc_dump_capabilities("host", mmc->host_caps);
Jean-Jacques Hiblot52d241d2017-11-30 17:43:54 +01001834#endif
1835
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001836 /* Restrict card's capabilities by what the host can do */
Jean-Jacques Hiblot1da8eb52017-11-30 17:43:57 +01001837 card_caps &= mmc->host_caps;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001838
1839 /* Only version 4 of MMC supports wider bus widths */
1840 if (mmc->version < MMC_VERSION_4)
1841 return 0;
1842
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02001843 if (!mmc->ext_csd) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001844 pr_debug("No ext_csd found!\n"); /* this should enver happen */
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02001845 return -ENOTSUPP;
1846 }
1847
Jaehoon Chung65117182018-01-26 19:25:29 +09001848 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02001849
1850 for_each_mmc_mode_by_pref(card_caps, mwt) {
1851 for_each_supported_width(card_caps & mwt->widths,
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001852 mmc_is_mode_ddr(mwt->mode), ecbw) {
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001853 enum mmc_voltage old_voltage;
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001854 pr_debug("trying mode %s width %d (at %d MHz)\n",
1855 mmc_mode_name(mwt->mode),
1856 bus_width(ecbw->cap),
1857 mmc_mode2freq(mmc, mwt->mode) / 1000000);
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001858 old_voltage = mmc->signal_voltage;
1859 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1860 MMC_ALL_SIGNAL_VOLTAGE);
1861 if (err)
1862 continue;
1863
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001864 /* configure the bus width (card + host) */
1865 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1866 EXT_CSD_BUS_WIDTH,
1867 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1868 if (err)
1869 goto error;
1870 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1871
1872 /* configure the bus speed (card) */
1873 err = mmc_set_card_speed(mmc, mwt->mode);
1874 if (err)
1875 goto error;
1876
1877 /*
1878 * configure the bus width AND the ddr mode (card)
1879 * The host side will be taken care of in the next step
1880 */
1881 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1882 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1883 EXT_CSD_BUS_WIDTH,
1884 ecbw->ext_csd_bits);
1885 if (err)
1886 goto error;
1887 }
1888
1889 /* configure the bus mode (host) */
1890 mmc_select_mode(mmc, mwt->mode);
Jaehoon Chung65117182018-01-26 19:25:29 +09001891 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001892#ifdef MMC_SUPPORTS_TUNING
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001893
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001894 /* execute tuning if needed */
1895 if (mwt->tuning) {
1896 err = mmc_execute_tuning(mmc, mwt->tuning);
1897 if (err) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09001898 pr_debug("tuning failed\n");
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001899 goto error;
1900 }
1901 }
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +01001902#endif
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +02001903
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001904 /* do a transfer to check the configuration */
1905 err = mmc_read_and_compare_ext_csd(mmc);
1906 if (!err)
1907 return 0;
1908error:
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +02001909 mmc_set_signal_voltage(mmc, old_voltage);
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001910 /* if an error occured, revert to a safer bus mode */
1911 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1912 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1913 mmc_select_mode(mmc, MMC_LEGACY);
1914 mmc_set_bus_width(mmc, 1);
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001915 }
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001916 }
1917
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01001918 pr_err("unable to select a mode\n");
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001919
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +02001920 return -ENOTSUPP;
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001921}
Marek Vasut62d77ce2018-04-15 00:37:11 +02001922#endif
1923
1924#if CONFIG_IS_ENABLED(MMC_TINY)
1925DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
1926#endif
Jean-Jacques Hiblot8ac8a262017-09-21 16:29:49 +02001927
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02001928static int mmc_startup_v4(struct mmc *mmc)
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02001929{
1930 int err, i;
1931 u64 capacity;
1932 bool has_parts = false;
1933 bool part_completed;
Jean-Jacques Hiblot58a6fb72018-01-04 15:23:31 +01001934 static const u32 mmc_versions[] = {
1935 MMC_VERSION_4,
1936 MMC_VERSION_4_1,
1937 MMC_VERSION_4_2,
1938 MMC_VERSION_4_3,
Jean-Jacques Hiblotace1bed2018-02-09 12:09:28 +01001939 MMC_VERSION_4_4,
Jean-Jacques Hiblot58a6fb72018-01-04 15:23:31 +01001940 MMC_VERSION_4_41,
1941 MMC_VERSION_4_5,
1942 MMC_VERSION_5_0,
1943 MMC_VERSION_5_1
1944 };
1945
Marek Vasut62d77ce2018-04-15 00:37:11 +02001946#if CONFIG_IS_ENABLED(MMC_TINY)
1947 u8 *ext_csd = ext_csd_bkup;
1948
1949 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
1950 return 0;
1951
1952 if (!mmc->ext_csd)
1953 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
1954
1955 err = mmc_send_ext_csd(mmc, ext_csd);
1956 if (err)
1957 goto error;
1958
1959 /* store the ext csd for future reference */
1960 if (!mmc->ext_csd)
1961 mmc->ext_csd = ext_csd;
1962#else
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01001963 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02001964
1965 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1966 return 0;
1967
1968 /* check ext_csd version and capacity */
1969 err = mmc_send_ext_csd(mmc, ext_csd);
1970 if (err)
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01001971 goto error;
1972
1973 /* store the ext csd for future reference */
1974 if (!mmc->ext_csd)
1975 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
1976 if (!mmc->ext_csd)
1977 return -ENOMEM;
1978 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
Marek Vasut62d77ce2018-04-15 00:37:11 +02001979#endif
Alexander Kochetkov76584e32018-02-20 14:35:55 +03001980 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
Jean-Jacques Hiblot58a6fb72018-01-04 15:23:31 +01001981 return -EINVAL;
1982
1983 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
1984
1985 if (mmc->version >= MMC_VERSION_4_2) {
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02001986 /*
1987 * According to the JEDEC Standard, the value of
1988 * ext_csd's capacity is valid if the value is more
1989 * than 2GB
1990 */
1991 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1992 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1993 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1994 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1995 capacity *= MMC_MAX_BLOCK_LEN;
1996 if ((capacity >> 20) > 2 * 1024)
1997 mmc->capacity_user = capacity;
1998 }
1999
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002000 /* The partition data may be non-zero but it is only
2001 * effective if PARTITION_SETTING_COMPLETED is set in
2002 * EXT_CSD, so ignore any data if this bit is not set,
2003 * except for enabling the high-capacity group size
2004 * definition (see below).
2005 */
2006 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2007 EXT_CSD_PARTITION_SETTING_COMPLETED);
2008
2009 /* store the partition info of emmc */
2010 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2011 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2012 ext_csd[EXT_CSD_BOOT_MULT])
2013 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2014 if (part_completed &&
2015 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2016 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2017
2018 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2019
2020 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2021
2022 for (i = 0; i < 4; i++) {
2023 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2024 uint mult = (ext_csd[idx + 2] << 16) +
2025 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2026 if (mult)
2027 has_parts = true;
2028 if (!part_completed)
2029 continue;
2030 mmc->capacity_gp[i] = mult;
2031 mmc->capacity_gp[i] *=
2032 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2033 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2034 mmc->capacity_gp[i] <<= 19;
2035 }
2036
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +01002037#ifndef CONFIG_SPL_BUILD
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002038 if (part_completed) {
2039 mmc->enh_user_size =
2040 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2041 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2042 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2043 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2044 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2045 mmc->enh_user_size <<= 19;
2046 mmc->enh_user_start =
2047 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2048 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2049 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2050 ext_csd[EXT_CSD_ENH_START_ADDR];
2051 if (mmc->high_capacity)
2052 mmc->enh_user_start <<= 9;
2053 }
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +01002054#endif
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002055
2056 /*
2057 * Host needs to enable ERASE_GRP_DEF bit if device is
2058 * partitioned. This bit will be lost every time after a reset
2059 * or power off. This will affect erase size.
2060 */
2061 if (part_completed)
2062 has_parts = true;
2063 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2064 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2065 has_parts = true;
2066 if (has_parts) {
2067 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2068 EXT_CSD_ERASE_GROUP_DEF, 1);
2069
2070 if (err)
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002071 goto error;
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002072
2073 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2074 }
2075
2076 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002077#if CONFIG_IS_ENABLED(MMC_WRITE)
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002078 /* Read out group size from ext_csd */
2079 mmc->erase_grp_size =
2080 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002081#endif
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002082 /*
2083 * if high capacity and partition setting completed
2084 * SEC_COUNT is valid even if it is smaller than 2 GiB
2085 * JEDEC Standard JESD84-B45, 6.2.4
2086 */
2087 if (mmc->high_capacity && part_completed) {
2088 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2089 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2090 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2091 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2092 capacity *= MMC_MAX_BLOCK_LEN;
2093 mmc->capacity_user = capacity;
2094 }
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002095 }
2096#if CONFIG_IS_ENABLED(MMC_WRITE)
2097 else {
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002098 /* Calculate the group size from the csd value. */
2099 int erase_gsz, erase_gmul;
2100
2101 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2102 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2103 mmc->erase_grp_size = (erase_gsz + 1)
2104 * (erase_gmul + 1);
2105 }
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002106#endif
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +01002107#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002108 mmc->hc_wp_grp_size = 1024
2109 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2110 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +01002111#endif
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002112
2113 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2114
2115 return 0;
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002116error:
2117 if (mmc->ext_csd) {
Marek Vasut62d77ce2018-04-15 00:37:11 +02002118#if !CONFIG_IS_ENABLED(MMC_TINY)
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002119 free(mmc->ext_csd);
Marek Vasut62d77ce2018-04-15 00:37:11 +02002120#endif
Jean-Jacques Hiblotf7d5dff2017-11-30 17:43:59 +01002121 mmc->ext_csd = NULL;
2122 }
2123 return err;
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002124}
2125
Kim Phillipsfdbb8732012-10-29 13:34:43 +00002126static int mmc_startup(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05002127{
Stephen Warrenf866a462013-06-11 15:14:01 -06002128 int err, i;
Andy Fleming272cc702008-10-30 16:41:01 -05002129 uint mult, freq;
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002130 u64 cmult, csize;
Andy Fleming272cc702008-10-30 16:41:01 -05002131 struct mmc_cmd cmd;
Simon Glassc40fdca2016-05-01 13:52:35 -06002132 struct blk_desc *bdesc;
Andy Fleming272cc702008-10-30 16:41:01 -05002133
Thomas Choud52ebf12010-12-24 13:12:21 +00002134#ifdef CONFIG_MMC_SPI_CRC_ON
2135 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2136 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2137 cmd.resp_type = MMC_RSP_R1;
2138 cmd.cmdarg = 1;
Thomas Choud52ebf12010-12-24 13:12:21 +00002139 err = mmc_send_cmd(mmc, &cmd, NULL);
Thomas Choud52ebf12010-12-24 13:12:21 +00002140 if (err)
2141 return err;
2142 }
2143#endif
2144
Andy Fleming272cc702008-10-30 16:41:01 -05002145 /* Put the Card in Identify Mode */
Thomas Choud52ebf12010-12-24 13:12:21 +00002146 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2147 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
Andy Fleming272cc702008-10-30 16:41:01 -05002148 cmd.resp_type = MMC_RSP_R2;
2149 cmd.cmdarg = 0;
Andy Fleming272cc702008-10-30 16:41:01 -05002150
2151 err = mmc_send_cmd(mmc, &cmd, NULL);
2152
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +02002153#ifdef CONFIG_MMC_QUIRKS
2154 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2155 int retries = 4;
2156 /*
2157 * It has been seen that SEND_CID may fail on the first
2158 * attempt, let's try a few more time
2159 */
2160 do {
2161 err = mmc_send_cmd(mmc, &cmd, NULL);
2162 if (!err)
2163 break;
2164 } while (retries--);
2165 }
2166#endif
2167
Andy Fleming272cc702008-10-30 16:41:01 -05002168 if (err)
2169 return err;
2170
2171 memcpy(mmc->cid, cmd.response, 16);
2172
2173 /*
2174 * For MMC cards, set the Relative Address.
2175 * For SD cards, get the Relatvie Address.
2176 * This also puts the cards into Standby State
2177 */
Thomas Choud52ebf12010-12-24 13:12:21 +00002178 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2179 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2180 cmd.cmdarg = mmc->rca << 16;
2181 cmd.resp_type = MMC_RSP_R6;
Andy Fleming272cc702008-10-30 16:41:01 -05002182
Thomas Choud52ebf12010-12-24 13:12:21 +00002183 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Fleming272cc702008-10-30 16:41:01 -05002184
Thomas Choud52ebf12010-12-24 13:12:21 +00002185 if (err)
2186 return err;
Andy Fleming272cc702008-10-30 16:41:01 -05002187
Thomas Choud52ebf12010-12-24 13:12:21 +00002188 if (IS_SD(mmc))
2189 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2190 }
Andy Fleming272cc702008-10-30 16:41:01 -05002191
2192 /* Get the Card-Specific Data */
2193 cmd.cmdidx = MMC_CMD_SEND_CSD;
2194 cmd.resp_type = MMC_RSP_R2;
2195 cmd.cmdarg = mmc->rca << 16;
Andy Fleming272cc702008-10-30 16:41:01 -05002196
2197 err = mmc_send_cmd(mmc, &cmd, NULL);
2198
2199 if (err)
2200 return err;
2201
Rabin Vincent998be3d2009-04-05 13:30:56 +05302202 mmc->csd[0] = cmd.response[0];
2203 mmc->csd[1] = cmd.response[1];
2204 mmc->csd[2] = cmd.response[2];
2205 mmc->csd[3] = cmd.response[3];
Andy Fleming272cc702008-10-30 16:41:01 -05002206
2207 if (mmc->version == MMC_VERSION_UNKNOWN) {
Rabin Vincent0b453ff2009-04-05 13:30:55 +05302208 int version = (cmd.response[0] >> 26) & 0xf;
Andy Fleming272cc702008-10-30 16:41:01 -05002209
2210 switch (version) {
Bin Meng53e8e402016-03-17 21:53:13 -07002211 case 0:
2212 mmc->version = MMC_VERSION_1_2;
2213 break;
2214 case 1:
2215 mmc->version = MMC_VERSION_1_4;
2216 break;
2217 case 2:
2218 mmc->version = MMC_VERSION_2_2;
2219 break;
2220 case 3:
2221 mmc->version = MMC_VERSION_3;
2222 break;
2223 case 4:
2224 mmc->version = MMC_VERSION_4;
2225 break;
2226 default:
2227 mmc->version = MMC_VERSION_1_2;
2228 break;
Andy Fleming272cc702008-10-30 16:41:01 -05002229 }
2230 }
2231
2232 /* divide frequency by 10, since the mults are 10x bigger */
Rabin Vincent0b453ff2009-04-05 13:30:55 +05302233 freq = fbase[(cmd.response[0] & 0x7)];
2234 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
Andy Fleming272cc702008-10-30 16:41:01 -05002235
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +02002236 mmc->legacy_speed = freq * mult;
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +02002237 mmc_select_mode(mmc, MMC_LEGACY);
Andy Fleming272cc702008-10-30 16:41:01 -05002238
Markus Niebelab711882013-12-16 13:40:46 +01002239 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
Rabin Vincent998be3d2009-04-05 13:30:56 +05302240 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002241#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Fleming272cc702008-10-30 16:41:01 -05002242
2243 if (IS_SD(mmc))
2244 mmc->write_bl_len = mmc->read_bl_len;
2245 else
Rabin Vincent998be3d2009-04-05 13:30:56 +05302246 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002247#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002248
2249 if (mmc->high_capacity) {
2250 csize = (mmc->csd[1] & 0x3f) << 16
2251 | (mmc->csd[2] & 0xffff0000) >> 16;
2252 cmult = 8;
2253 } else {
2254 csize = (mmc->csd[1] & 0x3ff) << 2
2255 | (mmc->csd[2] & 0xc0000000) >> 30;
2256 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2257 }
2258
Stephen Warrenf866a462013-06-11 15:14:01 -06002259 mmc->capacity_user = (csize + 1) << (cmult + 2);
2260 mmc->capacity_user *= mmc->read_bl_len;
2261 mmc->capacity_boot = 0;
2262 mmc->capacity_rpmb = 0;
2263 for (i = 0; i < 4; i++)
2264 mmc->capacity_gp[i] = 0;
Andy Fleming272cc702008-10-30 16:41:01 -05002265
Simon Glass8bfa1952013-04-03 08:54:30 +00002266 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2267 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Andy Fleming272cc702008-10-30 16:41:01 -05002268
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002269#if CONFIG_IS_ENABLED(MMC_WRITE)
Simon Glass8bfa1952013-04-03 08:54:30 +00002270 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2271 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002272#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002273
Markus Niebelab711882013-12-16 13:40:46 +01002274 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2275 cmd.cmdidx = MMC_CMD_SET_DSR;
2276 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2277 cmd.resp_type = MMC_RSP_NONE;
2278 if (mmc_send_cmd(mmc, &cmd, NULL))
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002279 pr_warn("MMC: SET_DSR failed\n");
Markus Niebelab711882013-12-16 13:40:46 +01002280 }
2281
Andy Fleming272cc702008-10-30 16:41:01 -05002282 /* Select the card, and put it into Transfer Mode */
Thomas Choud52ebf12010-12-24 13:12:21 +00002283 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2284 cmd.cmdidx = MMC_CMD_SELECT_CARD;
Ajay Bhargavfe8f7062011-10-05 03:13:23 +00002285 cmd.resp_type = MMC_RSP_R1;
Thomas Choud52ebf12010-12-24 13:12:21 +00002286 cmd.cmdarg = mmc->rca << 16;
Thomas Choud52ebf12010-12-24 13:12:21 +00002287 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Fleming272cc702008-10-30 16:41:01 -05002288
Thomas Choud52ebf12010-12-24 13:12:21 +00002289 if (err)
2290 return err;
2291 }
Andy Fleming272cc702008-10-30 16:41:01 -05002292
Lei Wene6f99a52011-06-22 17:03:31 +00002293 /*
2294 * For SD, its erase group is always one sector
2295 */
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002296#if CONFIG_IS_ENABLED(MMC_WRITE)
Lei Wene6f99a52011-06-22 17:03:31 +00002297 mmc->erase_grp_size = 1;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002298#endif
Lei Wenbc897b12011-05-02 16:26:26 +00002299 mmc->part_config = MMCPART_NOAVAILABLE;
Lei Wenbc897b12011-05-02 16:26:26 +00002300
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +02002301 err = mmc_startup_v4(mmc);
Jean-Jacques Hiblotc744b6f2017-09-21 16:29:50 +02002302 if (err)
2303 return err;
Sukumar Ghoraid23e2c02010-09-20 18:29:29 +05302304
Simon Glassc40fdca2016-05-01 13:52:35 -06002305 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
Stephen Warrenf866a462013-06-11 15:14:01 -06002306 if (err)
2307 return err;
2308
Marek Vasut62d77ce2018-04-15 00:37:11 +02002309#if CONFIG_IS_ENABLED(MMC_TINY)
2310 mmc_set_clock(mmc, mmc->legacy_speed, false);
2311 mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2312 mmc_set_bus_width(mmc, 1);
2313#else
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02002314 if (IS_SD(mmc)) {
2315 err = sd_get_capabilities(mmc);
2316 if (err)
2317 return err;
2318 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2319 } else {
2320 err = mmc_get_capabilities(mmc);
2321 if (err)
2322 return err;
2323 mmc_select_mode_and_width(mmc, mmc->card_caps);
2324 }
Marek Vasut62d77ce2018-04-15 00:37:11 +02002325#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002326 if (err)
2327 return err;
2328
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +02002329 mmc->best_mode = mmc->selected_mode;
Jaehoon Chungad5fd922012-03-26 21:16:03 +00002330
Andrew Gabbasov5af8f452014-12-01 06:59:11 -06002331 /* Fix the block length for DDR mode */
2332 if (mmc->ddr_mode) {
2333 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002334#if CONFIG_IS_ENABLED(MMC_WRITE)
Andrew Gabbasov5af8f452014-12-01 06:59:11 -06002335 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +01002336#endif
Andrew Gabbasov5af8f452014-12-01 06:59:11 -06002337 }
2338
Andy Fleming272cc702008-10-30 16:41:01 -05002339 /* fill in device description */
Simon Glassc40fdca2016-05-01 13:52:35 -06002340 bdesc = mmc_get_blk_desc(mmc);
2341 bdesc->lun = 0;
2342 bdesc->hwpart = 0;
2343 bdesc->type = 0;
2344 bdesc->blksz = mmc->read_bl_len;
2345 bdesc->log2blksz = LOG2(bdesc->blksz);
2346 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Sjoerd Simonsfc011f62015-12-04 23:27:40 +01002347#if !defined(CONFIG_SPL_BUILD) || \
2348 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2349 !defined(CONFIG_USE_TINY_PRINTF))
Simon Glassc40fdca2016-05-01 13:52:35 -06002350 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
Taylor Huttbabce5f2012-10-20 17:15:59 +00002351 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2352 (mmc->cid[3] >> 16) & 0xffff);
Simon Glassc40fdca2016-05-01 13:52:35 -06002353 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
Taylor Huttbabce5f2012-10-20 17:15:59 +00002354 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2355 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2356 (mmc->cid[2] >> 24) & 0xff);
Simon Glassc40fdca2016-05-01 13:52:35 -06002357 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
Taylor Huttbabce5f2012-10-20 17:15:59 +00002358 (mmc->cid[2] >> 16) & 0xf);
Paul Burton56196822013-09-04 16:12:25 +01002359#else
Simon Glassc40fdca2016-05-01 13:52:35 -06002360 bdesc->vendor[0] = 0;
2361 bdesc->product[0] = 0;
2362 bdesc->revision[0] = 0;
Paul Burton56196822013-09-04 16:12:25 +01002363#endif
Mikhail Kshevetskiy122efd42012-07-09 08:53:38 +00002364#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
Simon Glassc40fdca2016-05-01 13:52:35 -06002365 part_init(bdesc);
Mikhail Kshevetskiy122efd42012-07-09 08:53:38 +00002366#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002367
2368 return 0;
2369}
2370
Kim Phillipsfdbb8732012-10-29 13:34:43 +00002371static int mmc_send_if_cond(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05002372{
2373 struct mmc_cmd cmd;
2374 int err;
2375
2376 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2377 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02002378 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
Andy Fleming272cc702008-10-30 16:41:01 -05002379 cmd.resp_type = MMC_RSP_R7;
Andy Fleming272cc702008-10-30 16:41:01 -05002380
2381 err = mmc_send_cmd(mmc, &cmd, NULL);
2382
2383 if (err)
2384 return err;
2385
Rabin Vincent998be3d2009-04-05 13:30:56 +05302386 if ((cmd.response[0] & 0xff) != 0xaa)
Jaehoon Chung915ffa52016-07-19 16:33:36 +09002387 return -EOPNOTSUPP;
Andy Fleming272cc702008-10-30 16:41:01 -05002388 else
2389 mmc->version = SD_VERSION_2;
2390
2391 return 0;
2392}
2393
Simon Glassc4d660d2017-07-04 13:31:19 -06002394#if !CONFIG_IS_ENABLED(DM_MMC)
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +01002395/* board-specific MMC power initializations. */
2396__weak void board_mmc_power_init(void)
2397{
2398}
Simon Glass05cbeb72017-04-22 19:10:56 -06002399#endif
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +01002400
Peng Fan2051aef2016-10-11 15:08:43 +08002401static int mmc_power_init(struct mmc *mmc)
2402{
Simon Glassc4d660d2017-07-04 13:31:19 -06002403#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +02002404#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan2051aef2016-10-11 15:08:43 +08002405 int ret;
2406
2407 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +02002408 &mmc->vmmc_supply);
2409 if (ret)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002410 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
Peng Fan2051aef2016-10-11 15:08:43 +08002411
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +02002412 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2413 &mmc->vqmmc_supply);
2414 if (ret)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002415 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
Peng Fan2051aef2016-10-11 15:08:43 +08002416#endif
Simon Glass05cbeb72017-04-22 19:10:56 -06002417#else /* !CONFIG_DM_MMC */
2418 /*
2419 * Driver model should use a regulator, as above, rather than calling
2420 * out to board code.
2421 */
2422 board_mmc_power_init();
2423#endif
Peng Fan2051aef2016-10-11 15:08:43 +08002424 return 0;
2425}
2426
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002427/*
2428 * put the host in the initial state:
2429 * - turn on Vdd (card power supply)
2430 * - configure the bus width and clock to minimal values
2431 */
2432static void mmc_set_initial_state(struct mmc *mmc)
2433{
2434 int err;
2435
2436 /* First try to set 3.3V. If it fails set to 1.8V */
2437 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2438 if (err != 0)
2439 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2440 if (err != 0)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002441 pr_warn("mmc: failed to set signal voltage\n");
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002442
2443 mmc_select_mode(mmc, MMC_LEGACY);
2444 mmc_set_bus_width(mmc, 1);
Jaehoon Chung65117182018-01-26 19:25:29 +09002445 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002446}
2447
2448static int mmc_power_on(struct mmc *mmc)
2449{
2450#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2451 if (mmc->vmmc_supply) {
2452 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2453
2454 if (ret) {
2455 puts("Error enabling VMMC supply\n");
2456 return ret;
2457 }
2458 }
2459#endif
2460 return 0;
2461}
2462
2463static int mmc_power_off(struct mmc *mmc)
2464{
Jaehoon Chung65117182018-01-26 19:25:29 +09002465 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002466#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2467 if (mmc->vmmc_supply) {
2468 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2469
2470 if (ret) {
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002471 pr_debug("Error disabling VMMC supply\n");
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002472 return ret;
2473 }
2474 }
2475#endif
2476 return 0;
2477}
2478
2479static int mmc_power_cycle(struct mmc *mmc)
2480{
2481 int ret;
2482
2483 ret = mmc_power_off(mmc);
2484 if (ret)
2485 return ret;
2486 /*
2487 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2488 * to be on the safer side.
2489 */
2490 udelay(2000);
2491 return mmc_power_on(mmc);
2492}
2493
Jon Nettleton6c09eba2018-06-11 15:26:19 +03002494int mmc_get_op_cond(struct mmc *mmc)
Andy Fleming272cc702008-10-30 16:41:01 -05002495{
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02002496 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
Macpaul Linafd59322011-11-14 23:35:39 +00002497 int err;
Andy Fleming272cc702008-10-30 16:41:01 -05002498
Lei Wenbc897b12011-05-02 16:26:26 +00002499 if (mmc->has_init)
2500 return 0;
2501
Yangbo Lu5a8dbdc2015-04-22 13:57:00 +08002502#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2503 mmc_adapter_card_type_ident();
2504#endif
Peng Fan2051aef2016-10-11 15:08:43 +08002505 err = mmc_power_init(mmc);
2506 if (err)
2507 return err;
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +01002508
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +02002509#ifdef CONFIG_MMC_QUIRKS
2510 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2511 MMC_QUIRK_RETRY_SEND_CID;
2512#endif
2513
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +02002514 err = mmc_power_cycle(mmc);
2515 if (err) {
2516 /*
2517 * if power cycling is not supported, we should not try
2518 * to use the UHS modes, because we wouldn't be able to
2519 * recover from an error during the UHS initialization.
2520 */
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002521 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +02002522 uhs_en = false;
2523 mmc->host_caps &= ~UHS_CAPS;
2524 err = mmc_power_on(mmc);
2525 }
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002526 if (err)
2527 return err;
2528
Simon Glasse7881d82017-07-29 11:35:31 -06002529#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass8ca51e52016-06-12 23:30:22 -06002530 /* The device has already been probed ready for use */
2531#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +02002532 /* made sure it's not NULL earlier */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02002533 err = mmc->cfg->ops->init(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05002534 if (err)
2535 return err;
Simon Glass8ca51e52016-06-12 23:30:22 -06002536#endif
Andrew Gabbasov786e8f82014-12-01 06:59:09 -06002537 mmc->ddr_mode = 0;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +02002538
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02002539retry:
Kishon Vijay Abraham Ifb7c3be2017-09-21 16:30:02 +02002540 mmc_set_initial_state(mmc);
Jean-Jacques Hiblot318a7a52017-09-21 16:30:01 +02002541 mmc_send_init_stream(mmc);
2542
Andy Fleming272cc702008-10-30 16:41:01 -05002543 /* Reset the Card */
2544 err = mmc_go_idle(mmc);
2545
2546 if (err)
2547 return err;
2548
Lei Wenbc897b12011-05-02 16:26:26 +00002549 /* The internal partition reset to user partition(0) at every CMD0*/
Simon Glassc40fdca2016-05-01 13:52:35 -06002550 mmc_get_blk_desc(mmc)->hwpart = 0;
Lei Wenbc897b12011-05-02 16:26:26 +00002551
Andy Fleming272cc702008-10-30 16:41:01 -05002552 /* Test for SD version 2 */
Macpaul Linafd59322011-11-14 23:35:39 +00002553 err = mmc_send_if_cond(mmc);
Andy Fleming272cc702008-10-30 16:41:01 -05002554
Andy Fleming272cc702008-10-30 16:41:01 -05002555 /* Now try to get the SD card's operating condition */
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +02002556 err = sd_send_op_cond(mmc, uhs_en);
2557 if (err && uhs_en) {
2558 uhs_en = false;
2559 mmc_power_cycle(mmc);
2560 goto retry;
2561 }
Andy Fleming272cc702008-10-30 16:41:01 -05002562
2563 /* If the command timed out, we check for an MMC card */
Jaehoon Chung915ffa52016-07-19 16:33:36 +09002564 if (err == -ETIMEDOUT) {
Andy Fleming272cc702008-10-30 16:41:01 -05002565 err = mmc_send_op_cond(mmc);
2566
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002567 if (err) {
Paul Burton56196822013-09-04 16:12:25 +01002568#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002569 pr_err("Card did not respond to voltage select!\n");
Paul Burton56196822013-09-04 16:12:25 +01002570#endif
Jaehoon Chung915ffa52016-07-19 16:33:36 +09002571 return -EOPNOTSUPP;
Andy Fleming272cc702008-10-30 16:41:01 -05002572 }
2573 }
2574
Jon Nettleton6c09eba2018-06-11 15:26:19 +03002575 return err;
2576}
2577
2578int mmc_start_init(struct mmc *mmc)
2579{
2580 bool no_card;
2581 int err = 0;
2582
2583 /*
2584 * all hosts are capable of 1 bit bus-width and able to use the legacy
2585 * timings.
2586 */
2587 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2588 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2589
2590#if !defined(CONFIG_MMC_BROKEN_CD)
2591 /* we pretend there's no card when init is NULL */
2592 no_card = mmc_getcd(mmc) == 0;
2593#else
2594 no_card = 0;
2595#endif
2596#if !CONFIG_IS_ENABLED(DM_MMC)
2597 no_card = no_card || (mmc->cfg->ops->init == NULL);
2598#endif
2599 if (no_card) {
2600 mmc->has_init = 0;
2601#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2602 pr_err("MMC: no card present\n");
2603#endif
2604 return -ENOMEDIUM;
2605 }
2606
2607 err = mmc_get_op_cond(mmc);
2608
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002609 if (!err)
Che-Liang Chioue9550442012-11-28 15:21:13 +00002610 mmc->init_in_progress = 1;
2611
2612 return err;
2613}
2614
2615static int mmc_complete_init(struct mmc *mmc)
2616{
2617 int err = 0;
2618
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002619 mmc->init_in_progress = 0;
Che-Liang Chioue9550442012-11-28 15:21:13 +00002620 if (mmc->op_cond_pending)
2621 err = mmc_complete_op_cond(mmc);
2622
2623 if (!err)
2624 err = mmc_startup(mmc);
Lei Wenbc897b12011-05-02 16:26:26 +00002625 if (err)
2626 mmc->has_init = 0;
2627 else
2628 mmc->has_init = 1;
Che-Liang Chioue9550442012-11-28 15:21:13 +00002629 return err;
2630}
2631
2632int mmc_init(struct mmc *mmc)
2633{
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002634 int err = 0;
Vipul Kumar36332b62018-05-03 12:20:54 +05302635 __maybe_unused ulong start;
Simon Glassc4d660d2017-07-04 13:31:19 -06002636#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass33fb2112016-05-01 13:52:41 -06002637 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
Che-Liang Chioue9550442012-11-28 15:21:13 +00002638
Simon Glass33fb2112016-05-01 13:52:41 -06002639 upriv->mmc = mmc;
2640#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +00002641 if (mmc->has_init)
2642 return 0;
Mateusz Zalegad803fea2014-04-29 20:15:30 +02002643
2644 start = get_timer(0);
2645
Che-Liang Chioue9550442012-11-28 15:21:13 +00002646 if (!mmc->init_in_progress)
2647 err = mmc_start_init(mmc);
2648
Andrew Gabbasovbd47c132015-03-19 07:44:07 -05002649 if (!err)
Che-Liang Chioue9550442012-11-28 15:21:13 +00002650 err = mmc_complete_init(mmc);
Jagan Teki919b4852017-01-10 11:18:43 +01002651 if (err)
Masahiro Yamadad4d64882018-01-28 19:11:42 +09002652 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
Jagan Teki919b4852017-01-10 11:18:43 +01002653
Lei Wenbc897b12011-05-02 16:26:26 +00002654 return err;
Andy Fleming272cc702008-10-30 16:41:01 -05002655}
2656
Markus Niebelab711882013-12-16 13:40:46 +01002657int mmc_set_dsr(struct mmc *mmc, u16 val)
2658{
2659 mmc->dsr = val;
2660 return 0;
2661}
2662
Jeroen Hofsteecee9ab72014-07-10 22:46:28 +02002663/* CPU-specific MMC initializations */
2664__weak int cpu_mmc_init(bd_t *bis)
Andy Fleming272cc702008-10-30 16:41:01 -05002665{
2666 return -1;
2667}
2668
Jeroen Hofsteecee9ab72014-07-10 22:46:28 +02002669/* board-specific MMC initializations. */
2670__weak int board_mmc_init(bd_t *bis)
2671{
2672 return -1;
2673}
Andy Fleming272cc702008-10-30 16:41:01 -05002674
Che-Liang Chioue9550442012-11-28 15:21:13 +00002675void mmc_set_preinit(struct mmc *mmc, int preinit)
2676{
2677 mmc->preinit = preinit;
2678}
2679
Faiz Abbas8a856db2018-02-12 19:35:24 +05302680#if CONFIG_IS_ENABLED(DM_MMC)
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002681static int mmc_probe(bd_t *bis)
2682{
Simon Glass4a1db6d2015-12-29 05:22:49 -07002683 int ret, i;
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002684 struct uclass *uc;
Simon Glass4a1db6d2015-12-29 05:22:49 -07002685 struct udevice *dev;
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002686
2687 ret = uclass_get(UCLASS_MMC, &uc);
2688 if (ret)
2689 return ret;
2690
Simon Glass4a1db6d2015-12-29 05:22:49 -07002691 /*
2692 * Try to add them in sequence order. Really with driver model we
2693 * should allow holes, but the current MMC list does not allow that.
2694 * So if we request 0, 1, 3 we will get 0, 1, 2.
2695 */
2696 for (i = 0; ; i++) {
2697 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2698 if (ret == -ENODEV)
2699 break;
2700 }
2701 uclass_foreach_dev(dev, uc) {
2702 ret = device_probe(dev);
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002703 if (ret)
Jean-Jacques Hiblotd8e3d422017-11-30 17:44:00 +01002704 pr_err("%s - probe failed: %d\n", dev->name, ret);
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002705 }
2706
2707 return 0;
2708}
2709#else
2710static int mmc_probe(bd_t *bis)
2711{
2712 if (board_mmc_init(bis) < 0)
2713 cpu_mmc_init(bis);
2714
2715 return 0;
2716}
2717#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +00002718
Andy Fleming272cc702008-10-30 16:41:01 -05002719int mmc_initialize(bd_t *bis)
2720{
Daniel Kochmański1b26bab2015-05-29 16:55:43 +02002721 static int initialized = 0;
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002722 int ret;
Daniel Kochmański1b26bab2015-05-29 16:55:43 +02002723 if (initialized) /* Avoid initializing mmc multiple times */
2724 return 0;
2725 initialized = 1;
2726
Simon Glassc4d660d2017-07-04 13:31:19 -06002727#if !CONFIG_IS_ENABLED(BLK)
Marek Vasutb5b838f2016-12-01 02:06:33 +01002728#if !CONFIG_IS_ENABLED(MMC_TINY)
Simon Glassc40fdca2016-05-01 13:52:35 -06002729 mmc_list_init();
2730#endif
Marek Vasutb5b838f2016-12-01 02:06:33 +01002731#endif
Sjoerd Simons8e3332e2015-08-30 16:55:45 -06002732 ret = mmc_probe(bis);
2733 if (ret)
2734 return ret;
Andy Fleming272cc702008-10-30 16:41:01 -05002735
Ying Zhangbb0dc102013-08-16 15:16:11 +08002736#ifndef CONFIG_SPL_BUILD
Andy Fleming272cc702008-10-30 16:41:01 -05002737 print_mmc_devices(',');
Ying Zhangbb0dc102013-08-16 15:16:11 +08002738#endif
Andy Fleming272cc702008-10-30 16:41:01 -05002739
Simon Glassc40fdca2016-05-01 13:52:35 -06002740 mmc_do_preinit();
Andy Fleming272cc702008-10-30 16:41:01 -05002741 return 0;
2742}
Tomas Melincd3d4882016-11-25 11:01:03 +02002743
2744#ifdef CONFIG_CMD_BKOPS_ENABLE
2745int mmc_set_bkops_enable(struct mmc *mmc)
2746{
2747 int err;
2748 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2749
2750 err = mmc_send_ext_csd(mmc, ext_csd);
2751 if (err) {
2752 puts("Could not get ext_csd register values\n");
2753 return err;
2754 }
2755
2756 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2757 puts("Background operations not supported on device\n");
2758 return -EMEDIUMTYPE;
2759 }
2760
2761 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2762 puts("Background operations already enabled\n");
2763 return 0;
2764 }
2765
2766 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2767 if (err) {
2768 puts("Failed to enable manual background operations\n");
2769 return err;
2770 }
2771
2772 puts("Enabled manual background operations\n");
2773
2774 return 0;
2775}
2776#endif