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Bin Meng117a4332018-09-26 06:55:06 -07001menu "RISC-V architecture"
Rick Chenf94c44e2017-12-26 13:55:52 +08002 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
Rick Chen6f4dd622018-05-29 09:54:40 +080011config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
Rick Chenf94c44e2017-12-26 13:55:52 +080013
Bin Meng510e3792018-09-26 06:55:21 -070014config TARGET_QEMU_VIRT
15 bool "Support QEMU Virt Board"
16
Rick Chenf94c44e2017-12-26 13:55:52 +080017endchoice
18
Rick Chen52923c62018-11-07 09:34:06 +080019# board-specific options below
Rick Chen6f4dd622018-05-29 09:54:40 +080020source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng510e3792018-09-26 06:55:21 -070021source "board/emulation/qemu-riscv/Kconfig"
Rick Chenf94c44e2017-12-26 13:55:52 +080022
Rick Chen52923c62018-11-07 09:34:06 +080023# platform-specific options below
24source "arch/riscv/cpu/ax25/Kconfig"
Bin Meng84304d42018-12-12 06:12:32 -080025source "arch/riscv/cpu/qemu/Kconfig"
Rick Chen52923c62018-11-07 09:34:06 +080026
27# architecture-specific options below
28
Rick Chenf94c44e2017-12-26 13:55:52 +080029choice
Lukas Auer862e2e72018-11-22 11:26:12 +010030 prompt "Base ISA"
31 default ARCH_RV32I
Rick Chenf94c44e2017-12-26 13:55:52 +080032
Lukas Auer862e2e72018-11-22 11:26:12 +010033config ARCH_RV32I
34 bool "RV32I"
Rick Chenf94c44e2017-12-26 13:55:52 +080035 select 32BIT
36 help
Lukas Auer862e2e72018-11-22 11:26:12 +010037 Choose this option to target the RV32I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +080038
Lukas Auer862e2e72018-11-22 11:26:12 +010039config ARCH_RV64I
40 bool "RV64I"
Rick Chenf94c44e2017-12-26 13:55:52 +080041 select 64BIT
Lukas Auer71158562018-11-22 11:26:13 +010042 select PHYS_64BIT
Rick Chenf94c44e2017-12-26 13:55:52 +080043 help
Lukas Auer862e2e72018-11-22 11:26:12 +010044 Choose this option to target the RV64I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +080045
46endchoice
47
Lukas Auer8176ea42018-12-12 06:12:23 -080048choice
49 prompt "Code Model"
50 default CMODEL_MEDLOW
51
52config CMODEL_MEDLOW
53 bool "medium low code model"
54 help
55 U-Boot and its statically defined symbols must lie within a single 2 GiB
56 address range and must lie between absolute addresses -2 GiB and +2 GiB.
57
58config CMODEL_MEDANY
59 bool "medium any code model"
60 help
61 U-Boot and its statically defined symbols must be within any single 2 GiB
62 address range.
63
64endchoice
65
Anup Patel3cfc8252018-12-12 06:12:29 -080066choice
67 prompt "Run Mode"
68 default RISCV_MMODE
69
70config RISCV_MMODE
71 bool "Machine"
72 help
73 Choose this option to build U-Boot for RISC-V M-Mode.
74
75config RISCV_SMODE
76 bool "Supervisor"
77 help
78 Choose this option to build U-Boot for RISC-V S-Mode.
79
80endchoice
81
Lukas Auerd57ffa62018-11-22 11:26:14 +010082config RISCV_ISA_C
83 bool "Emit compressed instructions"
84 default y
85 help
86 Adds "C" to the ISA subsets that the toolchain is allowed to emit
87 when building U-Boot, which results in compressed instructions in the
88 U-Boot binary.
89
90config RISCV_ISA_A
91 def_bool y
92
Rick Chenf94c44e2017-12-26 13:55:52 +080093config 32BIT
94 bool
95
96config 64BIT
97 bool
98
Bin Meng644a3cd2018-12-12 06:12:30 -080099config SIFIVE_CLINT
100 bool
101 depends on RISCV_MMODE
102 select REGMAP
103 select SYSCON
104 help
105 The SiFive CLINT block holds memory-mapped control and status registers
106 associated with software and timer interrupts.
107
Anup Patel511107d2018-12-12 06:12:31 -0800108config RISCV_RDTIME
109 bool
110 default y if RISCV_SMODE
111 help
112 The provides the riscv_get_time() API that is implemented using the
113 standard rdtime instruction. This is the case for S-mode U-Boot, and
114 is useful for processors that support rdtime in M-mode too.
115
Bin Meng92b64fe2018-12-12 06:12:33 -0800116config SYS_MALLOC_F_LEN
117 default 0x1000
118
Rick Chenf94c44e2017-12-26 13:55:52 +0800119endmenu