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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenke35745b2004-04-18 23:32:11 +00005 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
wdenk945af8d2003-07-16 21:53:01 +00008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
wdenk96e48cf2003-08-05 18:22:44 +000029#include <pci.h>
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020030#include <asm/processor.h>
wdenk945af8d2003-07-16 21:53:01 +000031
Stefan Roesee59581c2006-11-28 17:55:49 +010032#if defined(CONFIG_OF_FLAT_TREE)
33#include <ft_build.h>
34#endif
35
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010036#if defined(CONFIG_LITE5200B)
37#include "mt46v32m16.h"
wdenke35745b2004-04-18 23:32:11 +000038#else
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010039# if defined(CONFIG_MPC5200_DDR)
40# include "mt46v16m16-75.h"
41# else
wdenke35745b2004-04-18 23:32:11 +000042#include "mt48lc16m16a2-75.h"
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010043# endif
wdenke35745b2004-04-18 23:32:11 +000044#endif
wdenkd94f92c2003-08-28 09:41:22 +000045#ifndef CFG_RAMBOOT
wdenke0ac62d2003-08-17 18:55:18 +000046static void sdram_start (int hi_addr)
47{
48 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
49
wdenkb2001f22003-12-20 22:45:10 +000050 /* unlock mode register */
wdenke35745b2004-04-18 23:32:11 +000051 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
52 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +000053
wdenkb2001f22003-12-20 22:45:10 +000054 /* precharge all banks */
wdenke35745b2004-04-18 23:32:11 +000055 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
56 __asm__ volatile ("sync");
57
58#if SDRAM_DDR
wdenkb2001f22003-12-20 22:45:10 +000059 /* set mode register: extended mode */
wdenke35745b2004-04-18 23:32:11 +000060 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
61 __asm__ volatile ("sync");
62
wdenkb2001f22003-12-20 22:45:10 +000063 /* set mode register: reset DLL */
wdenke35745b2004-04-18 23:32:11 +000064 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
65 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +000066#endif
wdenke35745b2004-04-18 23:32:11 +000067
68 /* precharge all banks */
69 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
70 __asm__ volatile ("sync");
71
wdenkf8d813e2004-03-02 14:05:39 +000072 /* auto refresh */
wdenke35745b2004-04-18 23:32:11 +000073 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
74 __asm__ volatile ("sync");
75
wdenke0ac62d2003-08-17 18:55:18 +000076 /* set mode register */
wdenke35745b2004-04-18 23:32:11 +000077 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
78 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +000079
wdenke0ac62d2003-08-17 18:55:18 +000080 /* normal operation */
wdenke35745b2004-04-18 23:32:11 +000081 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
82 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +000083}
wdenkd94f92c2003-08-28 09:41:22 +000084#endif
wdenke0ac62d2003-08-17 18:55:18 +000085
wdenke35745b2004-04-18 23:32:11 +000086/*
87 * ATTENTION: Although partially referenced initdram does NOT make real use
88 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
89 * is something else than 0x00000000.
90 */
91
92#if defined(CONFIG_MPC5200)
wdenk945af8d2003-07-16 21:53:01 +000093long int initdram (int board_type)
94{
wdenkd94f92c2003-08-28 09:41:22 +000095 ulong dramsize = 0;
wdenkb2001f22003-12-20 22:45:10 +000096 ulong dramsize2 = 0;
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020097 uint svr, pvr;
98
wdenk945af8d2003-07-16 21:53:01 +000099#ifndef CFG_RAMBOOT
wdenkd94f92c2003-08-28 09:41:22 +0000100 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000101
wdenke35745b2004-04-18 23:32:11 +0000102 /* setup SDRAM chip selects */
wdenke0ac62d2003-08-17 18:55:18 +0000103 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
104 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
wdenke35745b2004-04-18 23:32:11 +0000105 __asm__ volatile ("sync");
wdenk945af8d2003-07-16 21:53:01 +0000106
wdenkb2001f22003-12-20 22:45:10 +0000107 /* setup config registers */
wdenke35745b2004-04-18 23:32:11 +0000108 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
109 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
110 __asm__ volatile ("sync");
wdenkd4ca31c2004-01-02 14:00:00 +0000111
wdenke35745b2004-04-18 23:32:11 +0000112#if SDRAM_DDR
113 /* set tap delay */
114 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
115 __asm__ volatile ("sync");
wdenkb2001f22003-12-20 22:45:10 +0000116#endif
wdenk945af8d2003-07-16 21:53:01 +0000117
wdenke35745b2004-04-18 23:32:11 +0000118 /* find RAM size using SDRAM CS0 only */
wdenke0ac62d2003-08-17 18:55:18 +0000119 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200120 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000121 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200122 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000123 if (test1 > test2) {
124 sdram_start(0);
125 dramsize = test1;
126 } else {
127 dramsize = test2;
128 }
wdenke35745b2004-04-18 23:32:11 +0000129
130 /* memory smaller than 1MB is impossible */
131 if (dramsize < (1 << 20)) {
132 dramsize = 0;
133 }
wdenk5cf91d62004-04-23 20:32:05 +0000134
wdenke35745b2004-04-18 23:32:11 +0000135 /* set SDRAM CS0 size according to the amount of RAM found */
136 if (dramsize > 0) {
137 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
138 } else {
139 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
140 }
141
wdenke35745b2004-04-18 23:32:11 +0000142 /* let SDRAM CS1 start right after CS0 */
wdenkb2001f22003-12-20 22:45:10 +0000143 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
wdenke35745b2004-04-18 23:32:11 +0000144
145 /* find RAM size using SDRAM CS1 only */
wdenk07cc0992005-05-05 00:04:14 +0000146 if (!dramsize)
wdenka6310922005-04-21 21:10:22 +0000147 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200148 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000149 if (!dramsize) {
150 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200151 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000152 }
wdenkb2001f22003-12-20 22:45:10 +0000153 if (test1 > test2) {
154 sdram_start(0);
155 dramsize2 = test1;
156 } else {
157 dramsize2 = test2;
158 }
wdenk5cf91d62004-04-23 20:32:05 +0000159
wdenke35745b2004-04-18 23:32:11 +0000160 /* memory smaller than 1MB is impossible */
161 if (dramsize2 < (1 << 20)) {
162 dramsize2 = 0;
163 }
wdenk5cf91d62004-04-23 20:32:05 +0000164
wdenke35745b2004-04-18 23:32:11 +0000165 /* set SDRAM CS1 size according to the amount of RAM found */
166 if (dramsize2 > 0) {
167 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
168 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
169 } else {
170 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
171 }
wdenke0ac62d2003-08-17 18:55:18 +0000172
wdenke35745b2004-04-18 23:32:11 +0000173#else /* CFG_RAMBOOT */
174
175 /* retrieve size of memory connected to SDRAM CS0 */
176 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
177 if (dramsize >= 0x13) {
178 dramsize = (1 << (dramsize - 0x13)) << 20;
179 } else {
180 dramsize = 0;
181 }
182
183 /* retrieve size of memory connected to SDRAM CS1 */
184 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
185 if (dramsize2 >= 0x13) {
186 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
187 } else {
188 dramsize2 = 0;
189 }
190
wdenkd94f92c2003-08-28 09:41:22 +0000191#endif /* CFG_RAMBOOT */
wdenkb2001f22003-12-20 22:45:10 +0000192
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200193 /*
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200194 * On MPC5200B we need to set the special configuration delay in the
195 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200196 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
197 *
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200198 * "The SDelay should be written to a value of 0x00000004. It is
199 * required to account for changes caused by normal wafer processing
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200200 * parameters."
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200201 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200202 svr = get_svr();
203 pvr = get_pvr();
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200204 if ((SVR_MJREV(svr) >= 2) &&
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200205 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
206
207 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
208 __asm__ volatile ("sync");
209 }
210
wdenke35745b2004-04-18 23:32:11 +0000211 return dramsize + dramsize2;
212}
213
214#elif defined(CONFIG_MGT5100)
215
216long int initdram (int board_type)
217{
218 ulong dramsize = 0;
219#ifndef CFG_RAMBOOT
220 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000221
wdenke35745b2004-04-18 23:32:11 +0000222 /* setup and enable SDRAM chip selects */
223 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
224 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
225 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
226 __asm__ volatile ("sync");
227
228 /* setup config registers */
229 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
230 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
231
232 /* address select register */
233 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
234 __asm__ volatile ("sync");
235
236 /* find RAM size */
237 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200238 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000239 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200240 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000241 if (test1 > test2) {
242 sdram_start(0);
243 dramsize = test1;
244 } else {
245 dramsize = test2;
246 }
247
248 /* set SDRAM end address according to size */
249 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
wdenk5cf91d62004-04-23 20:32:05 +0000250
wdenke35745b2004-04-18 23:32:11 +0000251#else /* CFG_RAMBOOT */
252
253 /* Retrieve amount of SDRAM available */
254 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
255
256#endif /* CFG_RAMBOOT */
257
wdenke0ac62d2003-08-17 18:55:18 +0000258 return dramsize;
wdenk945af8d2003-07-16 21:53:01 +0000259}
260
wdenke35745b2004-04-18 23:32:11 +0000261#else
262#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
263#endif
264
wdenk945af8d2003-07-16 21:53:01 +0000265int checkboard (void)
266{
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100267#if defined (CONFIG_LITE5200B)
268 puts ("Board: Freescale Lite5200B\n");
269#elif defined(CONFIG_MPC5200)
wdenk945af8d2003-07-16 21:53:01 +0000270 puts ("Board: Motorola MPC5200 (IceCube)\n");
271#elif defined(CONFIG_MGT5100)
272 puts ("Board: Motorola MGT5100 (IceCube)\n");
273#endif
274 return 0;
275}
276
277void flash_preinit(void)
278{
279 /*
280 * Now, when we are in RAM, enable flash write
281 * access for detection process.
282 * Note that CS_BOOT cannot be cleared when
283 * executing in flash.
284 */
285#if defined(CONFIG_MGT5100)
286 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
287 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
288#endif
289 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
290}
wdenk96e48cf2003-08-05 18:22:44 +0000291
wdenk7152b1d2003-09-05 23:19:14 +0000292void flash_afterinit(ulong size)
293{
294 if (size == 0x800000) { /* adjust mapping */
wdenk42d1f032003-10-15 23:53:47 +0000295 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
wdenk7152b1d2003-09-05 23:19:14 +0000296 START_REG(CFG_BOOTCS_START | size);
wdenk42d1f032003-10-15 23:53:47 +0000297 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
wdenk7152b1d2003-09-05 23:19:14 +0000298 STOP_REG(CFG_BOOTCS_START | size, size);
299 }
300}
301
wdenk96e48cf2003-08-05 18:22:44 +0000302#ifdef CONFIG_PCI
303static struct pci_controller hose;
304
305extern void pci_mpc5xxx_init(struct pci_controller *);
306
307void pci_init_board(void)
308{
309 pci_mpc5xxx_init(&hose);
310}
311#endif
wdenkc3f9d492004-03-14 00:59:59 +0000312
313#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
314
wdenkc3f9d492004-03-14 00:59:59 +0000315void init_ide_reset (void)
316{
wdenk4d13cba2004-03-14 14:09:05 +0000317 debug ("init_ide_reset\n");
wdenk42dfe7a2004-03-14 22:25:36 +0000318
wdenkc3f9d492004-03-14 00:59:59 +0000319 /* Configure PSC1_4 as GPIO output for ATA reset */
wdenkc3f9d492004-03-14 00:59:59 +0000320 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
wdenk4d13cba2004-03-14 14:09:05 +0000321 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000322 /* Deassert reset */
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100323 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000324}
325
326void ide_set_reset (int idereset)
327{
wdenk4d13cba2004-03-14 14:09:05 +0000328 debug ("ide_reset(%d)\n", idereset);
329
wdenkc3f9d492004-03-14 00:59:59 +0000330 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100331 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000332 /* Make a delay. MPC5200 spec says 25 usec min */
333 udelay(500000);
wdenkc3f9d492004-03-14 00:59:59 +0000334 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100335 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000336 }
337}
338#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
Stefan Roesee59581c2006-11-28 17:55:49 +0100339
340#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
341void
342ft_board_setup(void *blob, bd_t *bd)
343{
344 ft_cpu_setup(blob, bd);
345}
346#endif