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Poonam Aggrwal0e870982009-07-31 12:08:14 +05301/*
York Sun709389b2012-08-17 08:20:26 +00002 * Copyright 2008-2012 Freescale Semiconductor, Inc.
Poonam Aggrwal0e870982009-07-31 12:08:14 +05303 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020024#include <asm-offsets.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060025#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page. We then set up the core, and head to
42 * start_secondary. Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46 .globl __secondary_start_page
47 .align 12
48__secondary_start_page:
49/* First do some preliminary setup */
50 lis r3, HID0_EMCP@h /* enable machine check */
Kumar Gala0f060c32008-10-23 01:47:38 -050051#ifndef CONFIG_E500MC
Kumar Galaec2b74f2008-01-17 16:48:33 -060052 ori r3,r3,HID0_TBEN@l /* enable Timebase */
Kumar Gala0f060c32008-10-23 01:47:38 -050053#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -060054#ifdef CONFIG_PHYS_64BIT
55 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
56#endif
57 mtspr SPRN_HID0,r3
58
Kumar Gala0f060c32008-10-23 01:47:38 -050059#ifndef CONFIG_E500MC
Kumar Galaec2b74f2008-01-17 16:48:33 -060060 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
Sandeep Gopalpetff8473e2010-03-12 10:45:02 +053061 mfspr r0,PVR
62 andi. r0,r0,0xff
63 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
64 blt 1f
65 /* Set MBDD bit also */
66 ori r3, r3, HID1_MBDD@l
671:
Kumar Galaec2b74f2008-01-17 16:48:33 -060068 mtspr SPRN_HID1,r3
Kumar Gala0f060c32008-10-23 01:47:38 -050069#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -060070
Kumar Gala43f082b2011-11-22 06:51:15 -060071#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
72 mfspr r3,977
73 oris r3,r3,0x0100
74 mtspr 977,r3
75#endif
76
Scott Wood33eee332012-08-14 10:14:53 +000077#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
78 mfspr r3,SPRN_SVR
79 rlwinm r3,r3,0,0xff
80 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
81 cmpw r3,r4
82 beq 1f
83
84#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
85 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
86 cmpw r3,r4
87 beq 1f
88#endif
89
90 /* Not a supported revision affected by erratum */
91 b 2f
92
931: /* Erratum says set bits 55:60 to 001001 */
94 msync
95 isync
96 mfspr r3,976
97 li r4,0x48
98 rlwimi r3,r4,0,0x1f8
99 mtspr 976,r3
100 isync
1012:
102#endif
103
Kumar Galaec2b74f2008-01-17 16:48:33 -0600104 /* Enable branch prediction */
Kumar Gala69bcf5b2010-03-29 13:50:31 -0500105 lis r3,BUCSR_ENABLE@h
106 ori r3,r3,BUCSR_ENABLE@l
Kumar Galaec2b74f2008-01-17 16:48:33 -0600107 mtspr SPRN_BUCSR,r3
108
Kumar Galae0ff3d32008-09-08 08:51:29 -0500109 /* Ensure TB is 0 */
110 li r3,0
111 mttbl r3
112 mttbu r3
113
Kumar Galaec2b74f2008-01-17 16:48:33 -0600114 /* Enable/invalidate the I-Cache */
Kumar Gala33f57bd2010-03-26 15:14:43 -0500115 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
116 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
117 mtspr SPRN_L1CSR1,r2
1181:
119 mfspr r3,SPRN_L1CSR1
120 and. r1,r3,r2
121 bne 1b
122
123 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
124 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
125 mtspr SPRN_L1CSR1,r3
Kumar Galaec2b74f2008-01-17 16:48:33 -0600126 isync
Kumar Gala33f57bd2010-03-26 15:14:43 -05001272:
128 mfspr r3,SPRN_L1CSR1
129 andi. r1,r3,L1CSR1_ICE@l
130 beq 2b
Kumar Galaec2b74f2008-01-17 16:48:33 -0600131
132 /* Enable/invalidate the D-Cache */
Kumar Gala33f57bd2010-03-26 15:14:43 -0500133 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
134 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
135 mtspr SPRN_L1CSR0,r2
1361:
137 mfspr r3,SPRN_L1CSR0
138 and. r1,r3,r2
139 bne 1b
140
141 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
142 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
143 mtspr SPRN_L1CSR0,r3
Kumar Galaec2b74f2008-01-17 16:48:33 -0600144 isync
Kumar Gala33f57bd2010-03-26 15:14:43 -05001452:
146 mfspr r3,SPRN_L1CSR0
147 andi. r1,r3,L1CSR0_DCE@l
148 beq 2b
Kumar Galaec2b74f2008-01-17 16:48:33 -0600149
150#define toreset(x) (x - __secondary_start_page + 0xfffff000)
151
152 /* get our PIR to figure out our table entry */
York Sunffd06e02012-10-08 07:44:30 +0000153 lis r3,toreset(__spin_table_addr)@h
154 ori r3,r3,toreset(__spin_table_addr)@l
155 lwz r3,0(r3)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600156
York Sunffd06e02012-10-08 07:44:30 +0000157 /*
158 * r10 has the base address for the entry.
159 * we cannot access it yet before setting up a new TLB
160 */
Kumar Galaec2b74f2008-01-17 16:48:33 -0600161 mfspr r0,SPRN_PIR
York Sun709389b2012-08-17 08:20:26 +0000162#if defined(CONFIG_E6500)
163/*
164 * PIR definition for E6500
165 * 0-17 Reserved (logic 0s)
Timur Tabi0c7e65f2012-10-05 09:48:50 +0000166 * 8-19 CHIP_ID, 2'b00 - SoC 1
York Sun709389b2012-08-17 08:20:26 +0000167 * all others - reserved
Timur Tabi0c7e65f2012-10-05 09:48:50 +0000168 * 20-24 CLUSTER_ID 5'b00000 - CCM 1
York Sun709389b2012-08-17 08:20:26 +0000169 * all others - reserved
Timur Tabi0c7e65f2012-10-05 09:48:50 +0000170 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
171 * 2'b01 - cluster 2
172 * 2'b10 - cluster 3
173 * 2'b11 - cluster 4
174 * 27-28 CORE_ID 2'b00 - core 0
175 * 2'b01 - core 1
176 * 2'b10 - core 2
177 * 2'b11 - core 3
178 * 29-31 THREAD_ID 3'b000 - thread 0
179 * 3'b001 - thread 1
York Sun709389b2012-08-17 08:20:26 +0000180 */
181 rlwinm r4,r0,29,25,31
182#elif defined(CONFIG_E500MC)
Kumar Gala0f060c32008-10-23 01:47:38 -0500183 rlwinm r4,r0,27,27,31
184#else
Kumar Galaec2b74f2008-01-17 16:48:33 -0600185 mr r4,r0
Kumar Gala0f060c32008-10-23 01:47:38 -0500186#endif
York Sunffd06e02012-10-08 07:44:30 +0000187 slwi r8,r4,6 /* spin table is padded to 64 byte */
Kumar Gala79679d82008-03-26 08:34:25 -0500188 add r10,r3,r8
Kumar Galaec2b74f2008-01-17 16:48:33 -0600189
York Sun709389b2012-08-17 08:20:26 +0000190#ifdef CONFIG_E6500
191 mfspr r0,SPRN_PIR
192 /*
193 * core 0 thread 0: pir reset value 0x00, new pir 0
194 * core 0 thread 1: pir reset value 0x01, new pir 1
195 * core 1 thread 0: pir reset value 0x08, new pir 2
196 * core 1 thread 1: pir reset value 0x09, new pir 3
197 * core 2 thread 0: pir reset value 0x10, new pir 4
198 * core 2 thread 1: pir reset value 0x11, new pir 5
199 * etc.
200 *
201 * Only thread 0 of each core will be running, updating PIR doesn't
202 * need to deal with the thread bits.
203 */
204 rlwinm r4,r0,30,24,30
205#endif
206
207 mtspr SPRN_PIR,r4 /* write to PIR register */
208
York Sun6d2b9da2012-10-08 07:44:08 +0000209#ifdef CONFIG_SYS_CACHE_STASHING
210 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
211 slwi r8,r4,1
212 addi r8,r8,32
213 mtspr L1CSR2,r8
214#endif
215
York Sun5e23ab02012-05-07 07:26:47 +0000216#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
217 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
218 /*
219 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
220 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
221 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
222 */
York Sun1e9ea852012-05-07 07:26:45 +0000223 mfspr r3,SPRN_SVR
York Sun5e23ab02012-05-07 07:26:47 +0000224 rlwinm r6,r3,24,~0x800 /* clear E bit */
York Sun1e9ea852012-05-07 07:26:45 +0000225
York Sun5e23ab02012-05-07 07:26:47 +0000226 lis r5,SVR_P4080@h
227 ori r5,r5,SVR_P4080@l
228 cmpw r6,r5
229 bne 1f
230
231 rlwinm r3,r3,0,0xf0
232 li r5,0x30
233 cmpw r3,r5
234 bge 2f
2351:
York Sun57125f22012-08-08 18:04:53 +0000236#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
237 lis r3,toreset(enable_cpu_a011_workaround)@ha
238 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
239 cmpwi r3,0
240 beq 2f
241#endif
York Sun5e23ab02012-05-07 07:26:47 +0000242 mfspr r3,L1CSR2
243 oris r3,r3,(L1CSR2_DCWS)@h
244 mtspr L1CSR2,r3
York Sun1e9ea852012-05-07 07:26:45 +00002452:
Kumar Galafd3c9be2010-05-05 22:35:27 -0500246#endif
247
Kumar Gala1b3e4042009-03-19 09:16:10 -0500248#ifdef CONFIG_BACKSIDE_L2_CACHE
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500249 /* skip L2 setup on P2040/P2040E as they have no L2 */
York Sunfeae3422012-05-07 07:39:53 +0000250 mfspr r3,SPRN_SVR
251 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
252
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500253 lis r3,SVR_P2040@h
254 ori r3,r3,SVR_P2040@l
York Sunfeae3422012-05-07 07:39:53 +0000255 cmpw r6,r3
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500256 beq 3f
257
Kumar Gala1b3e4042009-03-19 09:16:10 -0500258 /* Enable/invalidate the L2 cache */
259 msync
Dave Liuff8822952009-10-31 07:59:55 +0800260 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
261 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
262 mtspr SPRN_L2CSR0,r2
Kumar Gala1b3e4042009-03-19 09:16:10 -05002631:
264 mfspr r3,SPRN_L2CSR0
Dave Liuff8822952009-10-31 07:59:55 +0800265 and. r1,r3,r2
Kumar Gala1b3e4042009-03-19 09:16:10 -0500266 bne 1b
267
Kumar Gala82fd1f82009-03-19 02:53:01 -0500268#ifdef CONFIG_SYS_CACHE_STASHING
269 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
270 addi r3,r8,1
271 mtspr SPRN_L2CSR1,r3
272#endif
273
Kumar Gala1b3e4042009-03-19 09:16:10 -0500274 lis r3,CONFIG_SYS_INIT_L2CSR0@h
275 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
276 mtspr SPRN_L2CSR0,r3
277 isync
Dave Liuff8822952009-10-31 07:59:55 +08002782:
279 mfspr r3,SPRN_L2CSR0
280 andis. r1,r3,L2CSR0_L2E@h
281 beq 2b
Kumar Gala1b3e4042009-03-19 09:16:10 -0500282#endif
Kumar Galaacf3f8d2011-07-21 00:20:21 -05002833:
York Sunffd06e02012-10-08 07:44:30 +0000284 /* setup mapping for the spin table, WIMGE=0b00100 */
285 lis r13,toreset(__spin_table_addr)@h
286 ori r13,r13,toreset(__spin_table_addr)@l
287 lwz r13,0(r13)
288 /* mask by 4K */
289 rlwinm r13,r13,0,0,19
Kumar Gala1b3e4042009-03-19 09:16:10 -0500290
York Sunffd06e02012-10-08 07:44:30 +0000291 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
292 mtspr SPRN_MAS0,r11
293 lis r11,(MAS1_VALID|MAS1_IPROT)@h
294 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
295 mtspr SPRN_MAS1,r11
296 oris r11,r13,(MAS2_M|MAS2_G)@h
297 ori r11,r13,(MAS2_M|MAS2_G)@l
298 mtspr SPRN_MAS2,r11
299 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
300 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
301 mtspr SPRN_MAS3,r11
302 li r11,0
303 mtspr SPRN_MAS7,r11
304 tlbwe
305
306 /*
307 * __bootpg_addr has the address of __second_half_boot_page
308 * jump there in AS=1 space with cache enabled
309 */
310 lis r13,toreset(__bootpg_addr)@h
311 ori r13,r13,toreset(__bootpg_addr)@l
312 lwz r11,0(r13)
313 mtspr SPRN_SRR0,r11
314 mfmsr r13
315 ori r12,r13,MSR_IS|MSR_DS@l
316 mtspr SPRN_SRR1,r12
317 rfi
318
319 /*
320 * Allocate some space for the SDRAM address of the bootpg.
321 * This variable has to be in the boot page so that it can
322 * be accessed by secondary cores when they come out of reset.
323 */
324 .align L1_CACHE_SHIFT
325 .globl __bootpg_addr
326__bootpg_addr:
327 .long 0
328
329 .global __spin_table_addr
330__spin_table_addr:
331 .long 0
332
333 /*
334 * This variable is set by cpu_init_r() after parsing hwconfig
335 * to enable workaround for erratum NMG_CPU_A011.
336 */
337 .align L1_CACHE_SHIFT
338 .global enable_cpu_a011_workaround
339enable_cpu_a011_workaround:
340 .long 1
341
342 /* Fill in the empty space. The actual reset vector is
343 * the last word of the page */
344__secondary_start_code_end:
345 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
346__secondary_reset_vector:
347 b __secondary_start_page
348
349
350/* this is a separated page for the spin table and cacheable boot code */
351 .align L1_CACHE_SHIFT
352 .global __second_half_boot_page
353__second_half_boot_page:
York Sun2a5fcb82012-10-28 08:12:54 +0000354#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
355 lis r3,(spin_table_compat - __second_half_boot_page)@h
356 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
357 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
358 lwz r14,0(r3)
359#endif
360
Kumar Gala79679d82008-03-26 08:34:25 -0500361#define ENTRY_ADDR_UPPER 0
362#define ENTRY_ADDR_LOWER 4
363#define ENTRY_R3_UPPER 8
364#define ENTRY_R3_LOWER 12
365#define ENTRY_RESV 16
366#define ENTRY_PIR 20
York Sunffd06e02012-10-08 07:44:30 +0000367#define ENTRY_SIZE 64
368 /*
369 * setup the entry
370 * r10 has the base address of the spin table.
371 * spin table is defined as
372 * struct {
373 * uint64_t entry_addr;
374 * uint64_t r3;
375 * uint32_t rsvd1;
376 * uint32_t pir;
377 * };
378 * we pad this struct to 64 bytes so each entry is in its own cacheline
379 */
Kumar Gala79679d82008-03-26 08:34:25 -0500380 li r3,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600381 li r8,1
York Sunffd06e02012-10-08 07:44:30 +0000382 mfspr r4,SPRN_PIR
Kumar Gala79679d82008-03-26 08:34:25 -0500383 stw r3,ENTRY_ADDR_UPPER(r10)
Kumar Gala79679d82008-03-26 08:34:25 -0500384 stw r3,ENTRY_R3_UPPER(r10)
385 stw r4,ENTRY_R3_LOWER(r10)
York Sunffd06e02012-10-08 07:44:30 +0000386 stw r3,ENTRY_RESV(r10)
387 stw r4,ENTRY_PIR(r10)
388 msync
389 stw r8,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600390
391 /* spin waiting for addr */
York Sun2a5fcb82012-10-28 08:12:54 +00003923:
393/*
394 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
395 * memory. Old OS may not work with this change. A patch is waiting to be
396 * accepted for Linux kernel. Other OS needs similar fix to spin table.
397 * For OSes with old spin table code, we can enable this temporary fix by
398 * setting environmental variable "spin_table_compat". For new OSes, set
399 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
400 * and related code. For now, it is enabled by default.
401 */
402#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
403 cmpwi r14,0
404 beq 4f
405 dcbf 0, r10
406 sync
4074:
408#endif
409 lwz r4,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600410 andi. r11,r4,1
York Sunffd06e02012-10-08 07:44:30 +0000411 bne 3b
Kumar Galacf6cc012008-04-28 02:24:04 -0500412 isync
Kumar Gala79679d82008-03-26 08:34:25 -0500413
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500414 /* setup IVORs to match fixed offsets */
415#include "fixed_ivor.S"
416
Kumar Gala79679d82008-03-26 08:34:25 -0500417 /* get the upper bits of the addr */
418 lwz r11,ENTRY_ADDR_UPPER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600419
420 /* setup branch addr */
Kumar Gala79679d82008-03-26 08:34:25 -0500421 mtspr SPRN_SRR0,r4
Kumar Galaec2b74f2008-01-17 16:48:33 -0600422
423 /* mark the entry as released */
424 li r8,3
Kumar Gala79679d82008-03-26 08:34:25 -0500425 stw r8,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600426
427 /* mask by ~64M to setup our tlb we will jump to */
Kumar Gala79679d82008-03-26 08:34:25 -0500428 rlwinm r12,r4,0,0,5
Kumar Galaec2b74f2008-01-17 16:48:33 -0600429
York Sunffd06e02012-10-08 07:44:30 +0000430 /*
431 * setup r3, r4, r5, r6, r7, r8, r9
432 * r3 contains the value to put in the r3 register at secondary cpu
433 * entry. The high 32-bits are ignored on 32-bit chip implementations.
434 * 64-bit chip implementations however shall load all 64-bits
435 */
436#ifdef CONFIG_SYS_PPC64
437 ld r3,ENTRY_R3_UPPER(r10)
438#else
Kumar Gala79679d82008-03-26 08:34:25 -0500439 lwz r3,ENTRY_R3_LOWER(r10)
York Sunffd06e02012-10-08 07:44:30 +0000440#endif
Kumar Gala79679d82008-03-26 08:34:25 -0500441 li r4,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600442 li r5,0
York Sun3f0997b2012-10-08 07:44:29 +0000443 li r6,0
Kumar Gala79679d82008-03-26 08:34:25 -0500444 lis r7,(64*1024*1024)@h
445 li r8,0
446 li r9,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600447
448 /* load up the pir */
Kumar Gala79679d82008-03-26 08:34:25 -0500449 lwz r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600450 mtspr SPRN_PIR,r0
451 mfspr r0,SPRN_PIR
Kumar Gala79679d82008-03-26 08:34:25 -0500452 stw r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600453
Haiying Wang181a3652008-12-03 10:08:19 -0500454 mtspr IVPR,r12
Kumar Galaec2b74f2008-01-17 16:48:33 -0600455/*
456 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
457 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
458 * second mapping that maps addr 1:1 for 64M, and then we jump to
459 * addr
460 */
Kumar Gala79679d82008-03-26 08:34:25 -0500461 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
462 mtspr SPRN_MAS0,r10
463 lis r10,(MAS1_VALID|MAS1_IPROT)@h
464 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
465 mtspr SPRN_MAS1,r10
Kumar Galaec2b74f2008-01-17 16:48:33 -0600466 /* WIMGE = 0b00000 for now */
Kumar Gala79679d82008-03-26 08:34:25 -0500467 mtspr SPRN_MAS2,r12
468 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
469 mtspr SPRN_MAS3,r12
470#ifdef CONFIG_ENABLE_36BIT_PHYS
471 mtspr SPRN_MAS7,r11
472#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600473 tlbwe
474
475/* Now we have another mapping for this page, so we jump to that
476 * mapping
477 */
Kumar Gala79679d82008-03-26 08:34:25 -0500478 mtspr SPRN_SRR1,r13
479 rfi
Kumar Galaec2b74f2008-01-17 16:48:33 -0600480
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500481
York Sunffd06e02012-10-08 07:44:30 +0000482 .align 6
Kumar Galaec2b74f2008-01-17 16:48:33 -0600483 .globl __spin_table
484__spin_table:
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530485 .space CONFIG_MAX_CPUS*ENTRY_SIZE
York Sun2a5fcb82012-10-28 08:12:54 +0000486
487#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
488 .align L1_CACHE_SHIFT
489 .global spin_table_compat
490spin_table_compat:
491 .long 1
492
493#endif
494
York Sunffd06e02012-10-08 07:44:30 +0000495__spin_table_end:
496 .space 4096 - (__spin_table_end - __spin_table)