blob: e920b89ef540d5ad0ab48fc7d3cdf932adec10b6 [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
4 select SPL_BOARD_INIT
5 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Patrick Delaunaybc061342018-07-09 15:17:21 +02008 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
10 select SPL_GPIO_SUPPORT
11 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
Patrick Delaunay49ef8e12019-07-30 19:16:36 +020019 select SPL_SPI_LOAD
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010020 select SPL_SYSCON
Patrick Delaunay9cd8b9f2019-07-30 19:16:33 +020021 select SPL_WATCHDOG_SUPPORT if WATCHDOG
Patrick Delaunay27a986d2019-04-18 17:32:47 +020022 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
23 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010024 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010025 imply SPL_LIBDISK_SUPPORT
26
27config SYS_SOC
28 default "stm32mp"
29
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020030config SYS_MALLOC_LEN
31 default 0x2000000
32
Patrick Delaunay579a3e72019-04-18 17:32:37 +020033config ENV_SIZE
Patrice Chotard1538e1a2019-05-07 18:40:47 +020034 default 0x2000
Patrick Delaunay579a3e72019-04-18 17:32:37 +020035
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010036config TARGET_STM32MP1
37 bool "Support stm32mp1xx"
Patrick Delaunayabf26782019-02-12 11:44:39 +010038 select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
Lokesh Vutlaacf15002018-04-26 18:21:26 +053039 select CPU_V7A
Patrick Delaunayabf26782019-02-12 11:44:39 +010040 select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
Patrick Delaunay41c79772018-04-16 10:13:24 +020041 select CPU_V7_HAS_VIRT
Patrick Delaunaye81f8d12019-07-02 13:26:07 +020042 select OF_BOARD_SETUP
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010043 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020044 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010045 select STM32_RESET
Patrick Delaunay16a07222019-07-30 19:16:25 +020046 select STM32_SERIAL
Andre Przywara7842b6a2018-04-12 04:24:46 +030047 select SYS_ARCH_TIMER
Patrick Delaunay34199822019-04-18 17:32:45 +020048 imply BOOTCOUNT_LIMIT
Patrick Delaunay27a986d2019-04-18 17:32:47 +020049 imply BOOTSTAGE
Patrick Delaunay34199822019-04-18 17:32:45 +020050 imply CMD_BOOTCOUNT
Patrick Delaunay27a986d2019-04-18 17:32:47 +020051 imply CMD_BOOTSTAGE
Patrick Delaunayeee15802019-12-03 09:38:58 +010052 imply CMD_CLS if CMD_BMP
Patrick Delaunaya67d9582019-07-30 19:16:26 +020053 imply DISABLE_CONSOLE
Patrick Delaunay67551982019-07-30 19:16:23 +020054 imply PRE_CONSOLE_BUFFER
Patrick Delaunayc50c9282019-07-30 19:16:22 +020055 imply SILENT_CONSOLE
Patrick Delaunayabf26782019-02-12 11:44:39 +010056 imply SYSRESET_PSCI if STM32MP1_TRUSTED
57 imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010058 help
59 target STMicroelectronics SOC STM32MP1 family
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010060 STM32MP157, STM32MP153 or STM32MP151
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010061 STMicroelectronics MPU with core ARMv7
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010062 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010063
Patrick Delaunayabf26782019-02-12 11:44:39 +010064config STM32MP1_TRUSTED
65 bool "Support trusted boot with TF-A"
66 default y if !SPL
67 select ARM_SMCCC
68 help
69 Say Y here to enable boot with TF-A
70 Trusted boot chain is :
71 BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32
Patrick Delaunay152c84b2019-07-02 13:26:06 +020072 TF-A monitor provides proprietary SMC to manage secure devices
73
74config STM32MP1_OPTEE
75 bool "Support trusted boot with TF-A and OP-TEE"
76 depends on STM32MP1_TRUSTED
77 default n
78 help
79 Say Y here to enable boot with TF-A and OP-TEE
80 Trusted boot chain is :
81 BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32
82 OP-TEE monitor provides ST SMC to access to secure resources
Patrick Delaunayabf26782019-02-12 11:44:39 +010083
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010084config SYS_TEXT_BASE
85 prompt "U-Boot base address"
86 default 0xC0100000
87 help
88 configure the U-Boot base address
89 when DDR driver is used:
90 DDR + 1MB (0xC0100000)
91
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010092config NR_DRAM_BANKS
93 default 1
94
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +010095config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
96 hex "Partition on MMC2 to use to load U-Boot from"
97 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
98 default 1
99 help
100 Partition on the second MMC to load U-Boot from when the MMC is being
101 used in raw mode
102
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200103config STM32_ETZPC
104 bool "STM32 Extended TrustZone Protection"
105 depends on TARGET_STM32MP1
106 default y
107 help
108 Say y to enable STM32 Extended TrustZone Protection
109
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200110config CMD_STM32KEY
111 bool "command stm32key to fuse public key hash"
112 default y
113 depends on CMD_FUSE
114 help
115 fuse public key hash in corresponding fuse used to authenticate
116 binary.
117
Patrick Delaunay67551982019-07-30 19:16:23 +0200118
119config PRE_CON_BUF_ADDR
120 default 0xC02FF000
121
122config PRE_CON_BUF_SZ
123 default 4096
124
Patrick Delaunay27a986d2019-04-18 17:32:47 +0200125config BOOTSTAGE_STASH_ADDR
126 default 0xC3000000
127
Patrick Delaunay34199822019-04-18 17:32:45 +0200128if BOOTCOUNT_LIMIT
129config SYS_BOOTCOUNT_SINGLEWORD
130 default y
131
132# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
133config SYS_BOOTCOUNT_ADDR
134 default 0x5C00A154
135endif
136
Patrick Delaunay320d2662018-05-17 14:50:46 +0200137if DEBUG_UART
138
139config DEBUG_UART_BOARD_INIT
140 default y
141
142# debug on UART4 by default
143config DEBUG_UART_BASE
144 default 0x40010000
145
146# clock source is HSI on reset
147config DEBUG_UART_CLOCK
148 default 64000000
149endif
150
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100151source "board/st/stm32mp1/Kconfig"
152
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100153endif