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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek185f7d92012-09-13 20:23:34 +00002/*
3 * (C) Copyright 2011 Michal Simek
4 *
5 * Michal SIMEK <monstr@monstr.eu>
6 *
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
Michal Simek185f7d92012-09-13 20:23:34 +00009 */
10
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +053011#include <clk.h>
Michal Simek185f7d92012-09-13 20:23:34 +000012#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070013#include <cpu_func.h>
Michal Simek6889ca72015-11-30 14:14:56 +010014#include <dm.h>
Michal Simek185f7d92012-09-13 20:23:34 +000015#include <net.h>
Michal Simek2fd24892014-04-25 14:17:38 +020016#include <netdev.h>
Michal Simek185f7d92012-09-13 20:23:34 +000017#include <config.h>
Michal Simekb8de29f2015-09-24 20:13:45 +020018#include <console.h>
Michal Simek185f7d92012-09-13 20:23:34 +000019#include <malloc.h>
20#include <asm/io.h>
21#include <phy.h>
22#include <miiphy.h>
Mateusz Kulikowskie7138b32016-01-23 11:54:33 +010023#include <wait_bit.h>
Michal Simek185f7d92012-09-13 20:23:34 +000024#include <watchdog.h>
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +053025#include <asm/system.h>
David Andrey01fbf312013-04-05 17:24:24 +020026#include <asm/arch/hardware.h>
Michal Simek80243522012-10-15 14:01:23 +020027#include <asm/arch/sys_proto.h>
Simon Glass336d4612020-02-03 07:36:16 -070028#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070029#include <linux/err.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090030#include <linux/errno.h>
Michal Simek185f7d92012-09-13 20:23:34 +000031
Michal Simek185f7d92012-09-13 20:23:34 +000032/* Bit/mask specification */
33#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
38
39#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
42
43#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
46
47/* Wrap bit, last descriptor */
48#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
Michal Simek23a598f2015-08-17 09:58:54 +020050#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
Michal Simek185f7d92012-09-13 20:23:34 +000051
Michal Simek185f7d92012-09-13 20:23:34 +000052#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
56
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053057#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
58#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
59#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
60#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
Siva Durga Prasad Paladugu4eaf8f52016-05-16 15:31:38 +053061#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053062#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
Michal Simekf17ea712015-09-08 17:20:01 +020063#ifdef CONFIG_ARM64
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053064#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
Michal Simekf17ea712015-09-08 17:20:01 +020065#else
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053066#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
Michal Simekf17ea712015-09-08 17:20:01 +020067#endif
Michal Simek185f7d92012-09-13 20:23:34 +000068
Siva Durga Prasad Paladugu8a584c82014-07-08 15:31:03 +053069#ifdef CONFIG_ARM64
70# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
71#else
72# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
73#endif
74
75#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
76 ZYNQ_GEM_NWCFG_FDEN | \
Michal Simek185f7d92012-09-13 20:23:34 +000077 ZYNQ_GEM_NWCFG_FSREM | \
78 ZYNQ_GEM_NWCFG_MDCCLKDIV)
79
80#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
81
82#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
83/* Use full configured addressable space (8 Kb) */
84#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
85/* Use full configured addressable space (4 Kb) */
86#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
87/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
88#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
89
Vipul Kumar9a7799f2018-11-26 16:27:38 +053090#if defined(CONFIG_PHYS_64BIT)
91# define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
92#else
93# define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
94#endif
95
Michal Simek185f7d92012-09-13 20:23:34 +000096#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
97 ZYNQ_GEM_DMACR_RXSIZE | \
98 ZYNQ_GEM_DMACR_TXSIZE | \
Vipul Kumar9a7799f2018-11-26 16:27:38 +053099 ZYNQ_GEM_DMACR_RXBUF | \
100 ZYNQ_GEM_DMA_BUS_WIDTH)
Michal Simek185f7d92012-09-13 20:23:34 +0000101
Michal Simeke4d23182015-08-17 09:57:46 +0200102#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
103
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +0530104#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
105
Siva Durga Prasad Paladugu5f68f442018-11-26 16:27:39 +0530106#define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
107
Michal Simekf97d7e82013-04-22 14:41:09 +0200108/* Use MII register 1 (MII status register) to detect PHY */
109#define PHY_DETECT_REG 1
110
111/* Mask used to verify certain PHY features (or register contents)
112 * in the register above:
113 * 0x1000: 10Mbps full duplex support
114 * 0x0800: 10Mbps half duplex support
115 * 0x0008: Auto-negotiation support
116 */
117#define PHY_DETECT_MASK 0x1808
118
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530119/* TX BD status masks */
120#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
121#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
122#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
123
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800124/* Clock frequencies for different speeds */
125#define ZYNQ_GEM_FREQUENCY_10 2500000UL
126#define ZYNQ_GEM_FREQUENCY_100 25000000UL
127#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
128
Michal Simek185f7d92012-09-13 20:23:34 +0000129/* Device registers */
130struct zynq_gem_regs {
Michal Simek97a51a02015-10-05 11:49:43 +0200131 u32 nwctrl; /* 0x0 - Network Control reg */
132 u32 nwcfg; /* 0x4 - Network Config reg */
133 u32 nwsr; /* 0x8 - Network Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000134 u32 reserved1;
Michal Simek97a51a02015-10-05 11:49:43 +0200135 u32 dmacr; /* 0x10 - DMA Control reg */
136 u32 txsr; /* 0x14 - TX Status reg */
137 u32 rxqbase; /* 0x18 - RX Q Base address reg */
138 u32 txqbase; /* 0x1c - TX Q Base address reg */
139 u32 rxsr; /* 0x20 - RX Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000140 u32 reserved2[2];
Michal Simek97a51a02015-10-05 11:49:43 +0200141 u32 idr; /* 0x2c - Interrupt Disable reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000142 u32 reserved3;
Michal Simek97a51a02015-10-05 11:49:43 +0200143 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000144 u32 reserved4[18];
Michal Simek97a51a02015-10-05 11:49:43 +0200145 u32 hashl; /* 0x80 - Hash Low address reg */
146 u32 hashh; /* 0x84 - Hash High address reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000147#define LADDR_LOW 0
148#define LADDR_HIGH 1
Michal Simek97a51a02015-10-05 11:49:43 +0200149 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
150 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000151 u32 reserved6[18];
Michal Simek0ebf4042015-10-05 12:49:48 +0200152#define STAT_SIZE 44
153 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +0530154 u32 reserved9[20];
155 u32 pcscntrl;
Siva Durga Prasad Paladugu5f68f442018-11-26 16:27:39 +0530156 u32 rserved12[36];
157 u32 dcfg6; /* 0x294 Design config reg6 */
158 u32 reserved7[106];
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700159 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
160 u32 reserved8[15];
161 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530162 u32 reserved10[17];
163 u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
164 u32 reserved11[2];
165 u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
Michal Simek185f7d92012-09-13 20:23:34 +0000166};
167
168/* BD descriptors */
169struct emac_bd {
170 u32 addr; /* Next descriptor pointer */
171 u32 status;
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530172#if defined(CONFIG_PHYS_64BIT)
173 u32 addr_hi;
174 u32 reserved;
175#endif
Michal Simek185f7d92012-09-13 20:23:34 +0000176};
177
Michal Simek8af4c4d2019-05-22 14:12:20 +0200178/* Reduce amount of BUFs if you have limited amount of memory */
Siva Durga Prasad Paladugueda9d302015-04-15 12:15:01 +0530179#define RX_BUF 32
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530180/* Page table entries are set to 1MB, or multiples of 1MB
181 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
182 */
183#define BD_SPACE 0x100000
184/* BD separation space */
Michal Simekff475872015-08-17 09:45:53 +0200185#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
Michal Simek185f7d92012-09-13 20:23:34 +0000186
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700187/* Setup the first free TX descriptor */
188#define TX_FREE_DESC 2
189
Michal Simek185f7d92012-09-13 20:23:34 +0000190/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
191struct zynq_gem_priv {
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530192 struct emac_bd *tx_bd;
193 struct emac_bd *rx_bd;
194 char *rxbuffers;
Michal Simek185f7d92012-09-13 20:23:34 +0000195 u32 rxbd_current;
196 u32 rx_first_buf;
197 int phyaddr;
Michal Simek05868752013-01-24 13:04:12 +0100198 int init;
Michal Simekf2fc2762015-11-30 10:24:15 +0100199 struct zynq_gem_regs *iobase;
Michal Simek16ce6de2015-10-07 16:42:56 +0200200 phy_interface_t interface;
Michal Simek185f7d92012-09-13 20:23:34 +0000201 struct phy_device *phydev;
Siva Durga Prasad Paladugu26026e62018-07-16 18:25:45 +0530202 ofnode phy_of_node;
Michal Simek185f7d92012-09-13 20:23:34 +0000203 struct mii_dev *bus;
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530204 struct clk clk;
Siva Durga Prasad Paladugu69065e82018-04-12 12:22:17 +0200205 u32 max_speed;
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530206 bool int_pcs;
Siva Durga Prasad Paladugu5f68f442018-11-26 16:27:39 +0530207 bool dma_64bit;
Michal Simek185f7d92012-09-13 20:23:34 +0000208};
209
Michal Simekb33d4a52018-06-13 10:00:30 +0200210static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
Michal Simekf2fc2762015-11-30 10:24:15 +0100211 u32 op, u16 *data)
Michal Simek185f7d92012-09-13 20:23:34 +0000212{
213 u32 mgtcr;
Michal Simekf2fc2762015-11-30 10:24:15 +0100214 struct zynq_gem_regs *regs = priv->iobase;
Michal Simekb908fca2016-12-12 09:47:26 +0100215 int err;
Michal Simek185f7d92012-09-13 20:23:34 +0000216
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100217 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
218 true, 20000, false);
Michal Simekb908fca2016-12-12 09:47:26 +0100219 if (err)
220 return err;
Michal Simek185f7d92012-09-13 20:23:34 +0000221
222 /* Construct mgtcr mask for the operation */
223 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
224 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
225 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
226
227 /* Write mgtcr and wait for completion */
228 writel(mgtcr, &regs->phymntnc);
229
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100230 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
231 true, 20000, false);
Michal Simekb908fca2016-12-12 09:47:26 +0100232 if (err)
233 return err;
Michal Simek185f7d92012-09-13 20:23:34 +0000234
235 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
236 *data = readl(&regs->phymntnc);
237
238 return 0;
239}
240
Michal Simekb33d4a52018-06-13 10:00:30 +0200241static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
Michal Simekf2fc2762015-11-30 10:24:15 +0100242 u32 regnum, u16 *val)
Michal Simek185f7d92012-09-13 20:23:34 +0000243{
Michal Simekb33d4a52018-06-13 10:00:30 +0200244 int ret;
Michal Simek198e9a42015-10-07 16:34:51 +0200245
Michal Simekf2fc2762015-11-30 10:24:15 +0100246 ret = phy_setup_op(priv, phy_addr, regnum,
247 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
Michal Simek198e9a42015-10-07 16:34:51 +0200248
249 if (!ret)
250 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
251 phy_addr, regnum, *val);
252
253 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000254}
255
Michal Simekb33d4a52018-06-13 10:00:30 +0200256static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
Michal Simekf2fc2762015-11-30 10:24:15 +0100257 u32 regnum, u16 data)
Michal Simek185f7d92012-09-13 20:23:34 +0000258{
Michal Simek198e9a42015-10-07 16:34:51 +0200259 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
260 regnum, data);
261
Michal Simekf2fc2762015-11-30 10:24:15 +0100262 return phy_setup_op(priv, phy_addr, regnum,
263 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
Michal Simek185f7d92012-09-13 20:23:34 +0000264}
265
Michal Simek6889ca72015-11-30 14:14:56 +0100266static int zynq_gem_setup_mac(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000267{
268 u32 i, macaddrlow, macaddrhigh;
Michal Simek6889ca72015-11-30 14:14:56 +0100269 struct eth_pdata *pdata = dev_get_platdata(dev);
270 struct zynq_gem_priv *priv = dev_get_priv(dev);
271 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000272
273 /* Set the MAC bits [31:0] in BOT */
Michal Simek6889ca72015-11-30 14:14:56 +0100274 macaddrlow = pdata->enetaddr[0];
275 macaddrlow |= pdata->enetaddr[1] << 8;
276 macaddrlow |= pdata->enetaddr[2] << 16;
277 macaddrlow |= pdata->enetaddr[3] << 24;
Michal Simek185f7d92012-09-13 20:23:34 +0000278
279 /* Set MAC bits [47:32] in TOP */
Michal Simek6889ca72015-11-30 14:14:56 +0100280 macaddrhigh = pdata->enetaddr[4];
281 macaddrhigh |= pdata->enetaddr[5] << 8;
Michal Simek185f7d92012-09-13 20:23:34 +0000282
283 for (i = 0; i < 4; i++) {
284 writel(0, &regs->laddr[i][LADDR_LOW]);
285 writel(0, &regs->laddr[i][LADDR_HIGH]);
286 /* Do not use MATCHx register */
287 writel(0, &regs->match[i]);
288 }
289
290 writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
291 writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
292
293 return 0;
294}
295
Michal Simek6889ca72015-11-30 14:14:56 +0100296static int zynq_phy_init(struct udevice *dev)
Michal Simek68cc3bd2015-11-30 13:54:43 +0100297{
298 int ret;
Michal Simek6889ca72015-11-30 14:14:56 +0100299 struct zynq_gem_priv *priv = dev_get_priv(dev);
300 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100301 const u32 supported = SUPPORTED_10baseT_Half |
302 SUPPORTED_10baseT_Full |
303 SUPPORTED_100baseT_Half |
304 SUPPORTED_100baseT_Full |
305 SUPPORTED_1000baseT_Half |
306 SUPPORTED_1000baseT_Full;
307
Michal Simekc8e29272015-11-30 13:58:36 +0100308 /* Enable only MDIO bus */
309 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
310
Michal Simek68cc3bd2015-11-30 13:54:43 +0100311 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
312 priv->interface);
Michal Simek90c6f2e2015-11-30 14:03:37 +0100313 if (!priv->phydev)
314 return -ENODEV;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100315
Siva Durga Prasad Paladugu69065e82018-04-12 12:22:17 +0200316 if (priv->max_speed) {
317 ret = phy_set_supported(priv->phydev, priv->max_speed);
318 if (ret)
319 return ret;
320 }
321
Siva Durga Prasad Paladugu51c019f2019-03-27 17:39:59 +0530322 priv->phydev->supported &= supported | ADVERTISED_Pause |
323 ADVERTISED_Asym_Pause;
324
Michal Simek68cc3bd2015-11-30 13:54:43 +0100325 priv->phydev->advertising = priv->phydev->supported;
Siva Durga Prasad Paladugu26026e62018-07-16 18:25:45 +0530326 priv->phydev->node = priv->phy_of_node;
Dan Murphy20671a92016-05-02 15:45:57 -0500327
Michal Simek7a673f02016-05-18 14:37:23 +0200328 return phy_config(priv->phydev);
Michal Simek68cc3bd2015-11-30 13:54:43 +0100329}
330
Michal Simek6889ca72015-11-30 14:14:56 +0100331static int zynq_gem_init(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000332{
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530333 u32 i, nwconfig;
Michal Simek55259e72016-05-18 12:37:22 +0200334 int ret;
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800335 unsigned long clk_rate = 0;
Michal Simek6889ca72015-11-30 14:14:56 +0100336 struct zynq_gem_priv *priv = dev_get_priv(dev);
337 struct zynq_gem_regs *regs = priv->iobase;
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700338 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
339 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
Michal Simek185f7d92012-09-13 20:23:34 +0000340
Siva Durga Prasad Paladugu5f68f442018-11-26 16:27:39 +0530341 if (readl(&regs->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
342 priv->dma_64bit = true;
343 else
344 priv->dma_64bit = false;
345
346#if defined(CONFIG_PHYS_64BIT)
347 if (!priv->dma_64bit) {
348 printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
349 __func__);
350 return -EINVAL;
351 }
352#else
353 if (priv->dma_64bit)
354 debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
355 __func__);
356#endif
357
Michal Simek05868752013-01-24 13:04:12 +0100358 if (!priv->init) {
359 /* Disable all interrupts */
360 writel(0xFFFFFFFF, &regs->idr);
Michal Simek185f7d92012-09-13 20:23:34 +0000361
Michal Simek05868752013-01-24 13:04:12 +0100362 /* Disable the receiver & transmitter */
363 writel(0, &regs->nwctrl);
364 writel(0, &regs->txsr);
365 writel(0, &regs->rxsr);
366 writel(0, &regs->phymntnc);
Michal Simek185f7d92012-09-13 20:23:34 +0000367
Michal Simek05868752013-01-24 13:04:12 +0100368 /* Clear the Hash registers for the mac address
369 * pointed by AddressPtr
370 */
371 writel(0x0, &regs->hashl);
372 /* Write bits [63:32] in TOP */
373 writel(0x0, &regs->hashh);
Michal Simek185f7d92012-09-13 20:23:34 +0000374
Michal Simek05868752013-01-24 13:04:12 +0100375 /* Clear all counters */
Michal Simek0ebf4042015-10-05 12:49:48 +0200376 for (i = 0; i < STAT_SIZE; i++)
Michal Simek05868752013-01-24 13:04:12 +0100377 readl(&regs->stat[i]);
Michal Simek185f7d92012-09-13 20:23:34 +0000378
Michal Simek05868752013-01-24 13:04:12 +0100379 /* Setup RxBD space */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530380 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000381
Michal Simek05868752013-01-24 13:04:12 +0100382 for (i = 0; i < RX_BUF; i++) {
383 priv->rx_bd[i].status = 0xF0000000;
384 priv->rx_bd[i].addr =
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530385 (lower_32_bits((ulong)(priv->rxbuffers)
386 + (i * PKTSIZE_ALIGN)));
387#if defined(CONFIG_PHYS_64BIT)
388 priv->rx_bd[i].addr_hi =
389 (upper_32_bits((ulong)(priv->rxbuffers)
390 + (i * PKTSIZE_ALIGN)));
391#endif
392 }
Michal Simek05868752013-01-24 13:04:12 +0100393 /* WRAP bit to last BD */
394 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
395 /* Write RxBDs to IP */
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530396 writel(lower_32_bits((ulong)priv->rx_bd), &regs->rxqbase);
397#if defined(CONFIG_PHYS_64BIT)
398 writel(upper_32_bits((ulong)priv->rx_bd), &regs->upper_rxqbase);
399#endif
Michal Simek185f7d92012-09-13 20:23:34 +0000400
Michal Simek05868752013-01-24 13:04:12 +0100401 /* Setup for DMA Configuration register */
402 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
Michal Simek185f7d92012-09-13 20:23:34 +0000403
Michal Simek05868752013-01-24 13:04:12 +0100404 /* Setup for Network Control register, MDIO, Rx and Tx enable */
Michal Simek80243522012-10-15 14:01:23 +0200405 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
Michal Simek185f7d92012-09-13 20:23:34 +0000406
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700407 /* Disable the second priority queue */
408 dummy_tx_bd->addr = 0;
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530409#if defined(CONFIG_PHYS_64BIT)
410 dummy_tx_bd->addr_hi = 0;
411#endif
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700412 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
413 ZYNQ_GEM_TXBUF_LAST_MASK|
414 ZYNQ_GEM_TXBUF_USED_MASK;
415
416 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
417 ZYNQ_GEM_RXBUF_NEW_MASK;
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530418#if defined(CONFIG_PHYS_64BIT)
419 dummy_rx_bd->addr_hi = 0;
420#endif
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700421 dummy_rx_bd->status = 0;
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700422
423 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
424 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
425
Michal Simek05868752013-01-24 13:04:12 +0100426 priv->init++;
427 }
428
Michal Simek55259e72016-05-18 12:37:22 +0200429 ret = phy_startup(priv->phydev);
430 if (ret)
431 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000432
Michal Simek64a7ead2015-11-30 13:44:49 +0100433 if (!priv->phydev->link) {
434 printf("%s: No link.\n", priv->phydev->dev->name);
Michal Simek4ed4aa22013-11-12 14:25:29 +0100435 return -1;
436 }
437
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530438 nwconfig = ZYNQ_GEM_NWCFG_INIT;
439
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530440 /*
441 * Set SGMII enable PCS selection only if internal PCS/PMA
442 * core is used and interface is SGMII.
443 */
444 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
445 priv->int_pcs) {
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530446 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
447 ZYNQ_GEM_NWCFG_PCS_SEL;
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +0530448#ifdef CONFIG_ARM64
449 writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
450 &regs->pcscntrl);
451#endif
452 }
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530453
Michal Simek64a7ead2015-11-30 13:44:49 +0100454 switch (priv->phydev->speed) {
Michal Simek80243522012-10-15 14:01:23 +0200455 case SPEED_1000:
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530456 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
Michal Simek80243522012-10-15 14:01:23 +0200457 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800458 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
Michal Simek80243522012-10-15 14:01:23 +0200459 break;
460 case SPEED_100:
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530461 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
Michal Simek242b1542015-09-08 16:55:42 +0200462 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800463 clk_rate = ZYNQ_GEM_FREQUENCY_100;
Michal Simek80243522012-10-15 14:01:23 +0200464 break;
465 case SPEED_10:
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800466 clk_rate = ZYNQ_GEM_FREQUENCY_10;
Michal Simek80243522012-10-15 14:01:23 +0200467 break;
468 }
David Andrey01fbf312013-04-05 17:24:24 +0200469
Stefan Herbrechtsmeiereff55c52017-01-17 16:27:25 +0100470 ret = clk_set_rate(&priv->clk, clk_rate);
471 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
472 dev_err(dev, "failed to set tx clock rate\n");
473 return ret;
474 }
475
476 ret = clk_enable(&priv->clk);
477 if (ret && ret != -ENOSYS) {
478 dev_err(dev, "failed to enable tx clock\n");
479 return ret;
480 }
Michal Simek80243522012-10-15 14:01:23 +0200481
482 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
483 ZYNQ_GEM_NWCTRL_TXEN_MASK);
484
Michal Simek185f7d92012-09-13 20:23:34 +0000485 return 0;
486}
487
Michal Simek6889ca72015-11-30 14:14:56 +0100488static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
Michal Simek185f7d92012-09-13 20:23:34 +0000489{
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530490 dma_addr_t addr;
491 u32 size;
Michal Simek6889ca72015-11-30 14:14:56 +0100492 struct zynq_gem_priv *priv = dev_get_priv(dev);
493 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek23a598f2015-08-17 09:58:54 +0200494 struct emac_bd *current_bd = &priv->tx_bd[1];
Michal Simek185f7d92012-09-13 20:23:34 +0000495
Michal Simek185f7d92012-09-13 20:23:34 +0000496 /* Setup Tx BD */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530497 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000498
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530499 priv->tx_bd->addr = lower_32_bits((ulong)ptr);
500#if defined(CONFIG_PHYS_64BIT)
501 priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
502#endif
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530503 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
Michal Simek23a598f2015-08-17 09:58:54 +0200504 ZYNQ_GEM_TXBUF_LAST_MASK;
505 /* Dummy descriptor to mark it as the last in descriptor chain */
506 current_bd->addr = 0x0;
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530507#if defined(CONFIG_PHYS_64BIT)
508 current_bd->addr_hi = 0x0;
509#endif
Michal Simek23a598f2015-08-17 09:58:54 +0200510 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
511 ZYNQ_GEM_TXBUF_LAST_MASK|
512 ZYNQ_GEM_TXBUF_USED_MASK;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530513
Michal Simek45c07742015-08-17 09:50:09 +0200514 /* setup BD */
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530515 writel(lower_32_bits((ulong)priv->tx_bd), &regs->txqbase);
516#if defined(CONFIG_PHYS_64BIT)
517 writel(upper_32_bits((ulong)priv->tx_bd), &regs->upper_txqbase);
518#endif
Michal Simek45c07742015-08-17 09:50:09 +0200519
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530520 addr = (ulong) ptr;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530521 addr &= ~(ARCH_DMA_MINALIGN - 1);
522 size = roundup(len, ARCH_DMA_MINALIGN);
523 flush_dcache_range(addr, addr + size);
524 barrier();
Michal Simek185f7d92012-09-13 20:23:34 +0000525
526 /* Start transmit */
527 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
528
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530529 /* Read TX BD status */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530530 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
531 printf("TX buffers exhausted in mid frame\n");
Michal Simek185f7d92012-09-13 20:23:34 +0000532
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100533 return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
534 true, 20000, true);
Michal Simek185f7d92012-09-13 20:23:34 +0000535}
536
537/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
Michal Simek6889ca72015-11-30 14:14:56 +0100538static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek185f7d92012-09-13 20:23:34 +0000539{
540 int frame_len;
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530541 dma_addr_t addr;
Michal Simek6889ca72015-11-30 14:14:56 +0100542 struct zynq_gem_priv *priv = dev_get_priv(dev);
Michal Simek185f7d92012-09-13 20:23:34 +0000543 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
Michal Simek185f7d92012-09-13 20:23:34 +0000544
545 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
Michal Simek9d9211a2015-12-09 14:26:48 +0100546 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000547
548 if (!(current_bd->status &
549 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
550 printf("GEM: SOF or EOF not set for last buffer received!\n");
Michal Simek9d9211a2015-12-09 14:26:48 +0100551 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000552 }
553
554 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
Michal Simek9d9211a2015-12-09 14:26:48 +0100555 if (!frame_len) {
556 printf("%s: Zero size packet?\n", __func__);
557 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000558 }
559
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530560#if defined(CONFIG_PHYS_64BIT)
561 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
562 | ((dma_addr_t)current_bd->addr_hi << 32));
563#else
Michal Simek9d9211a2015-12-09 14:26:48 +0100564 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530565#endif
Michal Simek9d9211a2015-12-09 14:26:48 +0100566 addr &= ~(ARCH_DMA_MINALIGN - 1);
Vipul Kumar9a7799f2018-11-26 16:27:38 +0530567
Michal Simek9d9211a2015-12-09 14:26:48 +0100568 *packetp = (uchar *)(uintptr_t)addr;
569
Stefan Theil10598582018-12-17 09:12:30 +0100570 invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
571 barrier();
572
Michal Simek9d9211a2015-12-09 14:26:48 +0100573 return frame_len;
574}
575
576static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
577{
578 struct zynq_gem_priv *priv = dev_get_priv(dev);
579 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
580 struct emac_bd *first_bd;
581
582 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
583 priv->rx_first_buf = priv->rxbd_current;
584 } else {
585 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
586 current_bd->status = 0xF0000000; /* FIXME */
587 }
588
589 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
590 first_bd = &priv->rx_bd[priv->rx_first_buf];
591 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
592 first_bd->status = 0xF0000000;
593 }
594
595 if ((++priv->rxbd_current) >= RX_BUF)
596 priv->rxbd_current = 0;
597
Michal Simekda872d72015-12-09 14:16:32 +0100598 return 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000599}
600
Michal Simek6889ca72015-11-30 14:14:56 +0100601static void zynq_gem_halt(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000602{
Michal Simek6889ca72015-11-30 14:14:56 +0100603 struct zynq_gem_priv *priv = dev_get_priv(dev);
604 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000605
Michal Simek80243522012-10-15 14:01:23 +0200606 clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
607 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
Michal Simek185f7d92012-09-13 20:23:34 +0000608}
609
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600610__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
611{
612 return -ENOSYS;
613}
614
615static int zynq_gem_read_rom_mac(struct udevice *dev)
616{
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600617 struct eth_pdata *pdata = dev_get_platdata(dev);
618
Olliver Schinaglb2330892017-04-03 16:18:53 +0200619 if (!pdata)
620 return -ENOSYS;
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600621
Olliver Schinaglb2330892017-04-03 16:18:53 +0200622 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600623}
624
Michal Simek6889ca72015-11-30 14:14:56 +0100625static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
626 int devad, int reg)
Michal Simek185f7d92012-09-13 20:23:34 +0000627{
Michal Simek6889ca72015-11-30 14:14:56 +0100628 struct zynq_gem_priv *priv = bus->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000629 int ret;
Michal Simekd1b226b2018-06-14 09:08:44 +0200630 u16 val = 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000631
Michal Simek6889ca72015-11-30 14:14:56 +0100632 ret = phyread(priv, addr, reg, &val);
633 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
634 return val;
Michal Simek185f7d92012-09-13 20:23:34 +0000635}
636
Michal Simek6889ca72015-11-30 14:14:56 +0100637static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
638 int reg, u16 value)
Michal Simek185f7d92012-09-13 20:23:34 +0000639{
Michal Simek6889ca72015-11-30 14:14:56 +0100640 struct zynq_gem_priv *priv = bus->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000641
Michal Simek6889ca72015-11-30 14:14:56 +0100642 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
643 return phywrite(priv, addr, reg, value);
Michal Simek185f7d92012-09-13 20:23:34 +0000644}
645
Michal Simek6889ca72015-11-30 14:14:56 +0100646static int zynq_gem_probe(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000647{
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530648 void *bd_space;
Michal Simek6889ca72015-11-30 14:14:56 +0100649 struct zynq_gem_priv *priv = dev_get_priv(dev);
650 int ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000651
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530652 /* Align rxbuffers to ARCH_DMA_MINALIGN */
653 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
Michal Simek5b2c9a62018-06-13 15:20:35 +0200654 if (!priv->rxbuffers)
655 return -ENOMEM;
656
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530657 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
T Karthik Reddyb6779272020-01-15 02:15:13 -0700658 ulong addr = (ulong)priv->rxbuffers;
Stefan Theil10598582018-12-17 09:12:30 +0100659 flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
660 barrier();
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530661
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530662 /* Align bd_space to MMU_SECTION_SHIFT */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530663 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Michal Simek58ecd9a2020-02-06 14:36:46 +0100664 if (!bd_space) {
665 ret = -ENOMEM;
666 goto err1;
667 }
Michal Simek5b2c9a62018-06-13 15:20:35 +0200668
Michal Simek9ce1edc2015-04-15 13:31:28 +0200669 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
670 BD_SPACE, DCACHE_OFF);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530671
672 /* Initialize the bd spaces for tx and rx bd's */
673 priv->tx_bd = (struct emac_bd *)bd_space;
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530674 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530675
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530676 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
677 if (ret < 0) {
678 dev_err(dev, "failed to get clock\n");
Michal Simek58ecd9a2020-02-06 14:36:46 +0100679 goto err1;
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530680 }
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530681
Michal Simek6889ca72015-11-30 14:14:56 +0100682 priv->bus = mdio_alloc();
683 priv->bus->read = zynq_gem_miiphy_read;
684 priv->bus->write = zynq_gem_miiphy_write;
685 priv->bus->priv = priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000686
Michal Simek6516e3f2016-12-08 10:25:44 +0100687 ret = mdio_register_seq(priv->bus, dev->seq);
Michal Simekc8e29272015-11-30 13:58:36 +0100688 if (ret)
Michal Simek58ecd9a2020-02-06 14:36:46 +0100689 goto err2;
Michal Simekc8e29272015-11-30 13:58:36 +0100690
Michal Simek58ecd9a2020-02-06 14:36:46 +0100691 ret = zynq_phy_init(dev);
692 if (ret)
693 goto err2;
694
695 return ret;
696
697err2:
698 free(priv->rxbuffers);
699err1:
700 free(priv->tx_bd);
701 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000702}
Michal Simek6889ca72015-11-30 14:14:56 +0100703
704static int zynq_gem_remove(struct udevice *dev)
705{
706 struct zynq_gem_priv *priv = dev_get_priv(dev);
707
708 free(priv->phydev);
709 mdio_unregister(priv->bus);
710 mdio_free(priv->bus);
711
712 return 0;
713}
714
715static const struct eth_ops zynq_gem_ops = {
716 .start = zynq_gem_init,
717 .send = zynq_gem_send,
718 .recv = zynq_gem_recv,
Michal Simek9d9211a2015-12-09 14:26:48 +0100719 .free_pkt = zynq_gem_free_pkt,
Michal Simek6889ca72015-11-30 14:14:56 +0100720 .stop = zynq_gem_halt,
721 .write_hwaddr = zynq_gem_setup_mac,
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600722 .read_rom_hwaddr = zynq_gem_read_rom_mac,
Michal Simek6889ca72015-11-30 14:14:56 +0100723};
724
725static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
726{
727 struct eth_pdata *pdata = dev_get_platdata(dev);
728 struct zynq_gem_priv *priv = dev_get_priv(dev);
Siva Durga Prasad Paladugu26026e62018-07-16 18:25:45 +0530729 struct ofnode_phandle_args phandle_args;
Michal Simek3cdb1452015-11-30 14:17:50 +0100730 const char *phy_mode;
Michal Simek6889ca72015-11-30 14:14:56 +0100731
Siva Durga Prasad Paladugu26026e62018-07-16 18:25:45 +0530732 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
Michal Simek6889ca72015-11-30 14:14:56 +0100733 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
734 /* Hardcode for now */
Michal Simekbcdfef72015-12-09 09:29:12 +0100735 priv->phyaddr = -1;
Michal Simek6889ca72015-11-30 14:14:56 +0100736
Michal Simek3888c8d2018-09-20 09:42:27 +0200737 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
738 &phandle_args)) {
739 debug("phy-handle does exist %s\n", dev->name);
740 priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
741 "reg", -1);
742 priv->phy_of_node = phandle_args.node;
743 priv->max_speed = ofnode_read_u32_default(phandle_args.node,
744 "max-speed",
745 SPEED_1000);
Siva Durga Prasad Paladugu26026e62018-07-16 18:25:45 +0530746 }
Michal Simek6889ca72015-11-30 14:14:56 +0100747
Siva Durga Prasad Paladugu26026e62018-07-16 18:25:45 +0530748 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
Michal Simek3cdb1452015-11-30 14:17:50 +0100749 if (phy_mode)
750 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
751 if (pdata->phy_interface == -1) {
752 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
753 return -EINVAL;
754 }
755 priv->interface = pdata->phy_interface;
756
Siva Durga Prasad Paladugu26026e62018-07-16 18:25:45 +0530757 priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530758
Michal Simek15a2acd2016-11-16 08:41:01 +0100759 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
Michal Simek3cdb1452015-11-30 14:17:50 +0100760 priv->phyaddr, phy_string_for_interface(priv->interface));
Michal Simek6889ca72015-11-30 14:14:56 +0100761
762 return 0;
763}
764
765static const struct udevice_id zynq_gem_ids[] = {
Siva Durga Prasad Paladugu1ff8bdb2019-07-25 23:07:59 -0700766 { .compatible = "cdns,versal-gem" },
Michal Simek6889ca72015-11-30 14:14:56 +0100767 { .compatible = "cdns,zynqmp-gem" },
768 { .compatible = "cdns,zynq-gem" },
769 { .compatible = "cdns,gem" },
770 { }
771};
772
773U_BOOT_DRIVER(zynq_gem) = {
774 .name = "zynq_gem",
775 .id = UCLASS_ETH,
776 .of_match = zynq_gem_ids,
777 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
778 .probe = zynq_gem_probe,
779 .remove = zynq_gem_remove,
780 .ops = &zynq_gem_ops,
781 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
782 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
783};