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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenke35745b2004-04-18 23:32:11 +00005 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
wdenk945af8d2003-07-16 21:53:01 +00008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
wdenk96e48cf2003-08-05 18:22:44 +000029#include <pci.h>
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020030#include <asm/processor.h>
Grant Likelycf2817a2007-09-06 09:46:23 -060031#include <libfdt.h>
Ben Warren19403632008-08-31 10:03:22 -070032#include <netdev.h>
Stefan Roesee59581c2006-11-28 17:55:49 +010033
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010034#if defined(CONFIG_LITE5200B)
35#include "mt46v32m16.h"
wdenke35745b2004-04-18 23:32:11 +000036#else
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010037# if defined(CONFIG_MPC5200_DDR)
38# include "mt46v16m16-75.h"
39# else
wdenke35745b2004-04-18 23:32:11 +000040#include "mt48lc16m16a2-75.h"
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010041# endif
wdenke35745b2004-04-18 23:32:11 +000042#endif
Domen Puncerd3832e82007-04-16 14:00:13 +020043
44#ifdef CONFIG_LITE5200B_PM
45/* u-boot part of low-power mode implementation */
46#define SAVED_ADDR (*(void **)0x00000000)
47#define PSC2_4 0x02
48
49void lite5200b_wakeup(void)
50{
51 unsigned char wakeup_pin;
52 void (*linux_wakeup)(void);
53
54 /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
55 * from low power mode */
56 *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
57 __asm__ volatile ("sync");
58
59 wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
60 if (wakeup_pin & PSC2_4)
61 return;
62
63 /* acknowledge to "QT"
64 * by holding pin at 1 for 10 uS */
65 *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
66 __asm__ volatile ("sync");
67 *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
68 __asm__ volatile ("sync");
69 udelay(10);
70
71 /* put ram out of self-refresh */
72 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
73 __asm__ volatile ("sync");
74 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
75 __asm__ volatile ("sync");
76 *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
77 __asm__ volatile ("sync");
78 udelay(10); /* wait a bit */
79
80 /* jump back to linux kernel code */
81 linux_wakeup = SAVED_ADDR;
82 printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
83 linux_wakeup);
84 linux_wakeup();
85}
86#else
87#define lite5200b_wakeup()
88#endif
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#ifndef CONFIG_SYS_RAMBOOT
wdenke0ac62d2003-08-17 18:55:18 +000091static void sdram_start (int hi_addr)
92{
93 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
94
wdenkb2001f22003-12-20 22:45:10 +000095 /* unlock mode register */
wdenke35745b2004-04-18 23:32:11 +000096 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
97 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +000098
wdenkb2001f22003-12-20 22:45:10 +000099 /* precharge all banks */
wdenke35745b2004-04-18 23:32:11 +0000100 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
101 __asm__ volatile ("sync");
102
103#if SDRAM_DDR
wdenkb2001f22003-12-20 22:45:10 +0000104 /* set mode register: extended mode */
wdenke35745b2004-04-18 23:32:11 +0000105 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
106 __asm__ volatile ("sync");
107
wdenkb2001f22003-12-20 22:45:10 +0000108 /* set mode register: reset DLL */
wdenke35745b2004-04-18 23:32:11 +0000109 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
110 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +0000111#endif
wdenke35745b2004-04-18 23:32:11 +0000112
113 /* precharge all banks */
114 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
115 __asm__ volatile ("sync");
116
wdenkf8d813e2004-03-02 14:05:39 +0000117 /* auto refresh */
wdenke35745b2004-04-18 23:32:11 +0000118 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
119 __asm__ volatile ("sync");
120
wdenke0ac62d2003-08-17 18:55:18 +0000121 /* set mode register */
wdenke35745b2004-04-18 23:32:11 +0000122 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
123 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +0000124
wdenke0ac62d2003-08-17 18:55:18 +0000125 /* normal operation */
wdenke35745b2004-04-18 23:32:11 +0000126 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
127 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +0000128}
wdenkd94f92c2003-08-28 09:41:22 +0000129#endif
wdenke0ac62d2003-08-17 18:55:18 +0000130
wdenke35745b2004-04-18 23:32:11 +0000131/*
132 * ATTENTION: Although partially referenced initdram does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
wdenke35745b2004-04-18 23:32:11 +0000134 * is something else than 0x00000000.
135 */
136
Becky Bruce9973e3c2008-06-09 16:03:40 -0500137phys_size_t initdram (int board_type)
wdenk945af8d2003-07-16 21:53:01 +0000138{
wdenkd94f92c2003-08-28 09:41:22 +0000139 ulong dramsize = 0;
wdenkb2001f22003-12-20 22:45:10 +0000140 ulong dramsize2 = 0;
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200141 uint svr, pvr;
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#ifndef CONFIG_SYS_RAMBOOT
wdenkd94f92c2003-08-28 09:41:22 +0000144 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000145
wdenke35745b2004-04-18 23:32:11 +0000146 /* setup SDRAM chip selects */
wdenke0ac62d2003-08-17 18:55:18 +0000147 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
148 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
wdenke35745b2004-04-18 23:32:11 +0000149 __asm__ volatile ("sync");
wdenk945af8d2003-07-16 21:53:01 +0000150
wdenkb2001f22003-12-20 22:45:10 +0000151 /* setup config registers */
wdenke35745b2004-04-18 23:32:11 +0000152 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
153 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
154 __asm__ volatile ("sync");
wdenkd4ca31c2004-01-02 14:00:00 +0000155
wdenke35745b2004-04-18 23:32:11 +0000156#if SDRAM_DDR
157 /* set tap delay */
158 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
159 __asm__ volatile ("sync");
wdenkb2001f22003-12-20 22:45:10 +0000160#endif
wdenk945af8d2003-07-16 21:53:01 +0000161
wdenke35745b2004-04-18 23:32:11 +0000162 /* find RAM size using SDRAM CS0 only */
wdenke0ac62d2003-08-17 18:55:18 +0000163 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000165 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000167 if (test1 > test2) {
168 sdram_start(0);
169 dramsize = test1;
170 } else {
171 dramsize = test2;
172 }
wdenke35745b2004-04-18 23:32:11 +0000173
174 /* memory smaller than 1MB is impossible */
175 if (dramsize < (1 << 20)) {
176 dramsize = 0;
177 }
wdenk5cf91d62004-04-23 20:32:05 +0000178
wdenke35745b2004-04-18 23:32:11 +0000179 /* set SDRAM CS0 size according to the amount of RAM found */
180 if (dramsize > 0) {
181 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
182 } else {
183 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
184 }
185
wdenke35745b2004-04-18 23:32:11 +0000186 /* let SDRAM CS1 start right after CS0 */
wdenkb2001f22003-12-20 22:45:10 +0000187 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
wdenke35745b2004-04-18 23:32:11 +0000188
189 /* find RAM size using SDRAM CS1 only */
wdenk07cc0992005-05-05 00:04:14 +0000190 if (!dramsize)
wdenka6310922005-04-21 21:10:22 +0000191 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000193 if (!dramsize) {
194 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000196 }
wdenkb2001f22003-12-20 22:45:10 +0000197 if (test1 > test2) {
198 sdram_start(0);
199 dramsize2 = test1;
200 } else {
201 dramsize2 = test2;
202 }
wdenk5cf91d62004-04-23 20:32:05 +0000203
wdenke35745b2004-04-18 23:32:11 +0000204 /* memory smaller than 1MB is impossible */
205 if (dramsize2 < (1 << 20)) {
206 dramsize2 = 0;
207 }
wdenk5cf91d62004-04-23 20:32:05 +0000208
wdenke35745b2004-04-18 23:32:11 +0000209 /* set SDRAM CS1 size according to the amount of RAM found */
210 if (dramsize2 > 0) {
211 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
212 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
213 } else {
214 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
215 }
wdenke0ac62d2003-08-17 18:55:18 +0000216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#else /* CONFIG_SYS_RAMBOOT */
wdenke35745b2004-04-18 23:32:11 +0000218
219 /* retrieve size of memory connected to SDRAM CS0 */
220 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
221 if (dramsize >= 0x13) {
222 dramsize = (1 << (dramsize - 0x13)) << 20;
223 } else {
224 dramsize = 0;
225 }
226
227 /* retrieve size of memory connected to SDRAM CS1 */
228 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
229 if (dramsize2 >= 0x13) {
230 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
231 } else {
232 dramsize2 = 0;
233 }
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#endif /* CONFIG_SYS_RAMBOOT */
wdenkb2001f22003-12-20 22:45:10 +0000236
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200237 /*
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200238 * On MPC5200B we need to set the special configuration delay in the
239 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200240 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
241 *
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200242 * "The SDelay should be written to a value of 0x00000004. It is
243 * required to account for changes caused by normal wafer processing
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200244 * parameters."
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200245 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200246 svr = get_svr();
247 pvr = get_pvr();
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200248 if ((SVR_MJREV(svr) >= 2) &&
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200249 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
250
251 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
252 __asm__ volatile ("sync");
253 }
254
Domen Puncerd3832e82007-04-16 14:00:13 +0200255 lite5200b_wakeup();
256
wdenke35745b2004-04-18 23:32:11 +0000257 return dramsize + dramsize2;
258}
259
wdenk945af8d2003-07-16 21:53:01 +0000260int checkboard (void)
261{
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100262#if defined (CONFIG_LITE5200B)
263 puts ("Board: Freescale Lite5200B\n");
Detlev Zundelfd428c02010-03-12 10:01:12 +0100264#else
wdenk945af8d2003-07-16 21:53:01 +0000265 puts ("Board: Motorola MPC5200 (IceCube)\n");
wdenk945af8d2003-07-16 21:53:01 +0000266#endif
267 return 0;
268}
269
270void flash_preinit(void)
271{
272 /*
273 * Now, when we are in RAM, enable flash write
274 * access for detection process.
275 * Note that CS_BOOT cannot be cleared when
276 * executing in flash.
277 */
wdenk945af8d2003-07-16 21:53:01 +0000278 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
279}
wdenk96e48cf2003-08-05 18:22:44 +0000280
wdenk7152b1d2003-09-05 23:19:14 +0000281void flash_afterinit(ulong size)
282{
283 if (size == 0x800000) { /* adjust mapping */
wdenk42d1f032003-10-15 23:53:47 +0000284 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285 START_REG(CONFIG_SYS_BOOTCS_START | size);
wdenk42d1f032003-10-15 23:53:47 +0000286 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
wdenk7152b1d2003-09-05 23:19:14 +0000288 }
289}
290
wdenk96e48cf2003-08-05 18:22:44 +0000291#ifdef CONFIG_PCI
292static struct pci_controller hose;
293
294extern void pci_mpc5xxx_init(struct pci_controller *);
295
296void pci_init_board(void)
297{
298 pci_mpc5xxx_init(&hose);
299}
300#endif
wdenkc3f9d492004-03-14 00:59:59 +0000301
Jon Loeliger77a31852007-07-10 10:39:10 -0500302#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
wdenkc3f9d492004-03-14 00:59:59 +0000303
wdenkc3f9d492004-03-14 00:59:59 +0000304void init_ide_reset (void)
305{
wdenk4d13cba2004-03-14 14:09:05 +0000306 debug ("init_ide_reset\n");
wdenk42dfe7a2004-03-14 22:25:36 +0000307
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100308 /* Configure PSC1_4 as GPIO output for ATA reset */
wdenkc3f9d492004-03-14 00:59:59 +0000309 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
wdenk4d13cba2004-03-14 14:09:05 +0000310 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000311 /* Deassert reset */
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100312 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000313}
314
315void ide_set_reset (int idereset)
316{
wdenk4d13cba2004-03-14 14:09:05 +0000317 debug ("ide_reset(%d)\n", idereset);
318
wdenkc3f9d492004-03-14 00:59:59 +0000319 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100320 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000321 /* Make a delay. MPC5200 spec says 25 usec min */
322 udelay(500000);
wdenkc3f9d492004-03-14 00:59:59 +0000323 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100324 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000325 }
326}
Jon Loeliger77a31852007-07-10 10:39:10 -0500327#endif
Stefan Roesee59581c2006-11-28 17:55:49 +0100328
Grant Likelycf2817a2007-09-06 09:46:23 -0600329#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Stefan Roesee59581c2006-11-28 17:55:49 +0100330void
331ft_board_setup(void *blob, bd_t *bd)
332{
333 ft_cpu_setup(blob, bd);
334}
335#endif
Ben Warren19403632008-08-31 10:03:22 -0700336
337int board_eth_init(bd_t *bis)
338{
Ben Warrene1d74802008-08-31 10:39:12 -0700339 cpu_eth_init(bis); /* Built in FEC comes first */
Ben Warren19403632008-08-31 10:03:22 -0700340 return pci_eth_init(bis);
341}