Masahiro Yamada | 0b11dbf | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 1 | # |
| 2 | # Multifunction miscellaneous devices |
| 3 | # |
| 4 | |
| 5 | menu "Multifunction device drivers" |
| 6 | |
Thomas Chou | 4395e06 | 2015-10-07 20:20:51 +0800 | [diff] [blame] | 7 | config MISC |
| 8 | bool "Enable Driver Model for Misc drivers" |
| 9 | depends on DM |
| 10 | help |
| 11 | Enable driver model for miscellaneous devices. This class is |
| 12 | used only for those do not fit other more general classes. A |
| 13 | set of generic read, write and ioctl methods may be used to |
| 14 | access the device. |
| 15 | |
Simon Glass | aaba703 | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 16 | config SPL_MISC |
| 17 | bool "Enable Driver Model for Misc drivers in SPL" |
| 18 | depends on SPL_DM |
| 19 | help |
| 20 | Enable driver model for miscellaneous devices. This class is |
| 21 | used only for those do not fit other more general classes. A |
| 22 | set of generic read, write and ioctl methods may be used to |
| 23 | access the device. |
| 24 | |
| 25 | config TPL_MISC |
| 26 | bool "Enable Driver Model for Misc drivers in TPL" |
| 27 | depends on TPL_DM |
| 28 | help |
| 29 | Enable driver model for miscellaneous devices. This class is |
| 30 | used only for those do not fit other more general classes. A |
| 31 | set of generic read, write and ioctl methods may be used to |
| 32 | access the device. |
| 33 | |
Thomas Chou | ca844dd | 2015-10-14 08:43:31 +0800 | [diff] [blame] | 34 | config ALTERA_SYSID |
| 35 | bool "Altera Sysid support" |
| 36 | depends on MISC |
| 37 | help |
| 38 | Select this to enable a sysid for Altera devices. Please find |
| 39 | details on the "Embedded Peripherals IP User Guide" of Altera. |
| 40 | |
Marek BehĂșn | aa5eb9a | 2017-06-09 19:28:44 +0200 | [diff] [blame] | 41 | config ATSHA204A |
| 42 | bool "Support for Atmel ATSHA204A module" |
| 43 | depends on MISC |
| 44 | help |
| 45 | Enable support for I2C connected Atmel's ATSHA204A |
| 46 | CryptoAuthentication module found for example on the Turris Omnia |
| 47 | board. |
| 48 | |
Tim Harvey | 8479b9e | 2022-03-07 16:24:04 -0800 | [diff] [blame] | 49 | config GATEWORKS_SC |
| 50 | bool "Gateworks System Controller Support" |
| 51 | depends on MISC |
| 52 | help |
| 53 | Enable access for the Gateworks System Controller used on Gateworks |
| 54 | boards to provide a boot watchdog, power control, temperature monitor, |
| 55 | voltage ADCs, and EEPROM. |
| 56 | |
Philipp Tomsich | 49cd8e8 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 57 | config ROCKCHIP_EFUSE |
| 58 | bool "Rockchip e-fuse support" |
| 59 | depends on MISC |
| 60 | help |
| 61 | Enable (read-only) access for the e-fuse block found in Rockchip |
| 62 | SoCs: accesses can either be made using byte addressing and a length |
| 63 | or through child-nodes that are generated based on the e-fuse map |
| 64 | retrieved from the DTS. |
| 65 | |
| 66 | This driver currently supports the RK3399 only, but can easily be |
| 67 | extended (by porting the read function from the Linux kernel sources) |
| 68 | to support other recent Rockchip devices. |
| 69 | |
Finley Xiao | a907dc3 | 2019-09-25 17:57:49 +0200 | [diff] [blame] | 70 | config ROCKCHIP_OTP |
| 71 | bool "Rockchip OTP Support" |
| 72 | depends on MISC |
| 73 | help |
| 74 | Enable (read-only) access for the one-time-programmable memory block |
| 75 | found in Rockchip SoCs: accesses can either be made using byte |
| 76 | addressing and a length or through child-nodes that are generated |
| 77 | based on the e-fuse map retrieved from the DTS. |
| 78 | |
Pragnesh Patel | 0530721 | 2020-05-29 11:33:21 +0530 | [diff] [blame] | 79 | config SIFIVE_OTP |
| 80 | bool "SiFive eMemory OTP driver" |
| 81 | depends on MISC |
| 82 | help |
| 83 | Enable support for reading and writing the eMemory OTP on the |
| 84 | SiFive SoCs. |
| 85 | |
Liviu Dudau | 0fabfeb | 2018-09-28 13:43:31 +0100 | [diff] [blame] | 86 | config VEXPRESS_CONFIG |
| 87 | bool "Enable support for Arm Versatile Express config bus" |
| 88 | depends on MISC |
| 89 | help |
| 90 | If you say Y here, you will get support for accessing the |
| 91 | configuration bus on the Arm Versatile Express boards via |
| 92 | a sysreg driver. |
| 93 | |
Simon Glass | 6fb9ac1 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 94 | config CMD_CROS_EC |
| 95 | bool "Enable crosec command" |
| 96 | depends on CROS_EC |
| 97 | help |
| 98 | Enable command-line access to the Chrome OS EC (Embedded |
| 99 | Controller). This provides the 'crosec' command which has |
| 100 | a number of sub-commands for performing EC tasks such as |
| 101 | updating its flash, accessing a small saved context area |
| 102 | and talking to the I2C bus behind the EC (if there is one). |
| 103 | |
| 104 | config CROS_EC |
| 105 | bool "Enable Chrome OS EC" |
| 106 | help |
| 107 | Enable access to the Chrome OS EC. This is a separate |
| 108 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 109 | provides access to the keyboard, some internal storage and may |
| 110 | control access to the battery and main PMIC depending on the |
| 111 | device. You can use the 'crosec' command to access it. |
| 112 | |
Simon Glass | aaba703 | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 113 | config SPL_CROS_EC |
| 114 | bool "Enable Chrome OS EC in SPL" |
Adam Ford | a074667 | 2019-08-24 13:50:34 -0500 | [diff] [blame] | 115 | depends on SPL |
Simon Glass | aaba703 | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 116 | help |
| 117 | Enable access to the Chrome OS EC in SPL. This is a separate |
| 118 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 119 | provides access to the keyboard, some internal storage and may |
| 120 | control access to the battery and main PMIC depending on the |
| 121 | device. You can use the 'crosec' command to access it. |
| 122 | |
| 123 | config TPL_CROS_EC |
| 124 | bool "Enable Chrome OS EC in TPL" |
Adam Ford | a074667 | 2019-08-24 13:50:34 -0500 | [diff] [blame] | 125 | depends on TPL |
Simon Glass | aaba703 | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 126 | help |
| 127 | Enable access to the Chrome OS EC in TPL. This is a separate |
| 128 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 129 | provides access to the keyboard, some internal storage and may |
| 130 | control access to the battery and main PMIC depending on the |
| 131 | device. You can use the 'crosec' command to access it. |
| 132 | |
Simon Glass | 6fb9ac1 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 133 | config CROS_EC_I2C |
| 134 | bool "Enable Chrome OS EC I2C driver" |
| 135 | depends on CROS_EC |
| 136 | help |
| 137 | Enable I2C access to the Chrome OS EC. This is used on older |
| 138 | ARM Chromebooks such as snow and spring before the standard bus |
| 139 | changed to SPI. The EC will accept commands across the I2C using |
| 140 | a special message protocol, and provide responses. |
| 141 | |
| 142 | config CROS_EC_LPC |
| 143 | bool "Enable Chrome OS EC LPC driver" |
| 144 | depends on CROS_EC |
| 145 | help |
| 146 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 147 | Chromebooks such as link and falco. The keyboard is provided |
| 148 | through a legacy port interface, so on x86 machines the main |
| 149 | function of the EC is power and thermal management. |
| 150 | |
Simon Glass | aaba703 | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 151 | config SPL_CROS_EC_LPC |
| 152 | bool "Enable Chrome OS EC LPC driver in SPL" |
| 153 | depends on CROS_EC |
| 154 | help |
| 155 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 156 | Chromebooks such as link and falco. The keyboard is provided |
| 157 | through a legacy port interface, so on x86 machines the main |
| 158 | function of the EC is power and thermal management. |
| 159 | |
| 160 | config TPL_CROS_EC_LPC |
| 161 | bool "Enable Chrome OS EC LPC driver in TPL" |
| 162 | depends on CROS_EC |
| 163 | help |
| 164 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 165 | Chromebooks such as link and falco. The keyboard is provided |
| 166 | through a legacy port interface, so on x86 machines the main |
| 167 | function of the EC is power and thermal management. |
| 168 | |
Simon Glass | 47cb8c6 | 2015-03-26 09:29:40 -0600 | [diff] [blame] | 169 | config CROS_EC_SANDBOX |
| 170 | bool "Enable Chrome OS EC sandbox driver" |
| 171 | depends on CROS_EC && SANDBOX |
| 172 | help |
| 173 | Enable a sandbox emulation of the Chrome OS EC. This supports |
| 174 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 175 | EC flash read/write/erase support and a few other things. It is |
| 176 | enough to perform a Chrome OS verified boot on sandbox. |
| 177 | |
Simon Glass | aaba703 | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 178 | config SPL_CROS_EC_SANDBOX |
| 179 | bool "Enable Chrome OS EC sandbox driver in SPL" |
| 180 | depends on SPL_CROS_EC && SANDBOX |
| 181 | help |
| 182 | Enable a sandbox emulation of the Chrome OS EC in SPL. This supports |
| 183 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 184 | EC flash read/write/erase support and a few other things. It is |
| 185 | enough to perform a Chrome OS verified boot on sandbox. |
| 186 | |
| 187 | config TPL_CROS_EC_SANDBOX |
| 188 | bool "Enable Chrome OS EC sandbox driver in TPL" |
| 189 | depends on TPL_CROS_EC && SANDBOX |
| 190 | help |
| 191 | Enable a sandbox emulation of the Chrome OS EC in TPL. This supports |
| 192 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 193 | EC flash read/write/erase support and a few other things. It is |
| 194 | enough to perform a Chrome OS verified boot on sandbox. |
| 195 | |
Simon Glass | 6fb9ac1 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 196 | config CROS_EC_SPI |
| 197 | bool "Enable Chrome OS EC SPI driver" |
| 198 | depends on CROS_EC |
| 199 | help |
| 200 | Enable SPI access to the Chrome OS EC. This is used on newer |
| 201 | ARM Chromebooks such as pit, pi and nyan-big. The SPI interface |
| 202 | provides a faster and more robust interface than I2C but the bugs |
| 203 | are less interesting. |
| 204 | |
Simon Glass | 879704d | 2017-05-17 03:25:02 -0600 | [diff] [blame] | 205 | config DS4510 |
| 206 | bool "Enable support for DS4510 CPU supervisor" |
| 207 | help |
| 208 | Enable support for the Maxim DS4510 CPU supervisor. It has an |
| 209 | integrated 64-byte EEPROM, four programmable non-volatile I/O pins |
| 210 | and a configurable timer for the supervisor function. The device is |
| 211 | connected over I2C. |
| 212 | |
Peng Fan | c12e0d9 | 2015-08-26 15:41:33 +0800 | [diff] [blame] | 213 | config FSL_SEC_MON |
gaurav rana | fe78378 | 2015-02-27 09:44:22 +0530 | [diff] [blame] | 214 | bool "Enable FSL SEC_MON Driver" |
| 215 | help |
| 216 | Freescale Security Monitor block is responsible for monitoring |
| 217 | system states. |
| 218 | Security Monitor can be transitioned on any security failures, |
| 219 | like software violations or hardware security violations. |
Stefan Roese | 1cdd941 | 2015-03-12 11:22:46 +0100 | [diff] [blame] | 220 | |
Simon Glass | 79d66a6 | 2019-12-06 21:41:58 -0700 | [diff] [blame] | 221 | config IRQ |
Wasim Khan | 182c5f1 | 2021-03-08 16:48:13 +0100 | [diff] [blame] | 222 | bool "Interrupt controller" |
Simon Glass | 79d66a6 | 2019-12-06 21:41:58 -0700 | [diff] [blame] | 223 | help |
Wasim Khan | 182c5f1 | 2021-03-08 16:48:13 +0100 | [diff] [blame] | 224 | This enables support for interrupt controllers, including ITSS. |
Simon Glass | 79d66a6 | 2019-12-06 21:41:58 -0700 | [diff] [blame] | 225 | Some devices have extra features, such as Apollo Lake. The |
| 226 | device has its own uclass since there are several operations |
| 227 | involved. |
| 228 | |
Paul Burton | b5392c5 | 2018-12-16 19:25:19 -0300 | [diff] [blame] | 229 | config JZ4780_EFUSE |
| 230 | bool "Ingenic JZ4780 eFUSE support" |
| 231 | depends on ARCH_JZ47XX |
| 232 | help |
| 233 | This selects support for the eFUSE on Ingenic JZ4780 SoCs. |
| 234 | |
Peng Fan | 3e020f0 | 2015-08-27 14:49:05 +0800 | [diff] [blame] | 235 | config MXC_OCOTP |
| 236 | bool "Enable MXC OCOTP Driver" |
Peng Fan | 994ab73 | 2019-07-22 01:24:55 +0000 | [diff] [blame] | 237 | depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 |
Marcel Ziswiler | 0a6f625 | 2019-03-25 17:24:57 +0100 | [diff] [blame] | 238 | default y |
Peng Fan | 3e020f0 | 2015-08-27 14:49:05 +0800 | [diff] [blame] | 239 | help |
| 240 | If you say Y here, you will get support for the One Time |
| 241 | Programmable memory pages that are stored on the some |
| 242 | Freescale i.MX processors. |
| 243 | |
Michael Scott | 33e9a69 | 2021-09-25 19:49:28 +0300 | [diff] [blame] | 244 | config SPL_MXC_OCOTP |
| 245 | bool "Enable MXC OCOTP driver in SPL" |
| 246 | depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) |
| 247 | default y |
| 248 | help |
| 249 | If you say Y here, you will get support for the One Time |
| 250 | Programmable memory pages, that are stored on some |
| 251 | Freescale i.MX processors, in SPL. |
| 252 | |
Stefan Roese | 4cf9e46 | 2016-07-19 07:45:46 +0200 | [diff] [blame] | 253 | config NUVOTON_NCT6102D |
| 254 | bool "Enable Nuvoton NCT6102D Super I/O driver" |
| 255 | help |
| 256 | If you say Y here, you will get support for the Nuvoton |
| 257 | NCT6102D Super I/O driver. This can be used to enable or |
| 258 | disable the legacy UART, the watchdog or other devices |
| 259 | in the Nuvoton Super IO chips on X86 platforms. |
| 260 | |
Simon Glass | 5bee27a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 261 | config P2SB |
Wolfgang Wallner | d872e7d | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 262 | bool "Intel Primary to Sideband Bridge" |
Simon Glass | 5bee27a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 263 | depends on X86 || SANDBOX |
| 264 | help |
Wolfgang Wallner | d872e7d | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 265 | This enables support for the Intel Primary to Sideband Bridge, |
Simon Glass | 5bee27a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 266 | abbreviated to P2SB. The P2SB is used to access various peripherals |
| 267 | such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI |
| 268 | space. The space is segmented into different channels and peripherals |
| 269 | are accessed by device-specific means within those channels. Devices |
| 270 | should be added in the device tree as subnodes of the P2SB. A |
| 271 | Peripheral Channel Register? (PCR) API is provided to access those |
| 272 | devices - see pcr_readl(), etc. |
| 273 | |
| 274 | config SPL_P2SB |
Wolfgang Wallner | d872e7d | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 275 | bool "Intel Primary to Sideband Bridge in SPL" |
Simon Glass | 5bee27a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 276 | depends on SPL && (X86 || SANDBOX) |
| 277 | help |
Wolfgang Wallner | d872e7d | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 278 | The Primary to Sideband Bridge is used to access various peripherals |
Simon Glass | 5bee27a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 279 | through memory-mapped I/O in a large chunk of PCI space. The space is |
| 280 | segmented into different channels and peripherals are accessed by |
| 281 | device-specific means within those channels. Devices should be added |
| 282 | in the device tree as subnodes of the p2sb. |
| 283 | |
| 284 | config TPL_P2SB |
Wolfgang Wallner | d872e7d | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 285 | bool "Intel Primary to Sideband Bridge in TPL" |
Simon Glass | 5bee27a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 286 | depends on TPL && (X86 || SANDBOX) |
| 287 | help |
Wolfgang Wallner | d872e7d | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 288 | The Primary to Sideband Bridge is used to access various peripherals |
Simon Glass | 5bee27a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 289 | through memory-mapped I/O in a large chunk of PCI space. The space is |
| 290 | segmented into different channels and peripherals are accessed by |
| 291 | device-specific means within those channels. Devices should be added |
| 292 | in the device tree as subnodes of the p2sb. |
| 293 | |
Simon Glass | 5fd6bad | 2016-01-21 19:43:31 -0700 | [diff] [blame] | 294 | config PWRSEQ |
| 295 | bool "Enable power-sequencing drivers" |
| 296 | depends on DM |
| 297 | help |
| 298 | Power-sequencing drivers provide support for controlling power for |
| 299 | devices. They are typically referenced by a phandle from another |
| 300 | device. When the device is started up, its power sequence can be |
| 301 | initiated. |
| 302 | |
| 303 | config SPL_PWRSEQ |
| 304 | bool "Enable power-sequencing drivers for SPL" |
| 305 | depends on PWRSEQ |
| 306 | help |
| 307 | Power-sequencing drivers provide support for controlling power for |
| 308 | devices. They are typically referenced by a phandle from another |
| 309 | device. When the device is started up, its power sequence can be |
| 310 | initiated. |
| 311 | |
Stefan Roese | 1cdd941 | 2015-03-12 11:22:46 +0100 | [diff] [blame] | 312 | config PCA9551_LED |
| 313 | bool "Enable PCA9551 LED driver" |
| 314 | help |
| 315 | Enable driver for PCA9551 LED controller. This controller |
| 316 | is connected via I2C. So I2C needs to be enabled. |
| 317 | |
| 318 | config PCA9551_I2C_ADDR |
| 319 | hex "I2C address of PCA9551 LED controller" |
| 320 | depends on PCA9551_LED |
| 321 | default 0x60 |
| 322 | help |
| 323 | The I2C address of the PCA9551 LED controller. |
Simon Glass | f991745 | 2015-06-23 15:39:13 -0600 | [diff] [blame] | 324 | |
Patrick Delaunay | c3600e1 | 2018-05-17 15:24:06 +0200 | [diff] [blame] | 325 | config STM32MP_FUSE |
| 326 | bool "Enable STM32MP fuse wrapper providing the fuse API" |
| 327 | depends on ARCH_STM32MP && MISC |
| 328 | default y if CMD_FUSE |
| 329 | help |
| 330 | If you say Y here, you will get support for the fuse API (OTP) |
| 331 | for STM32MP architecture. |
| 332 | This API is needed for CMD_FUSE. |
| 333 | |
Christophe Kerello | 4e280b9 | 2017-09-13 18:00:08 +0200 | [diff] [blame] | 334 | config STM32_RCC |
| 335 | bool "Enable RCC driver for the STM32 SoC's family" |
Trevor Woerner | 71f6354 | 2020-05-06 08:02:42 -0400 | [diff] [blame] | 336 | depends on (ARCH_STM32 || ARCH_STM32MP) && MISC |
Christophe Kerello | 4e280b9 | 2017-09-13 18:00:08 +0200 | [diff] [blame] | 337 | help |
| 338 | Enable the STM32 RCC driver. The RCC block (Reset and Clock Control |
| 339 | block) is responsible of the management of the clock and reset |
| 340 | generation. |
| 341 | This driver is similar to an MFD driver in the Linux kernel. |
| 342 | |
Stephen Warren | bd3ee84 | 2016-09-13 10:45:57 -0600 | [diff] [blame] | 343 | config TEGRA_CAR |
| 344 | bool "Enable support for the Tegra CAR driver" |
| 345 | depends on TEGRA_NO_BPMP |
| 346 | help |
| 347 | The Tegra CAR (Clock and Reset Controller) is a HW module that |
| 348 | controls almost all clocks and resets in a Tegra SoC. |
| 349 | |
Stephen Warren | 73dd5c4 | 2016-08-08 09:41:34 -0600 | [diff] [blame] | 350 | config TEGRA186_BPMP |
| 351 | bool "Enable support for the Tegra186 BPMP driver" |
| 352 | depends on TEGRA186 |
| 353 | help |
| 354 | The Tegra BPMP (Boot and Power Management Processor) is a separate |
| 355 | auxiliary CPU embedded into Tegra to perform power management work, |
| 356 | and controls related features such as clocks, resets, power domains, |
| 357 | PMIC I2C bus, etc. This driver provides the core low-level |
| 358 | communication path by which feature-specific drivers (such as clock) |
| 359 | can make requests to the BPMP. This driver is similar to an MFD |
| 360 | driver in the Linux kernel. |
| 361 | |
Simon Glass | 079ac59 | 2020-12-23 08:11:18 -0700 | [diff] [blame] | 362 | config TEST_DRV |
| 363 | bool "Enable support for test drivers" |
| 364 | default y if SANDBOX |
| 365 | help |
| 366 | This enables drivers and uclasses that provides a way of testing the |
| 367 | operations of memory allocation and driver/uclass methods in driver |
| 368 | model. This should only be enabled for testing as it is not useful for |
| 369 | anything else. |
| 370 | |
Adam Ford | cc3fedb | 2018-08-06 14:26:50 -0500 | [diff] [blame] | 371 | config TWL4030_LED |
| 372 | bool "Enable TWL4030 LED controller" |
| 373 | help |
| 374 | Enable this to add support for the TWL4030 LED controller. |
| 375 | |
Stefan Roese | 8505693 | 2016-01-19 14:05:10 +0100 | [diff] [blame] | 376 | config WINBOND_W83627 |
| 377 | bool "Enable Winbond Super I/O driver" |
| 378 | help |
| 379 | If you say Y here, you will get support for the Winbond |
| 380 | W83627 Super I/O driver. This can be used to enable the |
| 381 | legacy UART or other devices in the Winbond Super IO chips |
| 382 | on X86 platforms. |
| 383 | |
Miao Yan | fcf5c04 | 2016-05-22 19:37:14 -0700 | [diff] [blame] | 384 | config QFW |
| 385 | bool |
| 386 | help |
Asherah Connor | 5b0b43e | 2021-03-19 18:21:40 +1100 | [diff] [blame] | 387 | Hidden option to enable QEMU fw_cfg interface and uclass. This will |
| 388 | be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. |
| 389 | |
| 390 | config QFW_PIO |
| 391 | bool |
| 392 | depends on QFW |
| 393 | help |
| 394 | Hidden option to enable PIO QEMU fw_cfg interface. This will be |
| 395 | selected by the appropriate QEMU board. |
Miao Yan | fcf5c04 | 2016-05-22 19:37:14 -0700 | [diff] [blame] | 396 | |
Asherah Connor | 5830b57 | 2021-03-19 18:21:42 +1100 | [diff] [blame] | 397 | config QFW_MMIO |
| 398 | bool |
| 399 | depends on QFW |
| 400 | help |
| 401 | Hidden option to enable MMIO QEMU fw_cfg interface. This will be |
| 402 | selected by the appropriate QEMU board. |
| 403 | |
mario.six@gdsys.cc | d7e2891 | 2016-06-22 15:14:16 +0200 | [diff] [blame] | 404 | config I2C_EEPROM |
| 405 | bool "Enable driver for generic I2C-attached EEPROMs" |
| 406 | depends on MISC |
| 407 | help |
| 408 | Enable a generic driver for EEPROMs attached via I2C. |
Adam Ford | e3f24d4 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 409 | |
Wenyou Yang | d81a1de | 2017-09-06 13:08:14 +0800 | [diff] [blame] | 410 | |
| 411 | config SPL_I2C_EEPROM |
| 412 | bool "Enable driver for generic I2C-attached EEPROMs for SPL" |
| 413 | depends on MISC && SPL && SPL_DM |
| 414 | help |
| 415 | This option is an SPL-variant of the I2C_EEPROM option. |
| 416 | See the help of I2C_EEPROM for details. |
| 417 | |
Adam Ford | e3f24d4 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 418 | config SYS_I2C_EEPROM_ADDR |
| 419 | hex "Chip address of the EEPROM device" |
Tom Rini | 88cd7d0 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 420 | depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM |
Adam Ford | e3f24d4 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 421 | default 0 |
| 422 | |
Tom Rini | 88cd7d0 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 423 | if I2C_EEPROM |
Adam Ford | e3f24d4 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 424 | |
| 425 | config SYS_I2C_EEPROM_ADDR_OVERFLOW |
| 426 | hex "EEPROM Address Overflow" |
Tom Rini | 5fd4a7e | 2021-12-11 14:55:47 -0500 | [diff] [blame] | 427 | default 0x0 |
Adam Ford | e3f24d4 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 428 | help |
| 429 | EEPROM chips that implement "address overflow" are ones |
| 430 | like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 431 | address and the extra bits end up in the "chip address" bit |
| 432 | slots. This makes a 24WC08 (1Kbyte) chip look like four 256 |
| 433 | byte chips. |
| 434 | |
| 435 | endif |
| 436 | |
Mario Six | 86da8c1 | 2018-04-27 14:53:33 +0200 | [diff] [blame] | 437 | config GDSYS_RXAUI_CTRL |
| 438 | bool "Enable gdsys RXAUI control driver" |
| 439 | depends on MISC |
| 440 | help |
| 441 | Support gdsys FPGA's RXAUI control. |
Mario Six | 7e86242 | 2018-07-31 14:24:15 +0200 | [diff] [blame] | 442 | |
| 443 | config GDSYS_IOEP |
| 444 | bool "Enable gdsys IOEP driver" |
| 445 | depends on MISC |
| 446 | help |
| 447 | Support gdsys FPGA's IO endpoint driver. |
Mario Six | d216631 | 2018-08-06 10:23:46 +0200 | [diff] [blame] | 448 | |
| 449 | config MPC83XX_SERDES |
| 450 | bool "Enable MPC83xx serdes driver" |
| 451 | depends on MISC |
| 452 | help |
| 453 | Support for serdes found on MPC83xx SoCs. |
| 454 | |
Tien Fong Chee | 6203000 | 2018-07-06 16:28:03 +0800 | [diff] [blame] | 455 | config FS_LOADER |
| 456 | bool "Enable loader driver for file system" |
| 457 | help |
| 458 | This is file system generic loader which can be used to load |
| 459 | the file image from the storage into target such as memory. |
| 460 | |
| 461 | The consumer driver would then use this loader to program whatever, |
| 462 | ie. the FPGA device. |
| 463 | |
Keerthy | b071a07 | 2022-01-27 13:16:53 +0100 | [diff] [blame] | 464 | config SPL_FS_LOADER |
| 465 | bool "Enable loader driver for file system" |
| 466 | help |
| 467 | This is file system generic loader which can be used to load |
| 468 | the file image from the storage into target such as memory. |
| 469 | |
| 470 | The consumer driver would then use this loader to program whatever, |
| 471 | ie. the FPGA device. |
| 472 | |
Mario Six | c0a2b08 | 2018-10-04 09:00:54 +0200 | [diff] [blame] | 473 | config GDSYS_SOC |
| 474 | bool "Enable gdsys SOC driver" |
| 475 | depends on MISC |
| 476 | help |
| 477 | Support for gdsys IHS SOC, a simple bus associated with each gdsys |
| 478 | IHS (Integrated Hardware Systems) FPGA, which holds all devices whose |
| 479 | register maps are contained within the FPGA's register map. |
| 480 | |
Mario Six | ab88bd2 | 2018-10-04 09:00:55 +0200 | [diff] [blame] | 481 | config IHS_FPGA |
| 482 | bool "Enable IHS FPGA driver" |
| 483 | depends on MISC |
| 484 | help |
| 485 | Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on |
| 486 | gdsys devices, which supply the majority of the functionality offered |
| 487 | by the devices. This driver supports both CON and CPU variants of the |
| 488 | devices, depending on the device tree entry. |
Tero Kristo | 344eb6d | 2020-02-14 11:18:15 +0200 | [diff] [blame] | 489 | config ESM_K3 |
| 490 | bool "Enable K3 ESM driver" |
| 491 | depends on ARCH_K3 |
| 492 | help |
| 493 | Support ESM (Error Signaling Module) on TI K3 SoCs. |
Mario Six | ab88bd2 | 2018-10-04 09:00:55 +0200 | [diff] [blame] | 494 | |
Eugen Hristev | f816495 | 2019-10-09 09:23:39 +0000 | [diff] [blame] | 495 | config MICROCHIP_FLEXCOM |
| 496 | bool "Enable Microchip Flexcom driver" |
| 497 | depends on MISC |
| 498 | help |
| 499 | The Atmel Flexcom is just a wrapper which embeds a SPI controller, |
| 500 | an I2C controller and an USART. |
| 501 | Only one function can be used at a time and is chosen at boot time |
| 502 | according to the device tree. |
| 503 | |
Tero Kristo | 9d233b4 | 2019-10-24 15:00:46 +0530 | [diff] [blame] | 504 | config K3_AVS0 |
| 505 | depends on ARCH_K3 && SPL_DM_REGULATOR |
| 506 | bool "AVS class 0 support for K3 devices" |
| 507 | help |
| 508 | K3 devices have the optimized voltage values for the main voltage |
| 509 | domains stored in efuse within the VTM IP. This driver reads the |
| 510 | optimized voltage from the efuse, so that it can be programmed |
| 511 | to the PMIC on board. |
| 512 | |
Tero Kristo | 3b36b38 | 2020-02-14 11:18:16 +0200 | [diff] [blame] | 513 | config ESM_PMIC |
| 514 | bool "Enable PMIC ESM driver" |
| 515 | depends on DM_PMIC |
| 516 | help |
| 517 | Support ESM (Error Signal Monitor) on PMIC devices. ESM is used |
| 518 | typically to reboot the board in error condition. |
| 519 | |
Tom Rini | 98ab831 | 2021-12-11 14:55:49 -0500 | [diff] [blame] | 520 | config FSL_IFC |
| 521 | bool |
| 522 | |
Michael Walle | 42595eb | 2022-02-25 18:06:24 +0530 | [diff] [blame] | 523 | config SL28CPLD |
| 524 | bool "Enable Kontron sl28cpld multi-function driver" |
| 525 | depends on DM_I2C |
| 526 | help |
| 527 | Support for the Kontron sl28cpld management controller. This is |
| 528 | the base driver which provides common access methods for the |
| 529 | sub-drivers. |
| 530 | |
Masahiro Yamada | 0b11dbf | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 531 | endmenu |