blob: fa29d69e859a8f4477e11b928bb99225e82a5908 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass6854f872014-11-14 20:56:33 -07002/*
3 * Copyright (C) 2014 Google, Inc
4 *
5 * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
6 *
7 * Modifications are:
8 * Copyright (C) 2003-2004 Linux Networx
9 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
10 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
11 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
12 * Copyright (C) 2005-2006 Tyan
13 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
14 * Copyright (C) 2005-2009 coresystems GmbH
15 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
16 *
17 * PCI Bus Services, see include/linux/pci.h for further explanation.
18 *
19 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
20 * David Mosberger-Tang
21 *
22 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
Simon Glass6854f872014-11-14 20:56:33 -070023 */
24
Simon Glass09387672020-07-02 21:12:30 -060025#define LOG_CATEGORY UCLASS_PCI
26
Simon Glass6854f872014-11-14 20:56:33 -070027#include <common.h>
28#include <bios_emul.h>
Simon Glass52f24232020-05-10 11:40:00 -060029#include <bootstage.h>
Simon Glass3f4e1e82015-11-29 13:17:57 -070030#include <dm.h>
Simon Glass6854f872014-11-14 20:56:33 -070031#include <errno.h>
Simon Glass35a3f872019-12-28 10:44:56 -070032#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060033#include <log.h>
Simon Glass6854f872014-11-14 20:56:33 -070034#include <malloc.h>
35#include <pci.h>
36#include <pci_rom.h>
37#include <vbe.h>
Simon Glassee87ee82016-10-05 20:42:17 -060038#include <video.h>
Simon Glass6854f872014-11-14 20:56:33 -070039#include <video_fb.h>
Simon Glass3cabcf92020-04-08 16:57:35 -060040#include <acpi/acpi_s3.h>
Bin Menga4520022015-07-06 16:31:36 +080041#include <linux/screen_info.h>
Simon Glass6854f872014-11-14 20:56:33 -070042
Bin Meng68769eb2017-04-21 07:24:46 -070043DECLARE_GLOBAL_DATA_PTR;
Bin Meng68769eb2017-04-21 07:24:46 -070044
Simon Glass3f4e1e82015-11-29 13:17:57 -070045__weak bool board_should_run_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070046{
Bin Meng68769eb2017-04-21 07:24:46 -070047#if defined(CONFIG_X86) && defined(CONFIG_HAVE_ACPI_RESUME)
48 if (gd->arch.prev_sleep_state == ACPI_S3) {
49 if (IS_ENABLED(CONFIG_S3_VGA_ROM_RUN))
50 return true;
51 else
52 return false;
53 }
54#endif
55
Simon Glass6854f872014-11-14 20:56:33 -070056 return true;
57}
58
Bin Mengf698baa2016-06-14 02:02:40 -070059__weak bool board_should_load_oprom(struct udevice *dev)
Simon Glass6854f872014-11-14 20:56:33 -070060{
Bin Mengc0aea6b2016-06-14 02:02:39 -070061 return true;
Simon Glass6854f872014-11-14 20:56:33 -070062}
63
64__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
65{
66 return vendev;
67}
68
Simon Glass3f4e1e82015-11-29 13:17:57 -070069static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
Simon Glass6854f872014-11-14 20:56:33 -070070{
Simon Glass3f4e1e82015-11-29 13:17:57 -070071 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Simon Glass6854f872014-11-14 20:56:33 -070072 struct pci_rom_header *rom_header;
73 struct pci_rom_data *rom_data;
Simon Glass40305242014-12-29 19:32:23 -070074 u16 rom_vendor, rom_device;
Bin Mengd57c2f22015-04-24 15:48:03 +080075 u32 rom_class;
Simon Glass6854f872014-11-14 20:56:33 -070076 u32 vendev;
77 u32 mapped_vendev;
78 u32 rom_address;
79
Simon Glass3f4e1e82015-11-29 13:17:57 -070080 vendev = pplat->vendor << 16 | pplat->device;
Simon Glass6854f872014-11-14 20:56:33 -070081 mapped_vendev = board_map_oprom_vendev(vendev);
82 if (vendev != mapped_vendev)
83 debug("Device ID mapped to %#08x\n", mapped_vendev);
84
Bin Meng786a08e2015-07-06 16:31:33 +080085#ifdef CONFIG_VGA_BIOS_ADDR
86 rom_address = CONFIG_VGA_BIOS_ADDR;
Simon Glass6854f872014-11-14 20:56:33 -070087#else
Simon Glass4a2708a2015-01-14 21:37:04 -070088
Simon Glass3f4e1e82015-11-29 13:17:57 -070089 dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
Simon Glass6854f872014-11-14 20:56:33 -070090 if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
91 debug("%s: rom_address=%x\n", __func__, rom_address);
92 return -ENOENT;
93 }
94
95 /* Enable expansion ROM address decoding. */
Simon Glass3f4e1e82015-11-29 13:17:57 -070096 dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
97 rom_address | PCI_ROM_ADDRESS_ENABLE);
Simon Glass6854f872014-11-14 20:56:33 -070098#endif
99 debug("Option ROM address %x\n", rom_address);
Minghuan Lianef2d17f2015-01-22 13:21:55 +0800100 rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
Simon Glass6854f872014-11-14 20:56:33 -0700101
102 debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700103 le16_to_cpu(rom_header->signature),
104 rom_header->size * 512, le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700105
Simon Glass40305242014-12-29 19:32:23 -0700106 if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
Simon Glass6854f872014-11-14 20:56:33 -0700107 printf("Incorrect expansion ROM header signature %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700108 le16_to_cpu(rom_header->signature));
Bin Mengf110da92015-07-08 13:06:41 +0800109#ifndef CONFIG_VGA_BIOS_ADDR
110 /* Disable expansion ROM address decoding */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700111 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
Bin Mengf110da92015-07-08 13:06:41 +0800112#endif
Simon Glass6854f872014-11-14 20:56:33 -0700113 return -EINVAL;
114 }
115
Simon Glass40305242014-12-29 19:32:23 -0700116 rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
117 rom_vendor = le16_to_cpu(rom_data->vendor);
118 rom_device = le16_to_cpu(rom_data->device);
Simon Glass6854f872014-11-14 20:56:33 -0700119
120 debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
Simon Glass40305242014-12-29 19:32:23 -0700121 rom_vendor, rom_device);
Simon Glass6854f872014-11-14 20:56:33 -0700122
123 /* If the device id is mapped, a mismatch is expected */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700124 if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
Simon Glass6854f872014-11-14 20:56:33 -0700125 (vendev == mapped_vendev)) {
126 printf("ID mismatch: vendor ID %04x, device ID %04x\n",
Simon Glass40305242014-12-29 19:32:23 -0700127 rom_vendor, rom_device);
Simon Glassc5caba02014-12-29 19:32:27 -0700128 /* Continue anyway */
Simon Glass6854f872014-11-14 20:56:33 -0700129 }
130
Bin Mengd57c2f22015-04-24 15:48:03 +0800131 rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
132 debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
133 rom_class, rom_data->type);
Simon Glass6854f872014-11-14 20:56:33 -0700134
Simon Glass3f4e1e82015-11-29 13:17:57 -0700135 if (pplat->class != rom_class) {
Bin Mengd57c2f22015-04-24 15:48:03 +0800136 debug("Class Code mismatch ROM %06x, dev %06x\n",
Simon Glass3f4e1e82015-11-29 13:17:57 -0700137 rom_class, pplat->class);
Simon Glass6854f872014-11-14 20:56:33 -0700138 }
139 *hdrp = rom_header;
140
141 return 0;
142}
143
Simon Glassd830b152016-01-15 05:23:22 -0700144/**
145 * pci_rom_load() - Load a ROM image and return a pointer to it
146 *
147 * @rom_header: Pointer to ROM image
148 * @ram_headerp: Returns a pointer to the image in RAM
149 * @allocedp: Returns true if @ram_headerp was allocated and needs
150 * to be freed
151 * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of
152 * the error state. Even if this function returns an error, it may have
153 * allocated memory.
154 */
155static int pci_rom_load(struct pci_rom_header *rom_header,
156 struct pci_rom_header **ram_headerp, bool *allocedp)
Simon Glass6854f872014-11-14 20:56:33 -0700157{
158 struct pci_rom_data *rom_data;
159 unsigned int rom_size;
160 unsigned int image_size = 0;
161 void *target;
162
Simon Glassd830b152016-01-15 05:23:22 -0700163 *allocedp = false;
Simon Glass6854f872014-11-14 20:56:33 -0700164 do {
165 /* Get next image, until we see an x86 version */
166 rom_header = (struct pci_rom_header *)((void *)rom_header +
167 image_size);
168
169 rom_data = (struct pci_rom_data *)((void *)rom_header +
Simon Glass40305242014-12-29 19:32:23 -0700170 le16_to_cpu(rom_header->data));
Simon Glass6854f872014-11-14 20:56:33 -0700171
Simon Glass40305242014-12-29 19:32:23 -0700172 image_size = le16_to_cpu(rom_data->ilen) * 512;
173 } while ((rom_data->type != 0) && (rom_data->indicator == 0));
Simon Glass6854f872014-11-14 20:56:33 -0700174
175 if (rom_data->type != 0)
176 return -EACCES;
177
178 rom_size = rom_header->size * 512;
179
Simon Glassbdc88d42014-12-29 19:32:24 -0700180#ifdef PCI_VGA_RAM_IMAGE_START
Simon Glass6854f872014-11-14 20:56:33 -0700181 target = (void *)PCI_VGA_RAM_IMAGE_START;
Simon Glassbdc88d42014-12-29 19:32:24 -0700182#else
183 target = (void *)malloc(rom_size);
184 if (!target)
185 return -ENOMEM;
Simon Glassd830b152016-01-15 05:23:22 -0700186 *allocedp = true;
Simon Glassbdc88d42014-12-29 19:32:24 -0700187#endif
Simon Glass6854f872014-11-14 20:56:33 -0700188 if (target != rom_header) {
Simon Glassfba7eac2015-01-01 16:18:01 -0700189 ulong start = get_timer(0);
190
Simon Glass6854f872014-11-14 20:56:33 -0700191 debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
192 rom_header, target, rom_size);
193 memcpy(target, rom_header, rom_size);
194 if (memcmp(target, rom_header, rom_size)) {
195 printf("VGA ROM copy failed\n");
196 return -EFAULT;
197 }
Simon Glassfba7eac2015-01-01 16:18:01 -0700198 debug("Copy took %lums\n", get_timer(start));
Simon Glass6854f872014-11-14 20:56:33 -0700199 }
200 *ram_headerp = target;
201
202 return 0;
203}
204
Bin Meng153e1dd2015-08-13 00:29:16 -0700205struct vbe_mode_info mode_info;
Simon Glass6854f872014-11-14 20:56:33 -0700206
Bin Menga4520022015-07-06 16:31:36 +0800207void setup_video(struct screen_info *screen_info)
208{
Bin Menga4520022015-07-06 16:31:36 +0800209 struct vesa_mode_info *vesa = &mode_info.vesa;
210
Bin Meng1e7a0472015-07-30 03:49:13 -0700211 /* Sanity test on VESA parameters */
212 if (!vesa->x_resolution || !vesa->y_resolution)
213 return;
214
Bin Menga4520022015-07-06 16:31:36 +0800215 screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
216
217 screen_info->lfb_width = vesa->x_resolution;
218 screen_info->lfb_height = vesa->y_resolution;
219 screen_info->lfb_depth = vesa->bits_per_pixel;
220 screen_info->lfb_linelength = vesa->bytes_per_scanline;
221 screen_info->lfb_base = vesa->phys_base_ptr;
222 screen_info->lfb_size =
223 ALIGN(screen_info->lfb_linelength * screen_info->lfb_height,
224 65536);
225 screen_info->lfb_size >>= 16;
226 screen_info->red_size = vesa->red_mask_size;
227 screen_info->red_pos = vesa->red_mask_pos;
228 screen_info->green_size = vesa->green_mask_size;
229 screen_info->green_pos = vesa->green_mask_pos;
230 screen_info->blue_size = vesa->blue_mask_size;
231 screen_info->blue_pos = vesa->blue_mask_pos;
232 screen_info->rsvd_size = vesa->reserved_mask_size;
233 screen_info->rsvd_pos = vesa->reserved_mask_pos;
Bin Menga4520022015-07-06 16:31:36 +0800234}
235
Simon Glass3f4e1e82015-11-29 13:17:57 -0700236int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
237 int exec_method)
Simon Glass6854f872014-11-14 20:56:33 -0700238{
Simon Glass3f4e1e82015-11-29 13:17:57 -0700239 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
Andreas Bießmanned488992016-02-16 23:29:31 +0100240 struct pci_rom_header *rom = NULL, *ram = NULL;
Simon Glass6854f872014-11-14 20:56:33 -0700241 int vesa_mode = -1;
Simon Glassd830b152016-01-15 05:23:22 -0700242 bool emulate, alloced;
Simon Glass6854f872014-11-14 20:56:33 -0700243 int ret;
244
245 /* Only execute VGA ROMs */
Simon Glass3f4e1e82015-11-29 13:17:57 -0700246 if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
247 debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
Simon Glass6854f872014-11-14 20:56:33 -0700248 PCI_CLASS_DISPLAY_VGA);
249 return -ENODEV;
250 }
251
Bin Mengf698baa2016-06-14 02:02:40 -0700252 if (!board_should_load_oprom(dev))
Simon Glass595aac92018-10-01 12:22:44 -0600253 return log_msg_ret("Should not load OPROM", -ENXIO);
Simon Glass6854f872014-11-14 20:56:33 -0700254
Simon Glass3f4e1e82015-11-29 13:17:57 -0700255 ret = pci_rom_probe(dev, &rom);
Simon Glass6854f872014-11-14 20:56:33 -0700256 if (ret)
257 return ret;
258
Simon Glassd830b152016-01-15 05:23:22 -0700259 ret = pci_rom_load(rom, &ram, &alloced);
Simon Glass6854f872014-11-14 20:56:33 -0700260 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700261 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700262
Simon Glassd830b152016-01-15 05:23:22 -0700263 if (!board_should_run_oprom(dev)) {
264 ret = -ENXIO;
265 goto err;
266 }
Simon Glass6854f872014-11-14 20:56:33 -0700267
268#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
269 defined(CONFIG_FRAMEBUFFER_VESA_MODE)
270 vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
271#endif
Simon Glass9a99caf2015-01-01 16:18:05 -0700272 debug("Selected vesa mode %#x\n", vesa_mode);
Simon Glassbc17d8f2015-01-27 22:13:34 -0700273
274 if (exec_method & PCI_ROM_USE_NATIVE) {
275#ifdef CONFIG_X86
276 emulate = false;
277#else
278 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
279 printf("BIOS native execution is only available on x86\n");
Simon Glassd830b152016-01-15 05:23:22 -0700280 ret = -ENOSYS;
281 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700282 }
283 emulate = true;
284#endif
285 } else {
286#ifdef CONFIG_BIOSEMU
287 emulate = true;
288#else
289 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
290 printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
Simon Glassd830b152016-01-15 05:23:22 -0700291 ret = -ENOSYS;
292 goto err;
Simon Glassbc17d8f2015-01-27 22:13:34 -0700293 }
294 emulate = false;
295#endif
296 }
297
Simon Glass6854f872014-11-14 20:56:33 -0700298 if (emulate) {
299#ifdef CONFIG_BIOSEMU
300 BE_VGAInfo *info;
301
Simon Glass72826722016-01-17 16:11:09 -0700302 ret = biosemu_setup(dev, &info);
Simon Glass6854f872014-11-14 20:56:33 -0700303 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700304 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700305 biosemu_set_interrupt_handler(0x15, int15_handler);
Simon Glass72826722016-01-17 16:11:09 -0700306 ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
307 true, vesa_mode, &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700308 if (ret)
Simon Glassd830b152016-01-15 05:23:22 -0700309 goto err;
Simon Glass6854f872014-11-14 20:56:33 -0700310#endif
311 } else {
Simon Glass6c456512019-04-25 21:59:08 -0600312#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
Simon Glass6854f872014-11-14 20:56:33 -0700313 bios_set_interrupt_handler(0x15, int15_handler);
314
Simon Glass8beb0bd2015-11-29 13:17:58 -0700315 bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
316 &mode_info);
Simon Glass6854f872014-11-14 20:56:33 -0700317#endif
318 }
Simon Glass9a99caf2015-01-01 16:18:05 -0700319 debug("Final vesa mode %#x\n", mode_info.video_mode);
Simon Glassd830b152016-01-15 05:23:22 -0700320 ret = 0;
Simon Glass6854f872014-11-14 20:56:33 -0700321
Simon Glassd830b152016-01-15 05:23:22 -0700322err:
323 if (alloced)
324 free(ram);
325 return ret;
Simon Glass6854f872014-11-14 20:56:33 -0700326}
Simon Glassee87ee82016-10-05 20:42:17 -0600327
328#ifdef CONFIG_DM_VIDEO
Bin Meng5f6ad022016-10-09 04:14:15 -0700329int vbe_setup_video_priv(struct vesa_mode_info *vesa,
330 struct video_priv *uc_priv,
331 struct video_uc_platdata *plat)
Simon Glassee87ee82016-10-05 20:42:17 -0600332{
333 if (!vesa->x_resolution)
Simon Glass595aac92018-10-01 12:22:44 -0600334 return log_msg_ret("No x resolution", -ENXIO);
Simon Glassee87ee82016-10-05 20:42:17 -0600335 uc_priv->xsize = vesa->x_resolution;
336 uc_priv->ysize = vesa->y_resolution;
Simon Glass06696eb2018-11-29 15:08:52 -0700337 uc_priv->line_length = vesa->bytes_per_scanline;
Simon Glassee87ee82016-10-05 20:42:17 -0600338 switch (vesa->bits_per_pixel) {
339 case 32:
340 case 24:
341 uc_priv->bpix = VIDEO_BPP32;
342 break;
343 case 16:
344 uc_priv->bpix = VIDEO_BPP16;
345 break;
346 default:
347 return -EPROTONOSUPPORT;
348 }
Simon Glass09387672020-07-02 21:12:30 -0600349
350 /* Use double buffering if enabled */
351 if (IS_ENABLED(CONFIG_VIDEO_COPY)) {
352 if (!plat->base)
353 return log_msg_ret("copy", -ENFILE);
354 plat->copy_base = vesa->phys_base_ptr;
355 } else {
356 plat->base = vesa->phys_base_ptr;
357 }
358 log_debug("base = %lx, copy_base = %lx\n", plat->base, plat->copy_base);
Simon Glassee87ee82016-10-05 20:42:17 -0600359 plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
360
361 return 0;
362}
363
364int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
365{
366 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
367 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
368 int ret;
369
370 /* If we are running from EFI or coreboot, this can't work */
Bin Mengf0920e42016-10-09 04:14:12 -0700371 if (!ll_boot_init()) {
372 printf("Not available (previous bootloader prevents it)\n");
Simon Glassee87ee82016-10-05 20:42:17 -0600373 return -EPERM;
Bin Mengf0920e42016-10-09 04:14:12 -0700374 }
Simon Glassee87ee82016-10-05 20:42:17 -0600375 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
376 ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
377 PCI_ROM_ALLOW_FALLBACK);
378 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
379 if (ret) {
380 debug("failed to run video BIOS: %d\n", ret);
381 return ret;
382 }
383
384 ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
385 if (ret) {
Simon Glass09387672020-07-02 21:12:30 -0600386 if (ret == -ENFILE) {
387 /*
388 * See video-uclass.c for how to set up reserved memory
389 * in your video driver
390 */
391 log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n",
392 dev->driver->name);
393 }
394
Simon Glassee87ee82016-10-05 20:42:17 -0600395 debug("No video mode configured\n");
396 return ret;
397 }
398
Bin Meng61130932018-04-11 22:02:18 -0700399 printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
Bin Mengf0920e42016-10-09 04:14:12 -0700400 mode_info.vesa.bits_per_pixel);
401
Simon Glassee87ee82016-10-05 20:42:17 -0600402 return 0;
403}
404#endif