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Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goede44d8ae52015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbell2c7e3b92014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergera26cd042015-05-12 14:46:23 -050021 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010022
Ian Campbellc3be2792014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbellc3be2792014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbellc3be2792014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080038 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020040 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020041 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080042 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010043
Ian Campbellc3be2792014-10-24 21:20:45 +010044config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010045 bool "sun7i (Allwinner A20)"
46 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020049 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010050 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020051 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010052
Hans de Goede5e6bacd2015-04-06 20:55:39 +020053config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010054 bool "sun8i (Allwinner A23)"
55 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080056 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020058 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010059 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080060 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010061
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053062config MACH_SUN8I_A33
63 bool "sun8i (Allwinner A33)"
64 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053067 select SUNXI_GEN_SUN6I
68 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080069 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053070
Jens Kuske1c27b7d2015-11-17 15:12:58 +010071config MACH_SUN8I_H3
72 bool "sun8i (Allwinner H3)"
73 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080074 select CPU_V7_HAS_NONSEC
75 select CPU_V7_HAS_VIRT
Jens Kuske1c27b7d2015-11-17 15:12:58 +010076 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +010077 select SUPPORT_SPL
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080078 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +010079
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020080config MACH_SUN50I
81 bool "sun50i (Allwinner A64)"
82 select ARM64
83 select SUNXI_GEN_SUN6I
84
vishnupatekar762e24a2015-11-29 01:07:19 +080085config MACH_SUN8I_A83T
86 bool "sun8i (Allwinner A83T)"
87 select CPU_V7
88 select SUNXI_GEN_SUN6I
89 select SUPPORT_SPL
90
Hans de Goede1871a8c2015-01-13 19:25:06 +010091config MACH_SUN9I
92 bool "sun9i (Allwinner A80)"
93 select CPU_V7
94 select SUNXI_GEN_SUN6I
95
Ian Campbell2c7e3b92014-10-24 21:20:44 +010096endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +080097
Hans de Goede5e6bacd2015-04-06 20:55:39 +020098# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
99config MACH_SUN8I
100 bool
vishnupatekar762e24a2015-11-29 01:07:19 +0800101 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200102
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800103config DRAM_TYPE
104 int "sunxi dram type"
105 depends on MACH_SUN8I_A83T
106 default 3
107 ---help---
108 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200109
Hans de Goede37781a12014-11-15 19:46:39 +0100110config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100111 int "sunxi dram clock speed"
112 default 312 if MACH_SUN6I || MACH_SUN8I
113 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100114 ---help---
115 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +0100116 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +0100117
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200118if MACH_SUN5I || MACH_SUN7I
119config DRAM_MBUS_CLK
120 int "sunxi mbus clock speed"
121 default 300
122 ---help---
123 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
124
125endif
126
Hans de Goede37781a12014-11-15 19:46:39 +0100127config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100128 int "sunxi dram zq value"
129 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
130 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100131 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100132 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100133
Hans de Goede8975cdf2015-05-13 15:00:46 +0200134config DRAM_ODT_EN
135 bool "sunxi dram odt enable"
136 default n if !MACH_SUN8I_A23
137 default y if MACH_SUN8I_A23
138 ---help---
139 Select this to enable dram odt (on die termination).
140
Hans de Goede8ffc4872015-01-17 14:24:55 +0100141if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
142config DRAM_EMR1
143 int "sunxi dram emr1 value"
144 default 0 if MACH_SUN4I
145 default 4 if MACH_SUN5I || MACH_SUN7I
146 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100147 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200148
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200149config DRAM_TPR3
150 hex "sunxi dram tpr3 value"
151 default 0
152 ---help---
153 Set the dram controller tpr3 parameter. This parameter configures
154 the delay on the command lane and also phase shifts, which are
155 applied for sampling incoming read data. The default value 0
156 means that no phase/delay adjustments are necessary. Properly
157 configuring this parameter increases reliability at high DRAM
158 clock speeds.
159
160config DRAM_DQS_GATING_DELAY
161 hex "sunxi dram dqs_gating_delay value"
162 default 0
163 ---help---
164 Set the dram controller dqs_gating_delay parmeter. Each byte
165 encodes the DQS gating delay for each byte lane. The delay
166 granularity is 1/4 cycle. For example, the value 0x05060606
167 means that the delay is 5 quarter-cycles for one lane (1.25
168 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
169 The default value 0 means autodetection. The results of hardware
170 autodetection are not very reliable and depend on the chip
171 temperature (sometimes producing different results on cold start
172 and warm reboot). But the accuracy of hardware autodetection
173 is usually good enough, unless running at really high DRAM
174 clocks speeds (up to 600MHz). If unsure, keep as 0.
175
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200176choice
177 prompt "sunxi dram timings"
178 default DRAM_TIMINGS_VENDOR_MAGIC
179 ---help---
180 Select the timings of the DDR3 chips.
181
182config DRAM_TIMINGS_VENDOR_MAGIC
183 bool "Magic vendor timings from Android"
184 ---help---
185 The same DRAM timings as in the Allwinner boot0 bootloader.
186
187config DRAM_TIMINGS_DDR3_1066F_1333H
188 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
189 ---help---
190 Use the timings of the standard JEDEC DDR3-1066F speed bin for
191 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
192 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
193 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
194 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
195 that down binning to DDR3-1066F is supported (because DDR3-1066F
196 uses a bit faster timings than DDR3-1333H).
197
198config DRAM_TIMINGS_DDR3_800E_1066G_1333J
199 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
200 ---help---
201 Use the timings of the slowest possible JEDEC speed bin for the
202 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
203 DDR3-800E, DDR3-1066G or DDR3-1333J.
204
205endchoice
206
Hans de Goede37781a12014-11-15 19:46:39 +0100207endif
208
Hans de Goede8975cdf2015-05-13 15:00:46 +0200209if MACH_SUN8I_A23
210config DRAM_ODT_CORRECTION
211 int "sunxi dram odt correction value"
212 default 0
213 ---help---
214 Set the dram odt correction value (range -255 - 255). In allwinner
215 fex files, this option is found in bits 8-15 of the u32 odt_en variable
216 in the [dram] section. When bit 31 of the odt_en variable is set
217 then the correction is negative. Usually the value for this is 0.
218endif
219
Iain Patone71b4222015-03-28 10:26:38 +0000220config SYS_CLK_FREQ
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200221 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000222 default 912000000 if MACH_SUN7I
223 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
224
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800225config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100226 default "sun4i" if MACH_SUN4I
227 default "sun5i" if MACH_SUN5I
228 default "sun6i" if MACH_SUN6I
229 default "sun7i" if MACH_SUN7I
230 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100231 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200232 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200233
Masahiro Yamadadd840582014-07-30 14:08:14 +0900234config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900235 default "sunxi"
236
237config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900238 default "sunxi"
239
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200240config UART0_PORT_F
241 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200242 default n
243 ---help---
244 Repurpose the SD card slot for getting access to the UART0 serial
245 console. Primarily useful only for low level u-boot debugging on
246 tablets, where normal UART0 is difficult to access and requires
247 device disassembly and/or soldering. As the SD card can't be used
248 at the same time, the system can be only booted in the FEL mode.
249 Only enable this if you really know what you are doing.
250
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200251config OLD_SUNXI_KERNEL_COMPAT
252 boolean "Enable workarounds for booting old kernels"
253 default n
254 ---help---
255 Set this to enable various workarounds for old kernels, this results in
256 sub-optimal settings for newer kernels, only enable if needed.
257
Maxime Ripard44c79872015-10-15 22:04:07 +0200258config MMC
259 depends on !UART0_PORT_F
260 default y if ARCH_SUNXI
261
Hans de Goedecd821132014-10-02 20:29:26 +0200262config MMC0_CD_PIN
263 string "Card detect pin for mmc0"
264 default ""
265 ---help---
266 Set the card detect pin for mmc0, leave empty to not use cd. This
267 takes a string in the format understood by sunxi_name_to_gpio, e.g.
268 PH1 for pin 1 of port H.
269
270config MMC1_CD_PIN
271 string "Card detect pin for mmc1"
272 default ""
273 ---help---
274 See MMC0_CD_PIN help text.
275
276config MMC2_CD_PIN
277 string "Card detect pin for mmc2"
278 default ""
279 ---help---
280 See MMC0_CD_PIN help text.
281
282config MMC3_CD_PIN
283 string "Card detect pin for mmc3"
284 default ""
285 ---help---
286 See MMC0_CD_PIN help text.
287
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100288config MMC1_PINS
289 string "Pins for mmc1"
290 default ""
291 ---help---
292 Set the pins used for mmc1, when applicable. This takes a string in the
293 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
294
295config MMC2_PINS
296 string "Pins for mmc2"
297 default ""
298 ---help---
299 See MMC1_PINS help text.
300
301config MMC3_PINS
302 string "Pins for mmc3"
303 default ""
304 ---help---
305 See MMC1_PINS help text.
306
Hans de Goede2ccfac02014-10-02 20:43:50 +0200307config MMC_SUNXI_SLOT_EXTRA
308 int "mmc extra slot number"
309 default -1
310 ---help---
311 sunxi builds always enable mmc0, some boards also have a second sdcard
312 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
313 support for this.
314
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200315config INITIAL_USB_SCAN_DELAY
316 int "delay initial usb scan by x ms to allow builtin devices to init"
317 default 0
318 ---help---
319 Some boards have on board usb devices which need longer than the
320 USB spec's 1 second to connect from board powerup. Set this config
321 option to a non 0 value to add an extra delay before the first usb
322 bus scan.
323
Hans de Goede4458b7a2015-01-07 15:26:06 +0100324config USB0_VBUS_PIN
325 string "Vbus enable pin for usb0 (otg)"
326 default ""
327 ---help---
328 Set the Vbus enable pin for usb0 (otg). This takes a string in the
329 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
330
Hans de Goede52defe82015-02-16 22:13:43 +0100331config USB0_VBUS_DET
332 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100333 default ""
334 ---help---
335 Set the Vbus detect pin for usb0 (otg). This takes a string in the
336 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
337
Hans de Goede48c06c92015-06-14 17:29:53 +0200338config USB0_ID_DET
339 string "ID detect pin for usb0 (otg)"
340 default ""
341 ---help---
342 Set the ID detect pin for usb0 (otg). This takes a string in the
343 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
344
Hans de Goede115200c2014-11-07 16:09:00 +0100345config USB1_VBUS_PIN
346 string "Vbus enable pin for usb1 (ehci0)"
347 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100348 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100349 ---help---
350 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
351 a string in the format understood by sunxi_name_to_gpio, e.g.
352 PH1 for pin 1 of port H.
353
354config USB2_VBUS_PIN
355 string "Vbus enable pin for usb2 (ehci1)"
356 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100357 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100358 ---help---
359 See USB1_VBUS_PIN help text.
360
Hans de Goede60fa6302016-03-18 08:42:01 +0100361config USB3_VBUS_PIN
362 string "Vbus enable pin for usb3 (ehci2)"
363 default ""
364 ---help---
365 See USB1_VBUS_PIN help text.
366
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200367config I2C0_ENABLE
368 bool "Enable I2C/TWI controller 0"
369 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
370 default n if MACH_SUN6I || MACH_SUN8I
371 ---help---
372 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
373 its clock and setting up the bus. This is especially useful on devices
374 with slaves connected to the bus or with pins exposed through e.g. an
375 expansion port/header.
376
377config I2C1_ENABLE
378 bool "Enable I2C/TWI controller 1"
379 default n
380 ---help---
381 See I2C0_ENABLE help text.
382
383config I2C2_ENABLE
384 bool "Enable I2C/TWI controller 2"
385 default n
386 ---help---
387 See I2C0_ENABLE help text.
388
389if MACH_SUN6I || MACH_SUN7I
390config I2C3_ENABLE
391 bool "Enable I2C/TWI controller 3"
392 default n
393 ---help---
394 See I2C0_ENABLE help text.
395endif
396
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100397if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100398config R_I2C_ENABLE
399 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100400 # This is used for the pmic on H3
401 default y if SY8106A_POWER
Jelle van der Waa9d082682016-01-14 14:06:26 +0100402 ---help---
403 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100404endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100405
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200406if MACH_SUN7I
407config I2C4_ENABLE
408 bool "Enable I2C/TWI controller 4"
409 default n
410 ---help---
411 See I2C0_ENABLE help text.
412endif
413
Hans de Goede2fcf0332015-04-25 17:25:14 +0200414config AXP_GPIO
415 boolean "Enable support for gpio-s on axp PMICs"
416 default n
417 ---help---
418 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
419
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200420config VIDEO
Hans de Goede2dae8002014-12-21 16:28:32 +0100421 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
vishnupatekar762e24a2015-11-29 01:07:19 +0800422 depends on !MACH_SUN8I_A83T
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200423 default y
424 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100425 Say Y here to add support for using a cfb console on the HDMI, LCD
426 or VGA output found on most sunxi devices. See doc/README.video for
427 info on how to select the video output and mode.
428
Hans de Goede2fbf0912014-12-23 23:04:35 +0100429config VIDEO_HDMI
430 boolean "HDMI output support"
431 depends on VIDEO && !MACH_SUN8I
432 default y
433 ---help---
434 Say Y here to add support for outputting video over HDMI.
435
Hans de Goeded9786d22014-12-25 13:58:06 +0100436config VIDEO_VGA
437 boolean "VGA output support"
438 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
439 default n
440 ---help---
441 Say Y here to add support for outputting video over VGA.
442
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100443config VIDEO_VGA_VIA_LCD
444 boolean "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800445 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100446 default n
447 ---help---
448 Say Y here to add support for external DACs connected to the parallel
449 LCD interface driving a VGA connector, such as found on the
450 Olimex A13 boards.
451
Hans de Goedefb75d972015-01-25 15:33:07 +0100452config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
453 boolean "Force sync active high for VGA via LCD controller support"
454 depends on VIDEO_VGA_VIA_LCD
455 default n
456 ---help---
457 Say Y here if you've a board which uses opendrain drivers for the vga
458 hsync and vsync signals. Opendrain drivers cannot generate steep enough
459 positive edges for a stable video output, so on boards with opendrain
460 drivers the sync signals must always be active high.
461
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800462config VIDEO_VGA_EXTERNAL_DAC_EN
463 string "LCD panel power enable pin"
464 depends on VIDEO_VGA_VIA_LCD
465 default ""
466 ---help---
467 Set the enable pin for the external VGA DAC. This takes a string in the
468 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
469
Hans de Goede39920c82015-08-03 19:20:26 +0200470config VIDEO_COMPOSITE
471 boolean "Composite video output support"
472 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
473 default n
474 ---help---
475 Say Y here to add support for outputting composite video.
476
Hans de Goede2dae8002014-12-21 16:28:32 +0100477config VIDEO_LCD_MODE
478 string "LCD panel timing details"
479 depends on VIDEO
480 default ""
481 ---help---
482 LCD panel timing details string, leave empty if there is no LCD panel.
483 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
484 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200485 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100486
Hans de Goede65150322015-01-13 13:21:46 +0100487config VIDEO_LCD_DCLK_PHASE
488 int "LCD panel display clock phase"
489 depends on VIDEO
490 default 1
491 ---help---
492 Select LCD panel display clock phase shift, range 0-3.
493
Hans de Goede2dae8002014-12-21 16:28:32 +0100494config VIDEO_LCD_POWER
495 string "LCD panel power enable pin"
496 depends on VIDEO
497 default ""
498 ---help---
499 Set the power enable pin for the LCD panel. This takes a string in the
500 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
501
Hans de Goede242e3d82015-02-16 17:26:41 +0100502config VIDEO_LCD_RESET
503 string "LCD panel reset pin"
504 depends on VIDEO
505 default ""
506 ---help---
507 Set the reset pin for the LCD panel. This takes a string in the format
508 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
509
Hans de Goede2dae8002014-12-21 16:28:32 +0100510config VIDEO_LCD_BL_EN
511 string "LCD panel backlight enable pin"
512 depends on VIDEO
513 default ""
514 ---help---
515 Set the backlight enable pin for the LCD panel. This takes a string in the
516 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
517 port H.
518
519config VIDEO_LCD_BL_PWM
520 string "LCD panel backlight pwm pin"
521 depends on VIDEO
522 default ""
523 ---help---
524 Set the backlight pwm pin for the LCD panel. This takes a string in the
525 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200526
Hans de Goedea7403ae2015-01-22 21:02:42 +0100527config VIDEO_LCD_BL_PWM_ACTIVE_LOW
528 bool "LCD panel backlight pwm is inverted"
529 depends on VIDEO
530 default y
531 ---help---
532 Set this if the backlight pwm output is active low.
533
Hans de Goede55410082015-02-16 17:23:25 +0100534config VIDEO_LCD_PANEL_I2C
535 bool "LCD panel needs to be configured via i2c"
536 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100537 default n
Hans de Goede55410082015-02-16 17:23:25 +0100538 ---help---
539 Say y here if the LCD panel needs to be configured via i2c. This
540 will add a bitbang i2c controller using gpios to talk to the LCD.
541
542config VIDEO_LCD_PANEL_I2C_SDA
543 string "LCD panel i2c interface SDA pin"
544 depends on VIDEO_LCD_PANEL_I2C
545 default "PG12"
546 ---help---
547 Set the SDA pin for the LCD i2c interface. This takes a string in the
548 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
549
550config VIDEO_LCD_PANEL_I2C_SCL
551 string "LCD panel i2c interface SCL pin"
552 depends on VIDEO_LCD_PANEL_I2C
553 default "PG10"
554 ---help---
555 Set the SCL pin for the LCD i2c interface. This takes a string in the
556 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
557
Hans de Goede213480e2015-01-01 22:04:34 +0100558
559# Note only one of these may be selected at a time! But hidden choices are
560# not supported by Kconfig
561config VIDEO_LCD_IF_PARALLEL
562 bool
563
564config VIDEO_LCD_IF_LVDS
565 bool
566
567
568choice
569 prompt "LCD panel support"
570 depends on VIDEO
571 ---help---
572 Select which type of LCD panel to support.
573
574config VIDEO_LCD_PANEL_PARALLEL
575 bool "Generic parallel interface LCD panel"
576 select VIDEO_LCD_IF_PARALLEL
577
578config VIDEO_LCD_PANEL_LVDS
579 bool "Generic lvds interface LCD panel"
580 select VIDEO_LCD_IF_LVDS
581
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200582config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
583 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
584 select VIDEO_LCD_SSD2828
585 select VIDEO_LCD_IF_PARALLEL
586 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200587 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
588
589config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
590 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
591 select VIDEO_LCD_ANX9804
592 select VIDEO_LCD_IF_PARALLEL
593 select VIDEO_LCD_PANEL_I2C
594 ---help---
595 Select this for eDP LCD panels with 4 lanes running at 1.62G,
596 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200597
Hans de Goede27515b22015-01-20 09:23:36 +0100598config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
599 bool "Hitachi tx18d42vm LCD panel"
600 select VIDEO_LCD_HITACHI_TX18D42VM
601 select VIDEO_LCD_IF_LVDS
602 ---help---
603 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
604
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100605config VIDEO_LCD_TL059WV5C0
606 bool "tl059wv5c0 LCD panel"
607 select VIDEO_LCD_PANEL_I2C
608 select VIDEO_LCD_IF_PARALLEL
609 ---help---
610 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
611 Aigo M60/M608/M606 tablets.
612
Hans de Goede213480e2015-01-01 22:04:34 +0100613endchoice
614
615
Hans de Goedec13f60d2015-01-25 12:10:48 +0100616config GMAC_TX_DELAY
617 int "GMAC Transmit Clock Delay Chain"
618 default 0
619 ---help---
620 Set the GMAC Transmit Clock Delay Chain value.
621
Hans de Goedeff42d102015-09-13 13:02:48 +0200622config SPL_STACK_R_ADDR
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200623 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200624 default 0x2fe00000 if MACH_SUN9I
625
Masahiro Yamadadd840582014-07-30 14:08:14 +0900626endif