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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
19 help
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
23 access the device.
24
25config TPL_MISC
26 bool "Enable Driver Model for Misc drivers in TPL"
27 depends on TPL_DM
28 help
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
32 access the device.
33
Thomas Chouca844dd2015-10-14 08:43:31 +080034config ALTERA_SYSID
35 bool "Altera Sysid support"
36 depends on MISC
37 help
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
40
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020041config ATSHA204A
42 bool "Support for Atmel ATSHA204A module"
Pali Rohár467f0c42022-04-12 11:20:44 +020043 select BITREVERSE
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020044 depends on MISC
45 help
46 Enable support for I2C connected Atmel's ATSHA204A
47 CryptoAuthentication module found for example on the Turris Omnia
48 board.
49
Tim Harvey8479b9e2022-03-07 16:24:04 -080050config GATEWORKS_SC
51 bool "Gateworks System Controller Support"
52 depends on MISC
53 help
54 Enable access for the Gateworks System Controller used on Gateworks
55 boards to provide a boot watchdog, power control, temperature monitor,
56 voltage ADCs, and EEPROM.
57
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020058config ROCKCHIP_EFUSE
59 bool "Rockchip e-fuse support"
60 depends on MISC
61 help
62 Enable (read-only) access for the e-fuse block found in Rockchip
63 SoCs: accesses can either be made using byte addressing and a length
64 or through child-nodes that are generated based on the e-fuse map
65 retrieved from the DTS.
66
67 This driver currently supports the RK3399 only, but can easily be
68 extended (by porting the read function from the Linux kernel sources)
69 to support other recent Rockchip devices.
70
Finley Xiaoa907dc32019-09-25 17:57:49 +020071config ROCKCHIP_OTP
72 bool "Rockchip OTP Support"
73 depends on MISC
74 help
75 Enable (read-only) access for the one-time-programmable memory block
76 found in Rockchip SoCs: accesses can either be made using byte
77 addressing and a length or through child-nodes that are generated
78 based on the e-fuse map retrieved from the DTS.
79
Pragnesh Patel05307212020-05-29 11:33:21 +053080config SIFIVE_OTP
81 bool "SiFive eMemory OTP driver"
82 depends on MISC
83 help
84 Enable support for reading and writing the eMemory OTP on the
85 SiFive SoCs.
86
Liviu Dudau0fabfeb2018-09-28 13:43:31 +010087config VEXPRESS_CONFIG
88 bool "Enable support for Arm Versatile Express config bus"
89 depends on MISC
90 help
91 If you say Y here, you will get support for accessing the
92 configuration bus on the Arm Versatile Express boards via
93 a sysreg driver.
94
Simon Glass6fb9ac12015-02-13 12:20:47 -070095config CMD_CROS_EC
96 bool "Enable crosec command"
97 depends on CROS_EC
98 help
99 Enable command-line access to the Chrome OS EC (Embedded
100 Controller). This provides the 'crosec' command which has
101 a number of sub-commands for performing EC tasks such as
102 updating its flash, accessing a small saved context area
103 and talking to the I2C bus behind the EC (if there is one).
104
105config CROS_EC
106 bool "Enable Chrome OS EC"
107 help
108 Enable access to the Chrome OS EC. This is a separate
109 microcontroller typically available on a SPI bus on Chromebooks. It
110 provides access to the keyboard, some internal storage and may
111 control access to the battery and main PMIC depending on the
112 device. You can use the 'crosec' command to access it.
113
Simon Glassaaba7032018-11-18 08:14:27 -0700114config SPL_CROS_EC
115 bool "Enable Chrome OS EC in SPL"
Adam Forda0746672019-08-24 13:50:34 -0500116 depends on SPL
Simon Glassaaba7032018-11-18 08:14:27 -0700117 help
118 Enable access to the Chrome OS EC in SPL. This is a separate
119 microcontroller typically available on a SPI bus on Chromebooks. It
120 provides access to the keyboard, some internal storage and may
121 control access to the battery and main PMIC depending on the
122 device. You can use the 'crosec' command to access it.
123
124config TPL_CROS_EC
125 bool "Enable Chrome OS EC in TPL"
Adam Forda0746672019-08-24 13:50:34 -0500126 depends on TPL
Simon Glassaaba7032018-11-18 08:14:27 -0700127 help
128 Enable access to the Chrome OS EC in TPL. This is a separate
129 microcontroller typically available on a SPI bus on Chromebooks. It
130 provides access to the keyboard, some internal storage and may
131 control access to the battery and main PMIC depending on the
132 device. You can use the 'crosec' command to access it.
133
Simon Glass6fb9ac12015-02-13 12:20:47 -0700134config CROS_EC_I2C
135 bool "Enable Chrome OS EC I2C driver"
136 depends on CROS_EC
137 help
138 Enable I2C access to the Chrome OS EC. This is used on older
139 ARM Chromebooks such as snow and spring before the standard bus
140 changed to SPI. The EC will accept commands across the I2C using
141 a special message protocol, and provide responses.
142
143config CROS_EC_LPC
144 bool "Enable Chrome OS EC LPC driver"
145 depends on CROS_EC
146 help
147 Enable I2C access to the Chrome OS EC. This is used on x86
148 Chromebooks such as link and falco. The keyboard is provided
149 through a legacy port interface, so on x86 machines the main
150 function of the EC is power and thermal management.
151
Simon Glassaaba7032018-11-18 08:14:27 -0700152config SPL_CROS_EC_LPC
153 bool "Enable Chrome OS EC LPC driver in SPL"
154 depends on CROS_EC
155 help
156 Enable I2C access to the Chrome OS EC. This is used on x86
157 Chromebooks such as link and falco. The keyboard is provided
158 through a legacy port interface, so on x86 machines the main
159 function of the EC is power and thermal management.
160
161config TPL_CROS_EC_LPC
162 bool "Enable Chrome OS EC LPC driver in TPL"
163 depends on CROS_EC
164 help
165 Enable I2C access to the Chrome OS EC. This is used on x86
166 Chromebooks such as link and falco. The keyboard is provided
167 through a legacy port interface, so on x86 machines the main
168 function of the EC is power and thermal management.
169
Simon Glass47cb8c62015-03-26 09:29:40 -0600170config CROS_EC_SANDBOX
171 bool "Enable Chrome OS EC sandbox driver"
172 depends on CROS_EC && SANDBOX
173 help
174 Enable a sandbox emulation of the Chrome OS EC. This supports
175 keyboard (use the -l flag to enable the LCD), verified boot context,
176 EC flash read/write/erase support and a few other things. It is
177 enough to perform a Chrome OS verified boot on sandbox.
178
Simon Glassaaba7032018-11-18 08:14:27 -0700179config SPL_CROS_EC_SANDBOX
180 bool "Enable Chrome OS EC sandbox driver in SPL"
181 depends on SPL_CROS_EC && SANDBOX
182 help
183 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
184 keyboard (use the -l flag to enable the LCD), verified boot context,
185 EC flash read/write/erase support and a few other things. It is
186 enough to perform a Chrome OS verified boot on sandbox.
187
188config TPL_CROS_EC_SANDBOX
189 bool "Enable Chrome OS EC sandbox driver in TPL"
190 depends on TPL_CROS_EC && SANDBOX
191 help
192 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
193 keyboard (use the -l flag to enable the LCD), verified boot context,
194 EC flash read/write/erase support and a few other things. It is
195 enough to perform a Chrome OS verified boot on sandbox.
196
Simon Glass6fb9ac12015-02-13 12:20:47 -0700197config CROS_EC_SPI
198 bool "Enable Chrome OS EC SPI driver"
199 depends on CROS_EC
200 help
201 Enable SPI access to the Chrome OS EC. This is used on newer
202 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
203 provides a faster and more robust interface than I2C but the bugs
204 are less interesting.
205
Simon Glass879704d2017-05-17 03:25:02 -0600206config DS4510
207 bool "Enable support for DS4510 CPU supervisor"
208 help
209 Enable support for the Maxim DS4510 CPU supervisor. It has an
210 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
211 and a configurable timer for the supervisor function. The device is
212 connected over I2C.
213
Peng Fanc12e0d92015-08-26 15:41:33 +0800214config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530215 bool "Enable FSL SEC_MON Driver"
216 help
217 Freescale Security Monitor block is responsible for monitoring
218 system states.
219 Security Monitor can be transitioned on any security failures,
220 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100221
Simon Glass79d66a62019-12-06 21:41:58 -0700222config IRQ
Wasim Khan182c5f12021-03-08 16:48:13 +0100223 bool "Interrupt controller"
Simon Glass79d66a62019-12-06 21:41:58 -0700224 help
Wasim Khan182c5f12021-03-08 16:48:13 +0100225 This enables support for interrupt controllers, including ITSS.
Simon Glass79d66a62019-12-06 21:41:58 -0700226 Some devices have extra features, such as Apollo Lake. The
227 device has its own uclass since there are several operations
228 involved.
229
Paul Burtonb5392c52018-12-16 19:25:19 -0300230config JZ4780_EFUSE
231 bool "Ingenic JZ4780 eFUSE support"
232 depends on ARCH_JZ47XX
233 help
234 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
235
Peng Fan3e020f02015-08-27 14:49:05 +0800236config MXC_OCOTP
237 bool "Enable MXC OCOTP Driver"
Peng Fan994ab732019-07-22 01:24:55 +0000238 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100239 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800240 help
241 If you say Y here, you will get support for the One Time
242 Programmable memory pages that are stored on the some
243 Freescale i.MX processors.
244
Michael Scott33e9a692021-09-25 19:49:28 +0300245config SPL_MXC_OCOTP
246 bool "Enable MXC OCOTP driver in SPL"
247 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
248 default y
249 help
250 If you say Y here, you will get support for the One Time
251 Programmable memory pages, that are stored on some
252 Freescale i.MX processors, in SPL.
253
Stefan Roese4cf9e462016-07-19 07:45:46 +0200254config NUVOTON_NCT6102D
255 bool "Enable Nuvoton NCT6102D Super I/O driver"
256 help
257 If you say Y here, you will get support for the Nuvoton
258 NCT6102D Super I/O driver. This can be used to enable or
259 disable the legacy UART, the watchdog or other devices
260 in the Nuvoton Super IO chips on X86 platforms.
261
Simon Glass5bee27a2019-12-06 21:41:55 -0700262config P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200263 bool "Intel Primary to Sideband Bridge"
Simon Glass5bee27a2019-12-06 21:41:55 -0700264 depends on X86 || SANDBOX
265 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200266 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass5bee27a2019-12-06 21:41:55 -0700267 abbreviated to P2SB. The P2SB is used to access various peripherals
268 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
269 space. The space is segmented into different channels and peripherals
270 are accessed by device-specific means within those channels. Devices
271 should be added in the device tree as subnodes of the P2SB. A
272 Peripheral Channel Register? (PCR) API is provided to access those
273 devices - see pcr_readl(), etc.
274
275config SPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200276 bool "Intel Primary to Sideband Bridge in SPL"
Simon Glass5bee27a2019-12-06 21:41:55 -0700277 depends on SPL && (X86 || SANDBOX)
278 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200279 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700280 through memory-mapped I/O in a large chunk of PCI space. The space is
281 segmented into different channels and peripherals are accessed by
282 device-specific means within those channels. Devices should be added
283 in the device tree as subnodes of the p2sb.
284
285config TPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200286 bool "Intel Primary to Sideband Bridge in TPL"
Simon Glass5bee27a2019-12-06 21:41:55 -0700287 depends on TPL && (X86 || SANDBOX)
288 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200289 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700290 through memory-mapped I/O in a large chunk of PCI space. The space is
291 segmented into different channels and peripherals are accessed by
292 device-specific means within those channels. Devices should be added
293 in the device tree as subnodes of the p2sb.
294
Simon Glass5fd6bad2016-01-21 19:43:31 -0700295config PWRSEQ
296 bool "Enable power-sequencing drivers"
297 depends on DM
298 help
299 Power-sequencing drivers provide support for controlling power for
300 devices. They are typically referenced by a phandle from another
301 device. When the device is started up, its power sequence can be
302 initiated.
303
304config SPL_PWRSEQ
305 bool "Enable power-sequencing drivers for SPL"
306 depends on PWRSEQ
307 help
308 Power-sequencing drivers provide support for controlling power for
309 devices. They are typically referenced by a phandle from another
310 device. When the device is started up, its power sequence can be
311 initiated.
312
Stefan Roese1cdd9412015-03-12 11:22:46 +0100313config PCA9551_LED
314 bool "Enable PCA9551 LED driver"
315 help
316 Enable driver for PCA9551 LED controller. This controller
317 is connected via I2C. So I2C needs to be enabled.
318
319config PCA9551_I2C_ADDR
320 hex "I2C address of PCA9551 LED controller"
321 depends on PCA9551_LED
322 default 0x60
323 help
324 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600325
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200326config STM32MP_FUSE
327 bool "Enable STM32MP fuse wrapper providing the fuse API"
328 depends on ARCH_STM32MP && MISC
329 default y if CMD_FUSE
330 help
331 If you say Y here, you will get support for the fuse API (OTP)
332 for STM32MP architecture.
333 This API is needed for CMD_FUSE.
334
Christophe Kerello4e280b92017-09-13 18:00:08 +0200335config STM32_RCC
336 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner71f63542020-05-06 08:02:42 -0400337 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200338 help
339 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
340 block) is responsible of the management of the clock and reset
341 generation.
342 This driver is similar to an MFD driver in the Linux kernel.
343
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600344config TEGRA_CAR
345 bool "Enable support for the Tegra CAR driver"
346 depends on TEGRA_NO_BPMP
347 help
348 The Tegra CAR (Clock and Reset Controller) is a HW module that
349 controls almost all clocks and resets in a Tegra SoC.
350
Stephen Warren73dd5c42016-08-08 09:41:34 -0600351config TEGRA186_BPMP
352 bool "Enable support for the Tegra186 BPMP driver"
353 depends on TEGRA186
354 help
355 The Tegra BPMP (Boot and Power Management Processor) is a separate
356 auxiliary CPU embedded into Tegra to perform power management work,
357 and controls related features such as clocks, resets, power domains,
358 PMIC I2C bus, etc. This driver provides the core low-level
359 communication path by which feature-specific drivers (such as clock)
360 can make requests to the BPMP. This driver is similar to an MFD
361 driver in the Linux kernel.
362
Simon Glass079ac592020-12-23 08:11:18 -0700363config TEST_DRV
364 bool "Enable support for test drivers"
365 default y if SANDBOX
366 help
367 This enables drivers and uclasses that provides a way of testing the
368 operations of memory allocation and driver/uclass methods in driver
369 model. This should only be enabled for testing as it is not useful for
370 anything else.
371
Adam Fordcc3fedb2018-08-06 14:26:50 -0500372config TWL4030_LED
373 bool "Enable TWL4030 LED controller"
374 help
375 Enable this to add support for the TWL4030 LED controller.
376
Stefan Roese85056932016-01-19 14:05:10 +0100377config WINBOND_W83627
378 bool "Enable Winbond Super I/O driver"
379 help
380 If you say Y here, you will get support for the Winbond
381 W83627 Super I/O driver. This can be used to enable the
382 legacy UART or other devices in the Winbond Super IO chips
383 on X86 platforms.
384
Miao Yanfcf5c042016-05-22 19:37:14 -0700385config QFW
386 bool
387 help
Asherah Connor5b0b43e2021-03-19 18:21:40 +1100388 Hidden option to enable QEMU fw_cfg interface and uclass. This will
389 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
390
391config QFW_PIO
392 bool
393 depends on QFW
394 help
395 Hidden option to enable PIO QEMU fw_cfg interface. This will be
396 selected by the appropriate QEMU board.
Miao Yanfcf5c042016-05-22 19:37:14 -0700397
Asherah Connor5830b572021-03-19 18:21:42 +1100398config QFW_MMIO
399 bool
400 depends on QFW
401 help
402 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
403 selected by the appropriate QEMU board.
404
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200405config I2C_EEPROM
406 bool "Enable driver for generic I2C-attached EEPROMs"
407 depends on MISC
408 help
409 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500410
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800411
412config SPL_I2C_EEPROM
413 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
414 depends on MISC && SPL && SPL_DM
415 help
416 This option is an SPL-variant of the I2C_EEPROM option.
417 See the help of I2C_EEPROM for details.
418
Adam Forde3f24d42017-08-13 09:00:28 -0500419config SYS_I2C_EEPROM_ADDR
420 hex "Chip address of the EEPROM device"
Tom Rini88cd7d02021-08-17 17:59:45 -0400421 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500422 default 0
423
Tom Rini88cd7d02021-08-17 17:59:45 -0400424if I2C_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500425
426config SYS_I2C_EEPROM_ADDR_OVERFLOW
427 hex "EEPROM Address Overflow"
Tom Rini5fd4a7e2021-12-11 14:55:47 -0500428 default 0x0
Adam Forde3f24d42017-08-13 09:00:28 -0500429 help
430 EEPROM chips that implement "address overflow" are ones
431 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
432 address and the extra bits end up in the "chip address" bit
433 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
434 byte chips.
435
436endif
437
Mario Six86da8c12018-04-27 14:53:33 +0200438config GDSYS_RXAUI_CTRL
439 bool "Enable gdsys RXAUI control driver"
440 depends on MISC
441 help
442 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200443
444config GDSYS_IOEP
445 bool "Enable gdsys IOEP driver"
446 depends on MISC
447 help
448 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200449
450config MPC83XX_SERDES
451 bool "Enable MPC83xx serdes driver"
452 depends on MISC
453 help
454 Support for serdes found on MPC83xx SoCs.
455
Tien Fong Chee62030002018-07-06 16:28:03 +0800456config FS_LOADER
457 bool "Enable loader driver for file system"
458 help
459 This is file system generic loader which can be used to load
460 the file image from the storage into target such as memory.
461
462 The consumer driver would then use this loader to program whatever,
463 ie. the FPGA device.
464
Keerthyb071a072022-01-27 13:16:53 +0100465config SPL_FS_LOADER
466 bool "Enable loader driver for file system"
467 help
468 This is file system generic loader which can be used to load
469 the file image from the storage into target such as memory.
470
471 The consumer driver would then use this loader to program whatever,
472 ie. the FPGA device.
473
Mario Sixc0a2b082018-10-04 09:00:54 +0200474config GDSYS_SOC
475 bool "Enable gdsys SOC driver"
476 depends on MISC
477 help
478 Support for gdsys IHS SOC, a simple bus associated with each gdsys
479 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
480 register maps are contained within the FPGA's register map.
481
Mario Sixab88bd22018-10-04 09:00:55 +0200482config IHS_FPGA
483 bool "Enable IHS FPGA driver"
484 depends on MISC
485 help
486 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
487 gdsys devices, which supply the majority of the functionality offered
488 by the devices. This driver supports both CON and CPU variants of the
489 devices, depending on the device tree entry.
Tero Kristo344eb6d2020-02-14 11:18:15 +0200490config ESM_K3
491 bool "Enable K3 ESM driver"
492 depends on ARCH_K3
493 help
494 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Sixab88bd22018-10-04 09:00:55 +0200495
Eugen Hristevf8164952019-10-09 09:23:39 +0000496config MICROCHIP_FLEXCOM
497 bool "Enable Microchip Flexcom driver"
498 depends on MISC
499 help
500 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
501 an I2C controller and an USART.
502 Only one function can be used at a time and is chosen at boot time
503 according to the device tree.
504
Tero Kristo9d233b42019-10-24 15:00:46 +0530505config K3_AVS0
506 depends on ARCH_K3 && SPL_DM_REGULATOR
507 bool "AVS class 0 support for K3 devices"
508 help
509 K3 devices have the optimized voltage values for the main voltage
510 domains stored in efuse within the VTM IP. This driver reads the
511 optimized voltage from the efuse, so that it can be programmed
512 to the PMIC on board.
513
Tero Kristo3b36b382020-02-14 11:18:16 +0200514config ESM_PMIC
515 bool "Enable PMIC ESM driver"
516 depends on DM_PMIC
517 help
518 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
519 typically to reboot the board in error condition.
520
Tom Rini98ab8312021-12-11 14:55:49 -0500521config FSL_IFC
522 bool
523
Michael Walle42595eb2022-02-25 18:06:24 +0530524config SL28CPLD
525 bool "Enable Kontron sl28cpld multi-function driver"
526 depends on DM_I2C
527 help
528 Support for the Kontron sl28cpld management controller. This is
529 the base driver which provides common access methods for the
530 sub-drivers.
531
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900532endmenu