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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 468ba8d00b5af7828302e297736ae23d4873cfb0 / . / arch / arm / mach-socfpga / Kconfig
blob: 38d6c1b2ba32bb9e03b2b53f81e6d69d27e0e027 [file] [log] [blame]
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Goldschmidta43b60c2019-10-22 21:29:48 +0200[diff] [blame]3config ERR_PTR_OFFSET
4 default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
5
Simon Goldschmidtaef44282019-04-09 21:02:05 +0200[diff] [blame]6config NR_DRAM_BANKS
7 default 1
8
Simon Goldschmidtd6d383c2019-06-13 21:50:28 +0200[diff] [blame]9config SPL_SIZE_LIMIT
Simon Glassb51882d2019-09-25 08:56:28 -0600[diff] [blame]10 default 0x10000 if TARGET_SOCFPGA_GEN5
Simon Goldschmidtd6d383c2019-06-13 21:50:28 +0200[diff] [blame]11
12config SPL_SIZE_LIMIT_PROVIDE_STACK
13 default 0x200 if TARGET_SOCFPGA_GEN5
14
Simon Goldschmidtaef44282019-04-09 21:02:05 +0200[diff] [blame]15config SPL_STACK_R_ADDR
16 default 0x00800000 if TARGET_SOCFPGA_GEN5
17
Simon Goldschmidt9dc61aa2019-04-09 21:02:06 +0200[diff] [blame]18config SPL_SYS_MALLOC_F_LEN
19 default 0x800 if TARGET_SOCFPGA_GEN5
20
Dalon Westergreenf0fb4fa2017-02-10 17:15:34 -0800[diff] [blame]21config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
22 default 0xa2
23
Simon Goldschmidtaef44282019-04-09 21:02:05 +0200[diff] [blame]24config SYS_MALLOC_F_LEN
25 default 0x2000 if TARGET_SOCFPGA_ARRIA10
26 default 0x2000 if TARGET_SOCFPGA_GEN5
27
28config SYS_TEXT_BASE
29 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
30 default 0x01000040 if TARGET_SOCFPGA_GEN5
31
Ley Foon Tana76b7112019-11-27 15:55:32 +0800[diff] [blame]32config TARGET_SOCFPGA_AGILEX
33 bool
34 select ARMV8_MULTIENTRY
35 select ARMV8_SET_SMPEN
36 select ARMV8_SPIN_TABLE
37 select CLK
38 select NCORE_CACHE
39 select SPL_CLK if SPL
40
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]41config TARGET_SOCFPGA_ARRIA5
42 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -0600[diff] [blame]43 select TARGET_SOCFPGA_GEN5
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]44
Ley Foon Tand89e9792017-04-26 02:44:48 +0800[diff] [blame]45config TARGET_SOCFPGA_ARRIA10
46 bool
Ley Foon Tan5918afd2019-05-06 09:55:59 +0800[diff] [blame]47 select SPL_ALTERA_SDRAM
Michal Simek58008cb2018-07-23 15:55:15 +0200[diff] [blame]48 select SPL_BOARD_INIT if SPL
Marek Vasut934aec72018-07-30 15:56:19 +0200[diff] [blame]49 select CLK
50 select SPL_CLK if SPL
Marek Vasutfe88c2f2018-08-13 18:32:38 +0200[diff] [blame]51 select DM_I2C
Marek Vasut8145c1c2018-08-13 18:32:38 +0200[diff] [blame]52 select DM_RESET
53 select SPL_DM_RESET if SPL
Marek Vasutd6a61da2018-08-13 20:06:46 +0200[diff] [blame]54 select REGMAP
55 select SPL_REGMAP if SPL
56 select SYSCON
57 select SPL_SYSCON if SPL
58 select ETH_DESIGNWARE_SOCFPGA
Simon Goldschmidtaef44282019-04-09 21:02:05 +0200[diff] [blame]59 imply FPGA_SOCFPGA
Simon Glass27084c02019-09-25 08:56:27 -0600[diff] [blame]60 imply SPL_USE_TINY_PRINTF
Ley Foon Tand89e9792017-04-26 02:44:48 +0800[diff] [blame]61
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]62config TARGET_SOCFPGA_CYCLONE5
63 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -0600[diff] [blame]64 select TARGET_SOCFPGA_GEN5
65
66config TARGET_SOCFPGA_GEN5
67 bool
Ley Foon Tan5918afd2019-05-06 09:55:59 +0800[diff] [blame]68 select SPL_ALTERA_SDRAM
Simon Goldschmidtaef44282019-04-09 21:02:05 +0200[diff] [blame]69 imply FPGA_SOCFPGA
Simon Goldschmidtd6d383c2019-06-13 21:50:28 +0200[diff] [blame]70 imply SPL_SIZE_LIMIT_SUBTRACT_GD
71 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
Simon Goldschmidtaef44282019-04-09 21:02:05 +0200[diff] [blame]72 imply SPL_STACK_R
73 imply SPL_SYS_MALLOC_SIMPLE
Simon Glass27084c02019-09-25 08:56:27 -0600[diff] [blame]74 imply SPL_USE_TINY_PRINTF
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]75
Ley Foon Tana6847292018-05-24 00:17:32 +0800[diff] [blame]76config TARGET_SOCFPGA_STRATIX10
77 bool
78 select ARMV8_MULTIENTRY
Ley Foon Tana6847292018-05-24 00:17:32 +0800[diff] [blame]79 select ARMV8_SET_SMPEN
Michal Simek58008cb2018-07-23 15:55:15 +0200[diff] [blame]80 select ARMV8_SPIN_TABLE
Ang, Chee Hongbd558172018-12-19 18:35:16 -0800[diff] [blame]81 select FPGA_STRATIX10
Ley Foon Tana6847292018-05-24 00:17:32 +0800[diff] [blame]82
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]83choice
84 prompt "Altera SOCFPGA board select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500[diff] [blame]85 optional
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]86
Ley Foon Tana76b7112019-11-27 15:55:32 +0800[diff] [blame]87config TARGET_SOCFPGA_AGILEX_SOCDK
88 bool "Intel SOCFPGA SoCDK (Agilex)"
89 select TARGET_SOCFPGA_AGILEX
90
Wolfgang Grandegger990ed442019-05-12 19:25:18 +0200[diff] [blame]91config TARGET_SOCFPGA_ARIES_MCVEVK
92 bool "Aries MCVEVK (Cyclone V)"
93 select TARGET_SOCFPGA_CYCLONE5
94
Ley Foon Tand89e9792017-04-26 02:44:48 +0800[diff] [blame]95config TARGET_SOCFPGA_ARRIA10_SOCDK
96 bool "Altera SOCFPGA SoCDK (Arria 10)"
97 select TARGET_SOCFPGA_ARRIA10
98
Holger Brunck468ba8d2020-02-19 19:55:14 +0100[diff] [blame^]99config TARGET_SOCFPGA_ARRIA5_SECU1
100 bool "ABB SECU1 (Arria V)"
101 select TARGET_SOCFPGA_ARRIA5
102 select VENDOR_KM
103
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]104config TARGET_SOCFPGA_ARRIA5_SOCDK
105 bool "Altera SOCFPGA SoCDK (Arria V)"
106 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]107
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]108config TARGET_SOCFPGA_CYCLONE5_SOCDK
109 bool "Altera SOCFPGA SoCDK (Cyclone V)"
110 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]111
Marek Vasut7fb46432018-02-24 23:34:00 +0100[diff] [blame]112config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
113 bool "Devboards DBM-SoC1 (Cyclone V)"
114 select TARGET_SOCFPGA_CYCLONE5
115
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]116config TARGET_SOCFPGA_EBV_SOCRATES
117 bool "EBV SoCrates (Cyclone V)"
118 select TARGET_SOCFPGA_CYCLONE5
119
Pavel Machek35546f62016-06-07 12:37:23 +0200[diff] [blame]120config TARGET_SOCFPGA_IS1
121 bool "IS1 (Cyclone V)"
122 select TARGET_SOCFPGA_CYCLONE5
123
Marek Vasut94a16b82019-06-27 00:19:31 +0200[diff] [blame]124config TARGET_SOCFPGA_SOFTING_VINING_FPGA
125 bool "Softing VIN|ING FPGA (Cyclone V)"
Tom Rinie5ec4812017-01-22 19:43:11 -0500[diff] [blame]126 select BOARD_LATE_INIT
Marek Vasut569a1912015-12-01 18:09:52 +0100[diff] [blame]127 select TARGET_SOCFPGA_CYCLONE5
128
Marek Vasutcf0a8da2016-06-08 02:57:05 +0200[diff] [blame]129config TARGET_SOCFPGA_SR1500
130 bool "SR1500 (Cyclone V)"
131 select TARGET_SOCFPGA_CYCLONE5
132
Ley Foon Tana6847292018-05-24 00:17:32 +0800[diff] [blame]133config TARGET_SOCFPGA_STRATIX10_SOCDK
134 bool "Intel SOCFPGA SoCDK (Stratix 10)"
135 select TARGET_SOCFPGA_STRATIX10
136
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]137config TARGET_SOCFPGA_TERASIC_DE0_NANO
138 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
139 select TARGET_SOCFPGA_CYCLONE5
140
Dalon Westergreen6bd041f2017-04-18 08:11:16 -0700[diff] [blame]141config TARGET_SOCFPGA_TERASIC_DE10_NANO
142 bool "Terasic DE10-Nano (Cyclone V)"
143 select TARGET_SOCFPGA_CYCLONE5
144
Anatolij Gustschine9c847c2016-11-14 16:07:10 +0100[diff] [blame]145config TARGET_SOCFPGA_TERASIC_DE1_SOC
146 bool "Terasic DE1-SoC (Cyclone V)"
147 select TARGET_SOCFPGA_CYCLONE5
148
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]149config TARGET_SOCFPGA_TERASIC_SOCKIT
150 bool "Terasic SoCkit (Cyclone V)"
151 select TARGET_SOCFPGA_CYCLONE5
152
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]153endchoice
154
155config SYS_BOARD
Ley Foon Tana76b7112019-11-27 15:55:32 +0800[diff] [blame]156 default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
Marek Vasutf0892402015-08-10 21:24:53 +0200[diff] [blame]157 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tand89e9792017-04-26 02:44:48 +0800[diff] [blame]158 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasutf0892402015-08-10 21:24:53 +0200[diff] [blame]159 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut7fb46432018-02-24 23:34:00 +0100[diff] [blame]160 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]161 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschine9c847c2016-11-14 16:07:10 +0100[diff] [blame]162 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen6bd041f2017-04-18 08:11:16 -0700[diff] [blame]163 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek35546f62016-06-07 12:37:23 +0200[diff] [blame]164 default "is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger990ed442019-05-12 19:25:18 +0200[diff] [blame]165 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Holger Brunck468ba8d2020-02-19 19:55:14 +0100[diff] [blame^]166 default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]167 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]168 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +0100[diff] [blame]169 default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tana6847292018-05-24 00:17:32 +0800[diff] [blame]170 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut94a16b82019-06-27 00:19:31 +0200[diff] [blame]171 default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]172
173config SYS_VENDOR
Ley Foon Tana76b7112019-11-27 15:55:32 +0800[diff] [blame]174 default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]175 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tand89e9792017-04-26 02:44:48 +0800[diff] [blame]176 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]177 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tana6847292018-05-24 00:17:32 +0800[diff] [blame]178 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Wolfgang Grandegger990ed442019-05-12 19:25:18 +0200[diff] [blame]179 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut7fb46432018-02-24 23:34:00 +0100[diff] [blame]180 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]181 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Holger Brunck468ba8d2020-02-19 19:55:14 +0100[diff] [blame^]182 default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
Marek Vasut94a16b82019-06-27 00:19:31 +0200[diff] [blame]183 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]184 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschine9c847c2016-11-14 16:07:10 +0100[diff] [blame]185 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen6bd041f2017-04-18 08:11:16 -0700[diff] [blame]186 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]187 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]188
189config SYS_SOC
190 default "socfpga"
191
192config SYS_CONFIG_NAME
Ley Foon Tana76b7112019-11-27 15:55:32 +0800[diff] [blame]193 default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
Holger Brunck468ba8d2020-02-19 19:55:14 +0100[diff] [blame^]194 default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
Dinh Nguyen3cbc7b82015-09-22 17:01:32 -0500[diff] [blame]195 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tand89e9792017-04-26 02:44:48 +0800[diff] [blame]196 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen3cbc7b82015-09-22 17:01:32 -0500[diff] [blame]197 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut7fb46432018-02-24 23:34:00 +0100[diff] [blame]198 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]199 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschine9c847c2016-11-14 16:07:10 +0100[diff] [blame]200 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen6bd041f2017-04-18 08:11:16 -0700[diff] [blame]201 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek35546f62016-06-07 12:37:23 +0200[diff] [blame]202 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger990ed442019-05-12 19:25:18 +0200[diff] [blame]203 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]204 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]205 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +0100[diff] [blame]206 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tana6847292018-05-24 00:17:32 +0800[diff] [blame]207 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut94a16b82019-06-27 00:19:31 +0200[diff] [blame]208 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]209
Holger Brunck468ba8d2020-02-19 19:55:14 +0100[diff] [blame^]210source "board/keymile/Kconfig"
211
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]212endif