blob: d97930e577bb057a45ce62249871244440c9bdcf [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010017 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010019 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +010021 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010023 select ROM_EXCEPTION_VECTORS
Masahiro Yamadadd840582014-07-30 14:08:14 +090024
25config TARGET_MALTA
26 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +010027 select DM
28 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +000029 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +010030 select MIPS_CM
31 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +010032 select OF_CONTROL
33 select OF_ISA_BUS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010034 select SUPPORTS_BIG_ENDIAN
35 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010036 select SUPPORTS_CPU_MIPS32_R1
37 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010038 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010039 select SUPPORTS_CPU_MIPS64_R1
40 select SUPPORTS_CPU_MIPS64_R2
41 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010042 select SWAP_IO_SPACE
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +010043 select MIPS_L1_CACHE_SHIFT_6
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010044 select ROM_EXCEPTION_VECTORS
Masahiro Yamadadd840582014-07-30 14:08:14 +090045
46config TARGET_VCT
47 bool "Support vct"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010048 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010049 select SUPPORTS_CPU_MIPS32_R1
50 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000051 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010052 select ROM_EXCEPTION_VECTORS
Masahiro Yamadadd840582014-07-30 14:08:14 +090053
54config TARGET_DBAU1X00
55 bool "Support dbau1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010056 select SUPPORTS_BIG_ENDIAN
57 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010058 select SUPPORTS_CPU_MIPS32_R1
59 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000060 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010061 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010062 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090063
64config TARGET_PB1X00
65 bool "Support pb1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010066 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010067 select SUPPORTS_CPU_MIPS32_R1
68 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000069 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010070 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010071 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090072
Wills Wang1d3d0f12016-03-16 16:59:52 +080073config ARCH_ATH79
74 bool "Support QCA/Atheros ath79"
75 select OF_CONTROL
76 select DM
77
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053078config MACH_PIC32
79 bool "Support Microchip PIC32"
80 select OF_CONTROL
81 select DM
82
Paul Burtonad8783c2016-09-08 07:47:39 +010083config TARGET_BOSTON
84 bool "Support Boston"
85 select DM
86 select DM_SERIAL
87 select OF_CONTROL
88 select MIPS_CM
89 select MIPS_L1_CACHE_SHIFT_6
90 select MIPS_L2_CACHE
91 select SUPPORTS_BIG_ENDIAN
92 select SUPPORTS_LITTLE_ENDIAN
93 select SUPPORTS_CPU_MIPS32_R1
94 select SUPPORTS_CPU_MIPS32_R2
95 select SUPPORTS_CPU_MIPS32_R6
96 select SUPPORTS_CPU_MIPS64_R1
97 select SUPPORTS_CPU_MIPS64_R2
98 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010099 select ROM_EXCEPTION_VECTORS
Paul Burtonad8783c2016-09-08 07:47:39 +0100100
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100101config TARGET_XILFPGA
102 bool "Support Imagination Xilfpga"
103 select OF_CONTROL
104 select DM
105 select DM_SERIAL
106 select DM_GPIO
107 select DM_ETH
108 select SUPPORTS_LITTLE_ENDIAN
109 select SUPPORTS_CPU_MIPS32_R1
110 select SUPPORTS_CPU_MIPS32_R2
111 select MIPS_L1_CACHE_SHIFT_4
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100112 select ROM_EXCEPTION_VECTORS
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100113 help
114 This supports IMGTEC MIPSfpga platform
115
Masahiro Yamadadd840582014-07-30 14:08:14 +0900116endchoice
117
118source "board/dbau1x00/Kconfig"
Paul Burtonad8783c2016-09-08 07:47:39 +0100119source "board/imgtec/boston/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900120source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100121source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900122source "board/micronas/vct/Kconfig"
123source "board/pb1x00/Kconfig"
124source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800125source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530126source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900127
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100128if MIPS
129
130choice
131 prompt "Endianness selection"
132 help
133 Some MIPS boards can be configured for either little or big endian
134 byte order. These modes require different U-Boot images. In general there
135 is one preferred byteorder for a particular system but some systems are
136 just as commonly used in the one or the other endianness.
137
138config SYS_BIG_ENDIAN
139 bool "Big endian"
140 depends on SUPPORTS_BIG_ENDIAN
141
142config SYS_LITTLE_ENDIAN
143 bool "Little endian"
144 depends on SUPPORTS_LITTLE_ENDIAN
145
146endchoice
147
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100148choice
149 prompt "CPU selection"
150 default CPU_MIPS32_R2
151
152config CPU_MIPS32_R1
153 bool "MIPS32 Release 1"
154 depends on SUPPORTS_CPU_MIPS32_R1
155 select 32BIT
156 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100157 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100158 MIPS32 architecture.
159
160config CPU_MIPS32_R2
161 bool "MIPS32 Release 2"
162 depends on SUPPORTS_CPU_MIPS32_R2
163 select 32BIT
164 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100165 Choose this option to build an U-Boot for release 2 through 5 of the
166 MIPS32 architecture.
167
168config CPU_MIPS32_R6
169 bool "MIPS32 Release 6"
170 depends on SUPPORTS_CPU_MIPS32_R6
171 select 32BIT
172 help
173 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100174 MIPS32 architecture.
175
176config CPU_MIPS64_R1
177 bool "MIPS64 Release 1"
178 depends on SUPPORTS_CPU_MIPS64_R1
179 select 64BIT
180 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100181 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100182 MIPS64 architecture.
183
184config CPU_MIPS64_R2
185 bool "MIPS64 Release 2"
186 depends on SUPPORTS_CPU_MIPS64_R2
187 select 64BIT
188 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100189 Choose this option to build a kernel for release 2 through 5 of the
190 MIPS64 architecture.
191
192config CPU_MIPS64_R6
193 bool "MIPS64 Release 6"
194 depends on SUPPORTS_CPU_MIPS64_R6
195 select 64BIT
196 help
197 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100198 MIPS64 architecture.
199
200endchoice
201
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100202menu "General setup"
203
204config ROM_EXCEPTION_VECTORS
205 bool "Build U-Boot image with exception vectors"
206 help
207 Enable this to include exception vectors in the U-Boot image. This is
208 required if the U-Boot entry point is equal to the address of the
209 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
210 U-Boot booted from parallel NOR flash).
211 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
212 In that case the image size will be reduced by 0x500 bytes.
213
214endmenu
215
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100216menu "OS boot interface"
217
218config MIPS_BOOT_CMDLINE_LEGACY
219 bool "Hand over legacy command line to Linux kernel"
220 default y
221 help
222 Enable this option if you want U-Boot to hand over the Yamon-style
223 command line to the kernel. All bootargs will be prepared as argc/argv
224 compatible list. The argument count (argc) is stored in register $a0.
225 The address of the argument list (argv) is stored in register $a1.
226
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100227config MIPS_BOOT_ENV_LEGACY
228 bool "Hand over legacy environment to Linux kernel"
229 default y
230 help
231 Enable this option if you want U-Boot to hand over the Yamon-style
232 environment to the kernel. Information like memory size, initrd
233 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400234 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100235
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100236config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100237 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100238 default n
239 help
240 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100241 device tree to the kernel. According to UHI register $a0 will be set
242 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100243
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100244endmenu
245
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100246config SUPPORTS_BIG_ENDIAN
247 bool
248
249config SUPPORTS_LITTLE_ENDIAN
250 bool
251
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100252config SUPPORTS_CPU_MIPS32_R1
253 bool
254
255config SUPPORTS_CPU_MIPS32_R2
256 bool
257
Paul Burtonc52ebea2016-05-16 10:52:12 +0100258config SUPPORTS_CPU_MIPS32_R6
259 bool
260
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100261config SUPPORTS_CPU_MIPS64_R1
262 bool
263
264config SUPPORTS_CPU_MIPS64_R2
265 bool
266
Paul Burtonc52ebea2016-05-16 10:52:12 +0100267config SUPPORTS_CPU_MIPS64_R6
268 bool
269
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100270config CPU_MIPS32
271 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100272 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100273
274config CPU_MIPS64
275 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100276 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100277
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100278config MIPS_TUNE_4KC
279 bool
280
281config MIPS_TUNE_14KC
282 bool
283
284config MIPS_TUNE_24KC
285 bool
286
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200287config MIPS_TUNE_34KC
288 bool
289
Marek Vasut0a0a9582016-05-06 20:10:33 +0200290config MIPS_TUNE_74KC
291 bool
292
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100293config 32BIT
294 bool
295
296config 64BIT
297 bool
298
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100299config SWAP_IO_SPACE
300 bool
301
Paul Burtondd7c7202015-01-29 01:28:02 +0000302config SYS_MIPS_CACHE_INIT_RAM_LOAD
303 bool
304
Daniel Schwierzeck924ad862016-06-04 16:13:21 +0200305config MIPS_INIT_STACK_IN_SRAM
306 bool
307 default n
308 help
309 Select this if the initial stack frame could be setup in SRAM.
310 Normally the initial stack frame is set up in DRAM which is often
311 only available after lowlevel_init. With this option the initial
312 stack frame and the early C environment is set up before
313 lowlevel_init. Thus lowlevel_init does not need to be implemented
314 in assembler.
315
Paul Burtonace3be42016-05-27 14:28:04 +0100316config SYS_DCACHE_SIZE
317 int
318 default 0
319 help
320 The total size of the L1 Dcache, if known at compile time.
321
Paul Burton37228622016-05-27 14:28:05 +0100322config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100323 int
Paul Burton37228622016-05-27 14:28:05 +0100324 default 0
325 help
326 The size of L1 Dcache lines, if known at compile time.
327
Paul Burtonace3be42016-05-27 14:28:04 +0100328config SYS_ICACHE_SIZE
329 int
330 default 0
331 help
332 The total size of the L1 ICache, if known at compile time.
333
Paul Burton37228622016-05-27 14:28:05 +0100334config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100335 int
336 default 0
337 help
Paul Burton37228622016-05-27 14:28:05 +0100338 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100339
340config SYS_CACHE_SIZE_AUTO
341 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100342 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100343 help
344 Select this (or let it be auto-selected by not defining any cache
345 sizes) in order to allow U-Boot to automatically detect the sizes
346 of caches at runtime. This has a small cost in code size & runtime
347 so if you know the cache configuration for your system at compile
348 time it would be beneficial to configure it.
349
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100350config MIPS_L1_CACHE_SHIFT_4
351 bool
352
353config MIPS_L1_CACHE_SHIFT_5
354 bool
355
356config MIPS_L1_CACHE_SHIFT_6
357 bool
358
359config MIPS_L1_CACHE_SHIFT_7
360 bool
361
362config MIPS_L1_CACHE_SHIFT
363 int
364 default "7" if MIPS_L1_CACHE_SHIFT_7
365 default "6" if MIPS_L1_CACHE_SHIFT_6
366 default "5" if MIPS_L1_CACHE_SHIFT_5
367 default "4" if MIPS_L1_CACHE_SHIFT_4
368 default "5"
369
Paul Burton4baa0ab2016-09-21 11:18:54 +0100370config MIPS_L2_CACHE
371 bool
372 help
373 Select this if your system includes an L2 cache and you want U-Boot
374 to initialise & maintain it.
375
Paul Burton05e34252016-01-29 13:54:52 +0000376config DYNAMIC_IO_PORT_BASE
377 bool
378
Paul Burtonb2b135d2016-09-21 11:18:53 +0100379config MIPS_CM
380 bool
381 help
382 Select this if your system contains a MIPS Coherence Manager and you
383 wish U-Boot to configure it or make use of it to retrieve system
384 information such as cache configuration.
385
386config MIPS_CM_BASE
387 hex
388 default 0x1fbf8000
389 help
390 The physical base address at which to map the MIPS Coherence Manager
391 Global Configuration Registers (GCRs). This should be set such that
392 the GCRs occupy a region of the physical address space which is
393 otherwise unused, or at minimum that software doesn't need to access.
394
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100395endif
396
Masahiro Yamadadd840582014-07-30 14:08:14 +0900397endmenu