blob: dcd9316f3f25feed623af50b61278672dd3bf414 [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
Patrick Delaunay97f7e392020-07-24 11:13:31 +02004 select SPL_BOARD_INIT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01005 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Patrick Delaunaybc061342018-07-09 15:17:21 +02008 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
10 select SPL_GPIO_SUPPORT
11 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
19 select SPL_SYSCON
Patrick Delaunay9cd8b9f2019-07-30 19:16:33 +020020 select SPL_WATCHDOG_SUPPORT if WATCHDOG
Patrick Delaunay27a986d2019-04-18 17:32:47 +020021 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010023 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010024 imply SPL_LIBDISK_SUPPORT
Jagan Teki14dcdc62021-03-16 21:52:02 +053025 imply SPL_SPI_LOAD if SPL_SPI_SUPPORT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010026
27config SYS_SOC
28 default "stm32mp"
29
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020030config SYS_MALLOC_LEN
31 default 0x2000000
32
Patrick Delaunay579a3e72019-04-18 17:32:37 +020033config ENV_SIZE
Patrice Chotard1538e1a2019-05-07 18:40:47 +020034 default 0x2000
Patrick Delaunay579a3e72019-04-18 17:32:37 +020035
Patrick Delaunay84625482020-01-13 15:17:42 +010036config STM32MP15x
37 bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunay654706b2020-04-01 09:07:33 +020038 select ARCH_SUPPORT_PSCI if !TFABOOT
39 select ARM_SMCCC if TFABOOT
Lokesh Vutlaacf15002018-04-26 18:21:26 +053040 select CPU_V7A
Patrick Delaunay654706b2020-04-01 09:07:33 +020041 select CPU_V7_HAS_NONSEC if !TFABOOT
Patrick Delaunay41c79772018-04-16 10:13:24 +020042 select CPU_V7_HAS_VIRT
Patrick Delaunaye81f8d12019-07-02 13:26:07 +020043 select OF_BOARD_SETUP
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010044 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020045 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010046 select STM32_RESET
Patrick Delaunay16a07222019-07-30 19:16:25 +020047 select STM32_SERIAL
Andre Przywara7842b6a2018-04-12 04:24:46 +030048 select SYS_ARCH_TIMER
Patrick Delaunayc16cba82020-07-02 17:43:45 +020049 imply CMD_NVEDIT_INFO
Patrick Delaunay654706b2020-04-01 09:07:33 +020050 imply SYSRESET_PSCI if TFABOOT
51 imply SYSRESET_SYSCON if !TFABOOT
Patrick Delaunay84625482020-01-13 15:17:42 +010052 help
53 support of STMicroelectronics SOC STM32MP15x family
54 STM32MP157, STM32MP153 or STM32MP151
55 STMicroelectronics MPU with core ARMv7
56 dual core A7 for STM32MP157/3, monocore for STM32MP151
57 target all the STMicroelectronics board with SOC STM32MP1 family
58
59choice
60 prompt "STM32MP15x board select"
61 optional
62
63config TARGET_ST_STM32MP15x
64 bool "STMicroelectronics STM32MP15x boards"
65 select STM32MP15x
Patrick Delaunay34199822019-04-18 17:32:45 +020066 imply BOOTCOUNT_LIMIT
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010067 imply BOOTSTAGE
Patrick Delaunay34199822019-04-18 17:32:45 +020068 imply CMD_BOOTCOUNT
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010069 imply CMD_BOOTSTAGE
Patrick Delaunayeee15802019-12-03 09:38:58 +010070 imply CMD_CLS if CMD_BMP
Patrick Delaunaya67d9582019-07-30 19:16:26 +020071 imply DISABLE_CONSOLE
Patrick Delaunay67551982019-07-30 19:16:23 +020072 imply PRE_CONSOLE_BUFFER
Patrick Delaunayc50c9282019-07-30 19:16:22 +020073 imply SILENT_CONSOLE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010074 help
Patrick Delaunay84625482020-01-13 15:17:42 +010075 target the STMicroelectronics board with SOC STM32MP15x
76 managed by board/st/stm32mp1:
77 Evalulation board (EV1) or Discovery board (DK1 and DK2).
78 The difference between board are managed with devicetree
79
Jagan Teki30edf402021-03-16 21:52:03 +053080config TARGET_ICORE_STM32MP1
81 bool "Engicam i.Core STM32MP1 SOM"
82 select STM32MP15x
83 imply BOOTCOUNT_LIMIT
84 imply BOOTSTAGE
85 imply CMD_BOOTCOUNT
86 imply CMD_BOOTSTAGE
87 imply CMD_CLS if CMD_BMP
88 imply DISABLE_CONSOLE
89 imply PRE_CONSOLE_BUFFER
90 imply SILENT_CONSOLE
91 help
92 i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
93
94 i.Core STM32MP1 EDIMM2.2:
95 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
96 * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
97 creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
98
Jagan Tekib594ec82021-03-16 21:52:04 +053099 i.Core STM32MP1 C.TOUCH 2.0
100 * C.TOUCH 2.0 is a general purpose Carrier board.
101 * i.Core STM32MP1 needs to mount on top of this Carrier board
102 for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
103
Marek Vasut19953732020-01-24 18:39:16 +0100104config TARGET_DH_STM32MP1_PDK2
105 bool "DH STM32MP1 PDK2"
106 select STM32MP15x
107 imply BOOTCOUNT_LIMIT
108 imply CMD_BOOTCOUNT
109 help
110 Target the DH PDK2 development kit with STM32MP15x SoM.
111
Patrick Delaunay84625482020-01-13 15:17:42 +0100112endchoice
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100113
114config SYS_TEXT_BASE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100115 default 0xC0100000
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100116
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100117config NR_DRAM_BANKS
118 default 1
119
Patrick Delaunay67f9f112020-09-04 12:55:19 +0200120config DDR_CACHEABLE_SIZE
121 hex "Size of the DDR marked cacheable in pre-reloc stage"
122 default 0x10000000 if TFABOOT
123 default 0x40000000
124 help
125 Define the size of the DDR marked as cacheable in U-Boot
126 pre-reloc stage.
127 This option can be useful to avoid speculatif access
128 to secured area of DDR used by TF-A or OP-TEE before U-Boot
129 initialization.
130 The areas marked "no-map" in device tree should be located
131 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
132
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +0100133config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
134 hex "Partition on MMC2 to use to load U-Boot from"
135 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
136 default 1
137 help
138 Partition on the second MMC to load U-Boot from when the MMC is being
139 used in raw mode
140
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200141config STM32_ETZPC
142 bool "STM32 Extended TrustZone Protection"
Patrick Delaunay7a02e4d2020-03-10 16:05:43 +0100143 depends on STM32MP15x
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200144 default y
145 help
146 Say y to enable STM32 Extended TrustZone Protection
147
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200148config CMD_STM32KEY
149 bool "command stm32key to fuse public key hash"
150 default y
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200151 help
152 fuse public key hash in corresponding fuse used to authenticate
153 binary.
154
Patrick Delaunay67551982019-07-30 19:16:23 +0200155config PRE_CON_BUF_ADDR
156 default 0xC02FF000
157
158config PRE_CON_BUF_SZ
159 default 4096
160
Patrick Delaunay27a986d2019-04-18 17:32:47 +0200161config BOOTSTAGE_STASH_ADDR
162 default 0xC3000000
163
Patrick Delaunay34199822019-04-18 17:32:45 +0200164if BOOTCOUNT_LIMIT
165config SYS_BOOTCOUNT_SINGLEWORD
166 default y
167
168# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
169config SYS_BOOTCOUNT_ADDR
170 default 0x5C00A154
171endif
172
Patrick Delaunay320d2662018-05-17 14:50:46 +0200173if DEBUG_UART
174
175config DEBUG_UART_BOARD_INIT
176 default y
177
178# debug on UART4 by default
179config DEBUG_UART_BASE
180 default 0x40010000
181
182# clock source is HSI on reset
183config DEBUG_UART_CLOCK
184 default 64000000
185endif
186
Patrick Delaunay2dc22162021-02-25 13:37:00 +0100187source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Marek Vasut19953732020-01-24 18:39:16 +0100188source "board/dhelectronics/dh_stm32mp1/Kconfig"
Jagan Teki30edf402021-03-16 21:52:03 +0530189source "board/engicam/stm32mp1/Kconfig"
190source "board/st/stm32mp1/Kconfig"
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100191
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100192endif