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wdenkc0218802003-03-27 12:09:35 +00001/*
2 * Startup Code for MIPS32 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenkc0218802003-03-27 12:09:35 +00007 */
8
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +02009#include <asm-offsets.h>
wdenkc0218802003-03-27 12:09:35 +000010#include <config.h>
Paul Burtona39b1cb2015-01-29 10:04:08 +000011#include <asm/asm.h>
wdenkc0218802003-03-27 12:09:35 +000012#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14
Daniel Schwierzeckdd821282015-01-18 22:18:38 +010015#ifndef CONFIG_SYS_INIT_SP_ADDR
16#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
17 CONFIG_SYS_INIT_SP_OFFSET)
18#endif
19
Paul Burtonab0d0022015-01-29 10:04:09 +000020#ifdef CONFIG_32BIT
21# define MIPS_RELOC 3
Paul Burtonf1c64a02015-01-29 10:04:10 +000022# define STATUS_SET 0
Paul Burtonab0d0022015-01-29 10:04:09 +000023#endif
24
25#ifdef CONFIG_64BIT
26# ifdef CONFIG_SYS_LITTLE_ENDIAN
27# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
29# else
30# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32# endif
33# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
Paul Burtonf1c64a02015-01-29 10:04:10 +000034# define STATUS_SET ST0_KX
Paul Burtonab0d0022015-01-29 10:04:09 +000035#endif
36
Shinya Kuribayashidecaba62008-03-25 21:30:07 +090037 /*
38 * For the moment disable interrupts, mark the kernel mode and
39 * set ST0_KX so that the CPU does not spit fire when using
40 * 64-bit addresses.
41 */
42 .macro setup_c0_status set clr
43 .set push
44 mfc0 t0, CP0_STATUS
45 or t0, ST0_CU0 | \set | 0x1f | \clr
46 xor t0, 0x1f | \clr
47 mtc0 t0, CP0_STATUS
48 .set noreorder
49 sll zero, 3 # ehb
50 .set pop
51 .endm
52
wdenkc0218802003-03-27 12:09:35 +000053 .set noreorder
54
Daniel Schwierzeck11349292015-12-19 20:20:45 +010055ENTRY(_start)
Bin Menga1875592016-02-05 19:30:11 -080056 /* U-Boot entry point */
Daniel Schwierzeck8b1c7342013-02-12 22:22:12 +010057 b reset
58 nop
59
60 .org 0x10
Gabor Juhos843a76b2013-05-22 03:57:46 +000061#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
Daniel Schwierzeck7185adb2011-07-27 13:22:37 +020062 /*
63 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
64 * access external NOR flashes. If the board boots from NOR flash the
65 * internal BootROM does a blind read at address 0xB0000010 to read the
66 * initial configuration for that EBU in order to access the flash
67 * device with correct parameters. This config option is board-specific.
68 */
69 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
Daniel Schwierzeck8b1c7342013-02-12 22:22:12 +010070 .word 0x0
Paul Burton7a9d1092013-11-09 10:22:08 +000071#elif defined(CONFIG_MALTA)
Gabor Juhos843a76b2013-05-22 03:57:46 +000072 /*
73 * Linux expects the Board ID here.
74 */
75 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
76 .word 0x00000000
wdenkc0218802003-03-27 12:09:35 +000077#endif
wdenk8bde7f72003-06-27 21:31:46 +000078
Daniel Schwierzeck8b1c7342013-02-12 22:22:12 +010079 .org 0x200
80 /* TLB refill, 32 bit task */
811: b 1b
82 nop
83
84 .org 0x280
85 /* XTLB refill, 64 bit task */
861: b 1b
87 nop
88
89 .org 0x300
90 /* Cache error exception */
911: b 1b
92 nop
93
94 .org 0x380
95 /* General exception */
961: b 1b
97 nop
98
99 .org 0x400
100 /* Catch interrupt exceptions */
1011: b 1b
102 nop
103
104 .org 0x480
105 /* EJTAG debug exception */
1061: b 1b
107 nop
108
wdenkc0218802003-03-27 12:09:35 +0000109 .align 4
110reset:
111
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900112 /* Clear watch registers */
Paul Burtona39b1cb2015-01-29 10:04:08 +0000113 MTC0 zero, CP0_WATCHLO
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100114 mtc0 zero, CP0_WATCHHI
wdenkc0218802003-03-27 12:09:35 +0000115
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900116 /* WP(Watch Pending), SW0/1 should be cleared */
Shinya Kuribayashid43d43e2008-03-25 21:30:07 +0900117 mtc0 zero, CP0_CAUSE
118
Paul Burtonf1c64a02015-01-29 10:04:10 +0000119 setup_c0_status STATUS_SET 0
wdenkc0218802003-03-27 12:09:35 +0000120
wdenkc0218802003-03-27 12:09:35 +0000121 /* Init Timer */
122 mtc0 zero, CP0_COUNT
123 mtc0 zero, CP0_COMPARE
124
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900125#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Paul Burton4f9226b2016-09-21 11:18:50 +0100126 mfc0 t0, CP0_CONFIG
127 and t0, t0, MIPS_CONF_IMPL
128 or t0, t0, CONF_CM_UNCACHED
wdenkc0218802003-03-27 12:09:35 +0000129 mtc0 t0, CP0_CONFIG
Paul Burtonc5b84122016-09-21 11:18:57 +0100130 ehb
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900131#endif
wdenkc0218802003-03-27 12:09:35 +0000132
Paul Burtona39b1cb2015-01-29 10:04:08 +0000133 /*
134 * Initialize $gp, force pointer sized alignment of bal instruction to
135 * forbid the compiler to put nop's between bal and _gp. This is
136 * required to keep _gp and ra aligned to 8 byte.
137 */
138 .align PTRLOG
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900139 bal 1f
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900140 nop
Paul Burtona39b1cb2015-01-29 10:04:08 +0000141 PTR _gp
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +09001421:
Paul Burtona39b1cb2015-01-29 10:04:08 +0000143 PTR_L gp, 0(ra)
Wolfgang Denkc75eba32005-12-01 02:15:07 +0100144
Paul Burtonb2b135d2016-09-21 11:18:53 +0100145#ifdef CONFIG_MIPS_CM
146 PTR_LA t9, mips_cm_map
147 jalr t9
148 nop
149#endif
150
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900151#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Paul Burtonf8981272016-09-21 11:18:51 +0100152# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900153 /* Initialize any external memory */
Paul Burtona39b1cb2015-01-29 10:04:08 +0000154 PTR_LA t9, lowlevel_init
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900155 jalr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900156 nop
Paul Burtonf8981272016-09-21 11:18:51 +0100157# endif
wdenkc0218802003-03-27 12:09:35 +0000158
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900159 /* Initialize caches... */
Paul Burtona39b1cb2015-01-29 10:04:08 +0000160 PTR_LA t9, mips_cache_reset
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +0900161 jalr t9
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900162 nop
Paul Burtonf8981272016-09-21 11:18:51 +0100163
164# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
165 /* Initialize any external memory */
166 PTR_LA t9, lowlevel_init
167 jalr t9
168 nop
169# endif
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900170#endif
wdenkc0218802003-03-27 12:09:35 +0000171
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900172 /* Set up temporary stack */
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100173 li t0, -16
Paul Burtona39b1cb2015-01-29 10:04:08 +0000174 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
Daniel Schwierzecke5200232015-01-18 22:18:39 +0100175 and sp, t1, t0 # force 16 byte alignment
Paul Burton9f8ac822016-05-16 10:52:10 +0100176 PTR_SUBU \
177 sp, sp, GD_SIZE # reserve space for gd
Daniel Schwierzecke5200232015-01-18 22:18:39 +0100178 and sp, sp, t0 # force 16 byte alignment
179 move k0, sp # save gd pointer
180#ifdef CONFIG_SYS_MALLOC_F_LEN
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100181 li t2, CONFIG_SYS_MALLOC_F_LEN
Paul Burton9f8ac822016-05-16 10:52:10 +0100182 PTR_SUBU \
183 sp, sp, t2 # reserve space for early malloc
Daniel Schwierzecke5200232015-01-18 22:18:39 +0100184 and sp, sp, t0 # force 16 byte alignment
185#endif
Daniel Schwierzeck6d08e222014-11-20 23:55:32 +0100186 move fp, sp
wdenkc0218802003-03-27 12:09:35 +0000187
Daniel Schwierzecke5200232015-01-18 22:18:39 +0100188 /* Clear gd */
189 move t0, k0
1901:
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100191 PTR_S zero, 0(t0)
Daniel Schwierzecke5200232015-01-18 22:18:39 +0100192 blt t0, t1, 1b
Paul Burton9f8ac822016-05-16 10:52:10 +0100193 PTR_ADDIU t0, PTRSIZE
Daniel Schwierzecke5200232015-01-18 22:18:39 +0100194
195#ifdef CONFIG_SYS_MALLOC_F_LEN
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100196 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
Daniel Schwierzecke5200232015-01-18 22:18:39 +0100197#endif
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100198
Purna Chandra Mandala6279092016-01-21 20:02:51 +0530199 move a0, zero # a0 <-- boot_flags = 0
Paul Burtona39b1cb2015-01-29 10:04:08 +0000200 PTR_LA t9, board_init_f
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900201 jr t9
Daniel Schwierzeck6d08e222014-11-20 23:55:32 +0100202 move ra, zero
wdenkc0218802003-03-27 12:09:35 +0000203
Daniel Schwierzeck11349292015-12-19 20:20:45 +0100204 END(_start)
205
wdenkc0218802003-03-27 12:09:35 +0000206/*
207 * void relocate_code (addr_sp, gd, addr_moni)
208 *
209 * This "function" does not return, instead it continues in RAM
210 * after relocating the monitor code.
211 *
212 * a0 = addr_sp
213 * a1 = gd
214 * a2 = destination address
215 */
Daniel Schwierzeck11349292015-12-19 20:20:45 +0100216ENTRY(relocate_code)
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900217 move sp, a0 # set new stack pointer
Daniel Schwierzeck6d08e222014-11-20 23:55:32 +0100218 move fp, sp
wdenkc0218802003-03-27 12:09:35 +0000219
Gabor Juhosb2fe86f2013-01-24 06:27:53 +0000220 move s0, a1 # save gd in s0
221 move s2, a2 # save destination address in s2
222
Paul Burtona39b1cb2015-01-29 10:04:08 +0000223 PTR_LI t0, CONFIG_SYS_MONITOR_BASE
224 PTR_SUB s1, s2, t0 # s1 <-- relocation offset
Gabor Juhos248fe032013-01-24 06:27:54 +0000225
Paul Burtona39b1cb2015-01-29 10:04:08 +0000226 PTR_LA t3, in_ram
227 PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
wdenk27b207f2003-07-24 23:38:38 +0000228 move t1, a2
229
Paul Burtona39b1cb2015-01-29 10:04:08 +0000230 PTR_ADD gp, s1 # adjust gp
wdenk8bde7f72003-06-27 21:31:46 +0000231
wdenkc0218802003-03-27 12:09:35 +0000232 /*
233 * t0 = source address
234 * t1 = target address
235 * t2 = source end address
236 */
2371:
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100238 PTR_L t3, 0(t0)
239 PTR_S t3, 0(t1)
240 PTR_ADDU t0, PTRSIZE
Gabor Juhos5b7dd812013-01-24 06:27:51 +0000241 blt t0, t2, 1b
Daniel Schwierzecke26e8dc2016-01-09 22:24:47 +0100242 PTR_ADDU t1, PTRSIZE
wdenkc0218802003-03-27 12:09:35 +0000243
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900244 /* If caches were enabled, we would have to flush them here. */
Paul Burtona39b1cb2015-01-29 10:04:08 +0000245 PTR_SUB a1, t1, s2 # a1 <-- size
246 PTR_LA t9, flush_cache
Stefan Roese71fa0712008-11-18 16:36:12 +0100247 jalr t9
Gabor Juhos67d80c92013-01-24 06:27:55 +0000248 move a0, s2 # a0 <-- destination address
Stefan Roese71fa0712008-11-18 16:36:12 +0100249
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900250 /* Jump to where we've relocated ourselves */
Paul Burton9f8ac822016-05-16 10:52:10 +0100251 PTR_ADDIU t0, s2, in_ram - _start
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900252 jr t0
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900253 nop
wdenkc0218802003-03-27 12:09:35 +0000254
Paul Burtona39b1cb2015-01-29 10:04:08 +0000255 PTR __rel_dyn_end
256 PTR __rel_dyn_start
257 PTR __image_copy_end
258 PTR _GLOBAL_OFFSET_TABLE_
259 PTR num_got_entries
wdenkc0218802003-03-27 12:09:35 +0000260
261in_ram:
Shinya Kuribayashi22069212007-10-21 10:55:36 +0900262 /*
263 * Now we want to update GOT.
264 *
265 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
266 * generated by GNU ld. Skip these reserved entries from relocation.
wdenkc0218802003-03-27 12:09:35 +0000267 */
Paul Burtona39b1cb2015-01-29 10:04:08 +0000268 PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
269 PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
270 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
Paul Burton9f8ac822016-05-16 10:52:10 +0100271 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
Paul Burtona39b1cb2015-01-29 10:04:08 +0000272 PTR_LI t2, 2
wdenkc0218802003-03-27 12:09:35 +00002731:
Paul Burtona39b1cb2015-01-29 10:04:08 +0000274 PTR_L t1, 0(t8)
wdenkc0218802003-03-27 12:09:35 +0000275 beqz t1, 2f
Paul Burtona39b1cb2015-01-29 10:04:08 +0000276 PTR_ADD t1, s1
277 PTR_S t1, 0(t8)
wdenkc0218802003-03-27 12:09:35 +00002782:
Paul Burton9f8ac822016-05-16 10:52:10 +0100279 PTR_ADDIU t2, 1
wdenkc0218802003-03-27 12:09:35 +0000280 blt t2, t3, 1b
Paul Burton9f8ac822016-05-16 10:52:10 +0100281 PTR_ADDIU t8, PTRSIZE
wdenkc0218802003-03-27 12:09:35 +0000282
Gabor Juhos04380c62013-02-12 22:22:13 +0100283 /* Update dynamic relocations */
Paul Burtona39b1cb2015-01-29 10:04:08 +0000284 PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
285 PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
Gabor Juhos04380c62013-02-12 22:22:13 +0100286
287 b 2f # skip first reserved entry
Paul Burton9f8ac822016-05-16 10:52:10 +0100288 PTR_ADDIU t1, 2 * PTRSIZE
Gabor Juhos04380c62013-02-12 22:22:13 +0100289
2901:
Gabor Juhos691995f2013-06-13 12:59:28 +0200291 lw t8, -4(t1) # t8 <-- relocation info
Gabor Juhos04380c62013-02-12 22:22:13 +0100292
Paul Burtonab0d0022015-01-29 10:04:09 +0000293 PTR_LI t3, MIPS_RELOC
294 bne t8, t3, 2f # skip non-MIPS_RELOC entries
Gabor Juhos04380c62013-02-12 22:22:13 +0100295 nop
296
Paul Burtona39b1cb2015-01-29 10:04:08 +0000297 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
Gabor Juhos04380c62013-02-12 22:22:13 +0100298
Paul Burtona39b1cb2015-01-29 10:04:08 +0000299 PTR_L t8, 0(t3) # t8 <-- original pointer
300 PTR_ADD t8, s1 # t8 <-- adjusted pointer
Gabor Juhos04380c62013-02-12 22:22:13 +0100301
Paul Burtona39b1cb2015-01-29 10:04:08 +0000302 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
303 PTR_S t8, 0(t3)
Gabor Juhos04380c62013-02-12 22:22:13 +0100304
3052:
306 blt t1, t2, 1b
Paul Burton9f8ac822016-05-16 10:52:10 +0100307 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
Gabor Juhos04380c62013-02-12 22:22:13 +0100308
Daniel Schwierzeck696a3b22013-02-12 22:22:13 +0100309 /*
310 * Clear BSS
311 *
312 * GOT is now relocated. Thus __bss_start and __bss_end can be
313 * accessed directly via $gp.
314 */
Paul Burtona39b1cb2015-01-29 10:04:08 +0000315 PTR_LA t1, __bss_start # t1 <-- __bss_start
316 PTR_LA t2, __bss_end # t2 <-- __bss_end
wdenkc0218802003-03-27 12:09:35 +0000317
Shinya Kuribayashi03c031d2007-10-27 15:27:06 +09003181:
Paul Burtona39b1cb2015-01-29 10:04:08 +0000319 PTR_S zero, 0(t1)
Daniel Schwierzeck696a3b22013-02-12 22:22:13 +0100320 blt t1, t2, 1b
Paul Burton9f8ac822016-05-16 10:52:10 +0100321 PTR_ADDIU t1, PTRSIZE
wdenk8bde7f72003-06-27 21:31:46 +0000322
Shinya Kuribayashi7aa1f192011-05-07 00:18:13 +0900323 move a0, s0 # a0 <-- gd
Daniel Schwierzeck6d08e222014-11-20 23:55:32 +0100324 move a1, s2
Paul Burtona39b1cb2015-01-29 10:04:08 +0000325 PTR_LA t9, board_init_r
Shinya Kuribayashi43c50922008-04-17 23:35:13 +0900326 jr t9
Daniel Schwierzeck6d08e222014-11-20 23:55:32 +0100327 move ra, zero
wdenkc0218802003-03-27 12:09:35 +0000328
Daniel Schwierzeck11349292015-12-19 20:20:45 +0100329 END(relocate_code)