blob: 079d66a80c1d32262cc0d843386cdf89e37af436 [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
Patrick Delaunay97f7e392020-07-24 11:13:31 +02004 select SPL_BOARD_INIT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01005 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Patrick Delaunaybc061342018-07-09 15:17:21 +02008 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
10 select SPL_GPIO_SUPPORT
11 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
Patrick Delaunay49ef8e12019-07-30 19:16:36 +020019 select SPL_SPI_LOAD
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010020 select SPL_SYSCON
Patrick Delaunay9cd8b9f2019-07-30 19:16:33 +020021 select SPL_WATCHDOG_SUPPORT if WATCHDOG
Patrick Delaunay27a986d2019-04-18 17:32:47 +020022 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
23 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010024 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010025 imply SPL_LIBDISK_SUPPORT
26
27config SYS_SOC
28 default "stm32mp"
29
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020030config SYS_MALLOC_LEN
31 default 0x2000000
32
Patrick Delaunay579a3e72019-04-18 17:32:37 +020033config ENV_SIZE
Patrice Chotard1538e1a2019-05-07 18:40:47 +020034 default 0x2000
Patrick Delaunay579a3e72019-04-18 17:32:37 +020035
Patrick Delaunay84625482020-01-13 15:17:42 +010036config STM32MP15x
37 bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunay654706b2020-04-01 09:07:33 +020038 select ARCH_SUPPORT_PSCI if !TFABOOT
39 select ARM_SMCCC if TFABOOT
Lokesh Vutlaacf15002018-04-26 18:21:26 +053040 select CPU_V7A
Patrick Delaunay654706b2020-04-01 09:07:33 +020041 select CPU_V7_HAS_NONSEC if !TFABOOT
Patrick Delaunay41c79772018-04-16 10:13:24 +020042 select CPU_V7_HAS_VIRT
Patrick Delaunaye81f8d12019-07-02 13:26:07 +020043 select OF_BOARD_SETUP
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010044 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020045 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010046 select STM32_RESET
Patrick Delaunay16a07222019-07-30 19:16:25 +020047 select STM32_SERIAL
Andre Przywara7842b6a2018-04-12 04:24:46 +030048 select SYS_ARCH_TIMER
Patrick Delaunayc16cba82020-07-02 17:43:45 +020049 imply CMD_NVEDIT_INFO
Patrick Delaunay654706b2020-04-01 09:07:33 +020050 imply SYSRESET_PSCI if TFABOOT
51 imply SYSRESET_SYSCON if !TFABOOT
Patrick Delaunay84625482020-01-13 15:17:42 +010052 help
53 support of STMicroelectronics SOC STM32MP15x family
54 STM32MP157, STM32MP153 or STM32MP151
55 STMicroelectronics MPU with core ARMv7
56 dual core A7 for STM32MP157/3, monocore for STM32MP151
57 target all the STMicroelectronics board with SOC STM32MP1 family
58
59choice
60 prompt "STM32MP15x board select"
61 optional
62
63config TARGET_ST_STM32MP15x
64 bool "STMicroelectronics STM32MP15x boards"
65 select STM32MP15x
Patrick Delaunay34199822019-04-18 17:32:45 +020066 imply BOOTCOUNT_LIMIT
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010067 imply BOOTSTAGE
Patrick Delaunay34199822019-04-18 17:32:45 +020068 imply CMD_BOOTCOUNT
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010069 imply CMD_BOOTSTAGE
Patrick Delaunayeee15802019-12-03 09:38:58 +010070 imply CMD_CLS if CMD_BMP
Patrick Delaunaya67d9582019-07-30 19:16:26 +020071 imply DISABLE_CONSOLE
Patrick Delaunay67551982019-07-30 19:16:23 +020072 imply PRE_CONSOLE_BUFFER
Patrick Delaunayc50c9282019-07-30 19:16:22 +020073 imply SILENT_CONSOLE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010074 help
Patrick Delaunay84625482020-01-13 15:17:42 +010075 target the STMicroelectronics board with SOC STM32MP15x
76 managed by board/st/stm32mp1:
77 Evalulation board (EV1) or Discovery board (DK1 and DK2).
78 The difference between board are managed with devicetree
79
Marek Vasut19953732020-01-24 18:39:16 +010080config TARGET_DH_STM32MP1_PDK2
81 bool "DH STM32MP1 PDK2"
82 select STM32MP15x
83 imply BOOTCOUNT_LIMIT
84 imply CMD_BOOTCOUNT
85 help
86 Target the DH PDK2 development kit with STM32MP15x SoM.
87
Patrick Delaunay84625482020-01-13 15:17:42 +010088endchoice
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010089
90config SYS_TEXT_BASE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010091 default 0xC0100000
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010092
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010093config NR_DRAM_BANKS
94 default 1
95
Patrick Delaunay67f9f112020-09-04 12:55:19 +020096config DDR_CACHEABLE_SIZE
97 hex "Size of the DDR marked cacheable in pre-reloc stage"
98 default 0x10000000 if TFABOOT
99 default 0x40000000
100 help
101 Define the size of the DDR marked as cacheable in U-Boot
102 pre-reloc stage.
103 This option can be useful to avoid speculatif access
104 to secured area of DDR used by TF-A or OP-TEE before U-Boot
105 initialization.
106 The areas marked "no-map" in device tree should be located
107 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
108
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +0100109config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
110 hex "Partition on MMC2 to use to load U-Boot from"
111 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
112 default 1
113 help
114 Partition on the second MMC to load U-Boot from when the MMC is being
115 used in raw mode
116
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200117config STM32_ETZPC
118 bool "STM32 Extended TrustZone Protection"
Patrick Delaunay7a02e4d2020-03-10 16:05:43 +0100119 depends on STM32MP15x
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200120 default y
121 help
122 Say y to enable STM32 Extended TrustZone Protection
123
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200124config CMD_STM32KEY
125 bool "command stm32key to fuse public key hash"
126 default y
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200127 help
128 fuse public key hash in corresponding fuse used to authenticate
129 binary.
130
Patrick Delaunay67551982019-07-30 19:16:23 +0200131config PRE_CON_BUF_ADDR
132 default 0xC02FF000
133
134config PRE_CON_BUF_SZ
135 default 4096
136
Patrick Delaunay27a986d2019-04-18 17:32:47 +0200137config BOOTSTAGE_STASH_ADDR
138 default 0xC3000000
139
Patrick Delaunay34199822019-04-18 17:32:45 +0200140if BOOTCOUNT_LIMIT
141config SYS_BOOTCOUNT_SINGLEWORD
142 default y
143
144# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
145config SYS_BOOTCOUNT_ADDR
146 default 0x5C00A154
147endif
148
Patrick Delaunay320d2662018-05-17 14:50:46 +0200149if DEBUG_UART
150
151config DEBUG_UART_BOARD_INIT
152 default y
153
154# debug on UART4 by default
155config DEBUG_UART_BASE
156 default 0x40010000
157
158# clock source is HSI on reset
159config DEBUG_UART_CLOCK
160 default 64000000
161endif
162
Patrick Delaunay2dc22162021-02-25 13:37:00 +0100163source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100164source "board/st/stm32mp1/Kconfig"
Marek Vasut19953732020-01-24 18:39:16 +0100165source "board/dhelectronics/dh_stm32mp1/Kconfig"
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100166
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100167endif