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wdenk42d1f032003-10-15 23:53:47 +00001/*
Andy Fleming1ced1212008-02-06 01:19:40 -06002 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andy Fleming75b9d4a2008-08-31 16:33:26 -050028#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000029#include <common.h>
30#include <watchdog.h>
31#include <command.h>
Andy Fleming75b9d4a2008-08-31 16:33:26 -050032#include <tsec.h>
Ben Warren3456a142008-10-22 23:20:29 -070033#include <netdev.h>
Andy Fleming80522dc2008-10-30 16:51:33 -050034#include <fsl_esdhc.h>
wdenk42d1f032003-10-15 23:53:47 +000035#include <asm/cache.h>
Sergei Poselenov740280e2008-06-06 15:42:40 +020036#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000037
James Yang591933c2008-02-08 16:44:53 -060038DECLARE_GLOBAL_DATA_PTR;
39
Andy Fleming1ced1212008-02-06 01:19:40 -060040struct cpu_type cpu_type_list [] = {
Kumar Gala4dbdb762008-06-10 16:53:46 -050041 CPU_TYPE_ENTRY(8533, 8533),
42 CPU_TYPE_ENTRY(8533, 8533_E),
Kumar Gala71b358c2009-05-20 01:11:33 -050043 CPU_TYPE_ENTRY(8535, 8535),
44 CPU_TYPE_ENTRY(8535, 8535_E),
Kumar Galaef50d6c2008-08-12 11:14:19 -050045 CPU_TYPE_ENTRY(8536, 8536),
46 CPU_TYPE_ENTRY(8536, 8536_E),
Kumar Gala4dbdb762008-06-10 16:53:46 -050047 CPU_TYPE_ENTRY(8540, 8540),
48 CPU_TYPE_ENTRY(8541, 8541),
49 CPU_TYPE_ENTRY(8541, 8541_E),
50 CPU_TYPE_ENTRY(8543, 8543),
51 CPU_TYPE_ENTRY(8543, 8543_E),
52 CPU_TYPE_ENTRY(8544, 8544),
53 CPU_TYPE_ENTRY(8544, 8544_E),
54 CPU_TYPE_ENTRY(8545, 8545),
55 CPU_TYPE_ENTRY(8545, 8545_E),
56 CPU_TYPE_ENTRY(8547, 8547_E),
57 CPU_TYPE_ENTRY(8548, 8548),
58 CPU_TYPE_ENTRY(8548, 8548_E),
59 CPU_TYPE_ENTRY(8555, 8555),
60 CPU_TYPE_ENTRY(8555, 8555_E),
61 CPU_TYPE_ENTRY(8560, 8560),
62 CPU_TYPE_ENTRY(8567, 8567),
63 CPU_TYPE_ENTRY(8567, 8567_E),
64 CPU_TYPE_ENTRY(8568, 8568),
65 CPU_TYPE_ENTRY(8568, 8568_E),
Haiying Wang22b6dbc2009-03-27 17:02:44 -040066 CPU_TYPE_ENTRY(8569, 8569),
67 CPU_TYPE_ENTRY(8569, 8569_E),
Kumar Gala4dbdb762008-06-10 16:53:46 -050068 CPU_TYPE_ENTRY(8572, 8572),
69 CPU_TYPE_ENTRY(8572, 8572_E),
Srikanth Srinivasan8d949af2009-01-21 17:17:33 -060070 CPU_TYPE_ENTRY(P2020, P2020),
71 CPU_TYPE_ENTRY(P2020, P2020_E),
Andy Fleming1ced1212008-02-06 01:19:40 -060072};
73
Anatolij Gustschin96026d42008-06-12 12:40:11 +020074struct cpu_type *identify_cpu(u32 ver)
Kumar Gala4dbdb762008-06-10 16:53:46 -050075{
76 int i;
77 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
78 if (cpu_type_list[i].soc_ver == ver)
79 return &cpu_type_list[i];
80
81 return NULL;
82}
83
wdenk42d1f032003-10-15 23:53:47 +000084int checkcpu (void)
85{
wdenk97d80fc2004-06-09 00:34:46 +000086 sys_info_t sysinfo;
wdenk97d80fc2004-06-09 00:34:46 +000087 uint pvr, svr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050088 uint fam;
wdenk97d80fc2004-06-09 00:34:46 +000089 uint ver;
90 uint major, minor;
Kumar Gala4dbdb762008-06-10 16:53:46 -050091 struct cpu_type *cpu;
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020092 char buf1[32], buf2[32];
Kumar Galaee1e35b2008-05-29 01:21:24 -050093#ifdef CONFIG_DDR_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Jason Jinc0391112008-09-27 14:40:57 +080095 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
96 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galaee1e35b2008-05-29 01:21:24 -050097#else
98 u32 ddr_ratio = 0;
99#endif
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500100 int i;
wdenk42d1f032003-10-15 23:53:47 +0000101
wdenk97d80fc2004-06-09 00:34:46 +0000102 svr = get_svr();
Andy Fleming1ced1212008-02-06 01:19:40 -0600103 ver = SVR_SOC_VER(svr);
wdenk97d80fc2004-06-09 00:34:46 +0000104 major = SVR_MAJ(svr);
Kumar Galaef50d6c2008-08-12 11:14:19 -0500105#ifdef CONFIG_MPC8536
106 major &= 0x7; /* the msb of this nibble is a mfg code */
107#endif
wdenk97d80fc2004-06-09 00:34:46 +0000108 minor = SVR_MIN(svr);
109
Ed Swarthout6856b3d2008-10-08 23:37:59 -0500110#if (CONFIG_NUM_CPUS > 1)
111 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
112 printf("CPU%d: ", pic->whoami);
113#else
wdenk6c9e7892005-03-15 22:56:53 +0000114 puts("CPU: ");
Ed Swarthout6856b3d2008-10-08 23:37:59 -0500115#endif
Andy Fleming1ced1212008-02-06 01:19:40 -0600116
Kumar Gala4dbdb762008-06-10 16:53:46 -0500117 cpu = identify_cpu(ver);
118 if (cpu) {
119 puts(cpu->name);
Andy Fleming1ced1212008-02-06 01:19:40 -0600120
Kim Phillips06b41862008-06-17 17:45:22 -0500121 if (IS_E_PROCESSOR(svr))
Kumar Gala4dbdb762008-06-10 16:53:46 -0500122 puts("E");
123 } else {
wdenk97d80fc2004-06-09 00:34:46 +0000124 puts("Unknown");
Kumar Gala4dbdb762008-06-10 16:53:46 -0500125 }
Andy Fleming1ced1212008-02-06 01:19:40 -0600126
wdenk97d80fc2004-06-09 00:34:46 +0000127 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +0000128
wdenk6c9e7892005-03-15 22:56:53 +0000129 pvr = get_pvr();
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500130 fam = PVR_FAM(pvr);
wdenk6c9e7892005-03-15 22:56:53 +0000131 ver = PVR_VER(pvr);
132 major = PVR_MAJ(pvr);
133 minor = PVR_MIN(pvr);
134
135 printf("Core: ");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500136 switch (fam) {
137 case PVR_FAM(PVR_85xx):
wdenk6c9e7892005-03-15 22:56:53 +0000138 puts("E500");
139 break;
140 default:
141 puts("Unknown");
142 break;
143 }
Kumar Gala0f060c32008-10-23 01:47:38 -0500144
145 if (PVR_MEM(pvr) == 0x03)
146 puts("MC");
147
wdenk6c9e7892005-03-15 22:56:53 +0000148 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
149
wdenk97d80fc2004-06-09 00:34:46 +0000150 get_sys_info(&sysinfo);
151
Kumar Galab29dee32009-02-04 09:35:57 -0600152 puts("Clock Configuration:");
153 for (i = 0; i < CONFIG_NUM_CPUS; i++) {
Wolfgang Denk1bba30e2009-02-19 00:41:08 +0100154 if (!(i & 3))
155 printf ("\n ");
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500156 printf("CPU%d:%-4s MHz, ",
157 i,strmhz(buf1, sysinfo.freqProcessor[i]));
Kumar Galab29dee32009-02-04 09:35:57 -0600158 }
159 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
Kumar Galaee1e35b2008-05-29 01:21:24 -0500160
Kumar Galad4357932007-12-07 04:59:26 -0600161 switch (ddr_ratio) {
162 case 0x0:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200163 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
164 strmhz(buf1, sysinfo.freqDDRBus/2),
165 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600166 break;
167 case 0x7:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200168 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
169 strmhz(buf1, sysinfo.freqDDRBus/2),
170 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600171 break;
172 default:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200173 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
174 strmhz(buf1, sysinfo.freqDDRBus/2),
175 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600176 break;
177 }
wdenk97d80fc2004-06-09 00:34:46 +0000178
Trent Piephoada591d2008-12-03 15:16:37 -0800179 if (sysinfo.freqLocalBus > LCRR_CLKDIV)
180 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
181 else
182 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
183 sysinfo.freqLocalBus);
wdenk97d80fc2004-06-09 00:34:46 +0000184
Andy Fleming1ced1212008-02-06 01:19:40 -0600185#ifdef CONFIG_CPM2
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200186 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
Andy Fleming1ced1212008-02-06 01:19:40 -0600187#endif
wdenk97d80fc2004-06-09 00:34:46 +0000188
Haiying Wangb3d7f202009-05-20 12:30:29 -0400189#ifdef CONFIG_QE
190 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
191#endif
192
wdenk6c9e7892005-03-15 22:56:53 +0000193 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000194
195 return 0;
196}
197
198
199/* ------------------------------------------------------------------------- */
200
201int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
202{
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800203 uint pvr;
204 uint ver;
Sergei Poselenov793670c2008-05-08 14:17:08 +0200205 unsigned long val, msr;
206
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800207 pvr = get_pvr();
208 ver = PVR_VER(pvr);
Sergei Poselenov793670c2008-05-08 14:17:08 +0200209
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800210 if (ver & 1){
211 /* e500 v2 core has reset control register */
212 volatile unsigned int * rstcr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
Wolfgang Denk2f152782007-05-05 18:23:11 +0200214 *rstcr = 0x2; /* HRESET_REQ */
Sergei Poselenov793670c2008-05-08 14:17:08 +0200215 udelay(100);
216 }
217
wdenk42d1f032003-10-15 23:53:47 +0000218 /*
Sergei Poselenov793670c2008-05-08 14:17:08 +0200219 * Fallthrough if the code above failed
wdenk42d1f032003-10-15 23:53:47 +0000220 * Initiate hard reset in debug control register DBCR0
221 * Make sure MSR[DE] = 1
222 */
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400223
Sergei Poselenov793670c2008-05-08 14:17:08 +0200224 msr = mfmsr ();
225 msr |= MSR_DE;
226 mtmsr (msr);
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400227
Sergei Poselenov793670c2008-05-08 14:17:08 +0200228 val = mfspr(DBCR0);
229 val |= 0x70000000;
230 mtspr(DBCR0,val);
231
wdenk42d1f032003-10-15 23:53:47 +0000232 return 1;
233}
234
235
236/*
237 * Get timebase clock frequency
238 */
239unsigned long get_tbclk (void)
240{
James Yang591933c2008-02-08 16:44:53 -0600241 return (gd->bus_clk + 4UL)/8UL;
wdenk42d1f032003-10-15 23:53:47 +0000242}
243
244
245#if defined(CONFIG_WATCHDOG)
246void
247watchdog_reset(void)
248{
249 int re_enable = disable_interrupts();
250 reset_85xx_watchdog();
251 if (re_enable) enable_interrupts();
252}
253
254void
255reset_85xx_watchdog(void)
256{
257 /*
258 * Clear TSR(WIS) bit by writing 1
259 */
260 unsigned long val;
Andy Fleming03b81b42007-04-23 01:44:44 -0500261 val = mfspr(SPRN_TSR);
262 val |= TSR_WIS;
263 mtspr(SPRN_TSR, val);
wdenk42d1f032003-10-15 23:53:47 +0000264}
265#endif /* CONFIG_WATCHDOG */
266
Sergei Poselenov740280e2008-06-06 15:42:40 +0200267/*
Sergei Poselenov59f63052008-08-15 15:42:11 +0200268 * Configures a UPM. The function requires the respective MxMR to be set
269 * before calling this function. "size" is the number or entries, not a sizeof.
Sergei Poselenov740280e2008-06-06 15:42:40 +0200270 */
271void upmconfig (uint upm, uint * table, uint size)
272{
273 int i, mdr, mad, old_mad = 0;
274 volatile u32 *mxmr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200276 volatile u32 *brp,*orp;
277 volatile u8* dummy = NULL;
278 int upmmask;
279
280 switch (upm) {
281 case UPMA:
282 mxmr = &lbc->mamr;
283 upmmask = BR_MS_UPMA;
284 break;
285 case UPMB:
286 mxmr = &lbc->mbmr;
287 upmmask = BR_MS_UPMB;
288 break;
289 case UPMC:
290 mxmr = &lbc->mcmr;
291 upmmask = BR_MS_UPMC;
292 break;
293 default:
294 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
295 hang();
296 }
297
298 /* Find the address for the dummy write transaction */
299 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
300 i++, brp += 2, orp += 2) {
Wolfgang Denke093a242008-06-28 23:34:37 +0200301
Sergei Poselenov740280e2008-06-06 15:42:40 +0200302 /* Look for a valid BR with selected UPM */
Sergei Poselenov59f63052008-08-15 15:42:11 +0200303 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
304 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200305 break;
306 }
307 }
308
309 if (i == 8) {
310 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
311 hang();
312 }
313
314 for (i = 0; i < size; i++) {
315 /* 1 */
Sergei Poselenov59f63052008-08-15 15:42:11 +0200316 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200317 /* 2 */
318 out_be32(&lbc->mdr, table[i]);
319 /* 3 */
320 mdr = in_be32(&lbc->mdr);
321 /* 4 */
322 *(volatile u8 *)dummy = 0;
323 /* 5 */
324 do {
Sergei Poselenov59f63052008-08-15 15:42:11 +0200325 mad = in_be32(mxmr) & MxMR_MAD_MSK;
Sergei Poselenov740280e2008-06-06 15:42:40 +0200326 } while (mad <= old_mad && !(!mad && i == (size-1)));
327 old_mad = mad;
328 }
Sergei Poselenov59f63052008-08-15 15:42:11 +0200329 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200330}
Ben Warrendd354792008-06-23 22:57:27 -0700331
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500332
333/*
334 * Initializes on-chip ethernet controllers.
335 * to override, implement board_eth_init()
Ben Warrendd354792008-06-23 22:57:27 -0700336 */
Ben Warrendd354792008-06-23 22:57:27 -0700337int cpu_eth_init(bd_t *bis)
338{
Ben Warren3456a142008-10-22 23:20:29 -0700339#if defined(CONFIG_ETHER_ON_FCC)
340 fec_initialize(bis);
341#endif
Haiying Wang8e552582009-06-04 16:12:41 -0400342
343#if defined(CONFIG_UEC_ETH)
344 uec_standard_init(bis);
Ben Warren0e8454e2008-10-22 23:32:48 -0700345#endif
Haiying Wang8e552582009-06-04 16:12:41 -0400346
Ben Warren62e15b42008-10-30 22:15:35 -0700347#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500348 tsec_standard_init(bis);
Ben Warrendd354792008-06-23 22:57:27 -0700349#endif
Andy Fleming80522dc2008-10-30 16:51:33 -0500350
Ben Warrendd354792008-06-23 22:57:27 -0700351 return 0;
352}
Andy Fleming80522dc2008-10-30 16:51:33 -0500353
354/*
355 * Initializes on-chip MMC controllers.
356 * to override, implement board_mmc_init()
357 */
358int cpu_mmc_init(bd_t *bis)
359{
360#ifdef CONFIG_FSL_ESDHC
361 return fsl_esdhc_mmc_init(bis);
362#else
363 return 0;
364#endif
365}