blob: a5b9fbd2257407bf606a53e49ca5a18a41c6f384 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -06007 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -07008
Simon Glass00606d72014-07-23 06:55:03 -06009 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060011 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070012 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060013 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060014 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass9cc36a22015-01-25 08:27:05 -070016 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060017 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070019 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070021 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -050022 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060024 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060026 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020027 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070028 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +020034 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060038 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020041 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020042 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060043 };
44
Simon Glassce6d99a2018-12-10 10:37:33 -070045 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glasse96fa6c2018-12-10 10:37:34 -070050 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060051 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré23f965a2019-10-07 15:29:05 +020079 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glass2e7d35d2014-02-26 15:59:21 -070083 a-test {
Simon Glass0503e822015-07-06 12:54:36 -060084 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070085 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -060086 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070087 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -060088 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -070089 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glassa1b17e42018-12-10 10:37:37 -070094 int-value = <1234>;
95 uint-value = <(-1234)>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070096 };
97
98 junk {
Simon Glass0503e822015-07-06 12:54:36 -060099 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700100 compatible = "not,compatible";
101 };
102
103 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600104 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700105 };
106
Simon Glass5d9a88f2018-10-01 12:22:40 -0600107 backlight: backlight {
108 compatible = "pwm-backlight";
109 enable-gpios = <&gpio_a 1>;
110 power-supply = <&ldo_1>;
111 pwms = <&pwm 0 1000>;
112 default-brightness-level = <5>;
113 brightness-levels = <0 16 32 64 128 170 202 234 255>;
114 };
115
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200116 bind-test {
117 bind-test-child1 {
118 compatible = "sandbox,phy";
119 #phy-cells = <1>;
120 };
121
122 bind-test-child2 {
123 compatible = "simple-bus";
124 };
125 };
126
Simon Glass2e7d35d2014-02-26 15:59:21 -0700127 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600128 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700129 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600130 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700131 ping-add = <3>;
132 };
133
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200134 phy_provider0: gen_phy@0 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 phy_provider1: gen_phy@1 {
140 compatible = "sandbox,phy";
141 #phy-cells = <0>;
142 broken;
143 };
144
145 gen_phy_user: gen_phy_user {
146 compatible = "simple-bus";
147 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
148 phy-names = "phy1", "phy2", "phy3";
149 };
150
Simon Glass2e7d35d2014-02-26 15:59:21 -0700151 some-bus {
152 #address-cells = <1>;
153 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600154 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600155 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600156 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700157 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600158 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700159 compatible = "denx,u-boot-fdt-test";
160 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600161 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700162 ping-add = <5>;
163 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600164 c-test@0 {
165 compatible = "denx,u-boot-fdt-test";
166 reg = <0>;
167 ping-expect = <6>;
168 ping-add = <6>;
169 };
170 c-test@1 {
171 compatible = "denx,u-boot-fdt-test";
172 reg = <1>;
173 ping-expect = <7>;
174 ping-add = <7>;
175 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700176 };
177
178 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600179 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600180 ping-expect = <6>;
181 ping-add = <6>;
182 compatible = "google,another-fdt-test";
183 };
184
185 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600186 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600187 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700188 ping-add = <6>;
189 compatible = "google,another-fdt-test";
190 };
191
Simon Glass9cc36a22015-01-25 08:27:05 -0700192 f-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
196 g-test {
197 compatible = "denx,u-boot-fdt-test";
198 };
199
Bin Meng2786cd72018-10-10 22:07:01 -0700200 h-test {
201 compatible = "denx,u-boot-fdt-test1";
202 };
203
Patrice Chotardee87a092017-09-04 14:55:57 +0200204 clocks {
205 clk_fixed: clk-fixed {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <1234>;
209 };
Anup Patelb630d572019-02-25 08:14:55 +0000210
211 clk_fixed_factor: clk-fixed-factor {
212 compatible = "fixed-factor-clock";
213 #clock-cells = <0>;
214 clock-div = <3>;
215 clock-mult = <2>;
216 clocks = <&clk_fixed>;
217 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200218
219 osc {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <20000000>;
223 };
Stephen Warren135aa952016-06-17 09:44:00 -0600224 };
225
226 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600227 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600228 #clock-cells = <1>;
229 };
230
231 clk-test {
232 compatible = "sandbox,clk-test";
233 clocks = <&clk_fixed>,
234 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200235 <&clk_sandbox 0>,
236 <&clk_sandbox 3>,
237 <&clk_sandbox 2>;
238 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600239 };
240
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200241 ccf: clk-ccf {
242 compatible = "sandbox,clk-ccf";
243 };
244
Simon Glass171e9912015-05-22 15:42:15 -0600245 eth@10002000 {
246 compatible = "sandbox,eth";
247 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500248 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600249 };
250
251 eth_5: eth@10003000 {
252 compatible = "sandbox,eth";
253 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500254 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600255 };
256
Bin Meng71d79712015-08-27 22:25:53 -0700257 eth_3: sbe5 {
258 compatible = "sandbox,eth";
259 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500260 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700261 };
262
Simon Glass171e9912015-05-22 15:42:15 -0600263 eth@10004000 {
264 compatible = "sandbox,eth";
265 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500266 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600267 };
268
Rajan Vaja31b82172018-09-19 03:43:46 -0700269 firmware {
270 sandbox_firmware: sandbox-firmware {
271 compatible = "sandbox,firmware";
272 };
273 };
274
Simon Glass0ae0cb72014-10-13 23:42:11 -0600275 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700276 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700277 gpio-controller;
278 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700279 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700280 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700281 };
282
Simon Glass3669e0e2015-01-05 20:05:29 -0700283 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700284 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700285 gpio-controller;
286 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700287 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700288 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700289 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600290
Simon Glassecc2ed52014-12-10 08:55:55 -0700291 i2c@0 {
292 #address-cells = <1>;
293 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600294 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700295 compatible = "sandbox,i2c";
296 clock-frequency = <100000>;
297 eeprom@2c {
298 reg = <0x2c>;
299 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700300 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700301 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200302
Simon Glass52d3bc52015-05-22 15:42:17 -0600303 rtc_0: rtc@43 {
304 reg = <0x43>;
305 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700306 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600307 };
308
309 rtc_1: rtc@61 {
310 reg = <0x61>;
311 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700312 sandbox,emul = <&emul1>;
313 };
314
315 i2c_emul: emul {
316 reg = <0xff>;
317 compatible = "sandbox,i2c-emul-parent";
318 emul_eeprom: emul-eeprom {
319 compatible = "sandbox,i2c-eeprom";
320 sandbox,filename = "i2c.bin";
321 sandbox,size = <256>;
322 };
323 emul0: emul0 {
324 compatible = "sandbox,i2c-rtc";
325 };
326 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600327 compatible = "sandbox,i2c-rtc";
328 };
329 };
330
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200331 sandbox_pmic: sandbox_pmic {
332 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700333 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200334 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200335
336 mc34708: pmic@41 {
337 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700338 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200339 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700340 };
341
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100342 bootcount@0 {
343 compatible = "u-boot,bootcount-rtc";
344 rtc = <&rtc_1>;
345 offset = <0x13>;
346 };
347
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100348 adc@0 {
349 compatible = "sandbox,adc";
350 vdd-supply = <&buck2>;
351 vss-microvolts = <0>;
352 };
353
Simon Glass3c97c4f2016-01-18 19:52:26 -0700354 lcd {
355 u-boot,dm-pre-reloc;
356 compatible = "sandbox,lcd-sdl";
357 xres = <1366>;
358 yres = <768>;
359 };
360
Simon Glass3c43fba2015-07-06 12:54:34 -0600361 leds {
362 compatible = "gpio-leds";
363
364 iracibble {
365 gpios = <&gpio_a 1 0>;
366 label = "sandbox:red";
367 };
368
369 martinet {
370 gpios = <&gpio_a 2 0>;
371 label = "sandbox:green";
372 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200373
374 default_on {
375 gpios = <&gpio_a 5 0>;
376 label = "sandbox:default_on";
377 default-state = "on";
378 };
379
380 default_off {
381 gpios = <&gpio_a 6 0>;
382 label = "sandbox:default_off";
383 default-state = "off";
384 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600385 };
386
Stephen Warren8961b522016-05-16 17:41:37 -0600387 mbox: mbox {
388 compatible = "sandbox,mbox";
389 #mbox-cells = <1>;
390 };
391
392 mbox-test {
393 compatible = "sandbox,mbox-test";
394 mboxes = <&mbox 100>, <&mbox 1>;
395 mbox-names = "other", "test";
396 };
397
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900398 cpus {
399 cpu-test1 {
400 compatible = "sandbox,cpu_sandbox";
401 u-boot,dm-pre-reloc;
402 };
Mario Sixfa44b532018-08-06 10:23:44 +0200403
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900404 cpu-test2 {
405 compatible = "sandbox,cpu_sandbox";
406 u-boot,dm-pre-reloc;
407 };
Mario Sixfa44b532018-08-06 10:23:44 +0200408
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900409 cpu-test3 {
410 compatible = "sandbox,cpu_sandbox";
411 u-boot,dm-pre-reloc;
412 };
Mario Sixfa44b532018-08-06 10:23:44 +0200413 };
414
Simon Glasse96fa6c2018-12-10 10:37:34 -0700415 i2s: i2s {
416 compatible = "sandbox,i2s";
417 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700418 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700419 };
420
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200421 nop-test_0 {
422 compatible = "sandbox,nop_sandbox1";
423 nop-test_1 {
424 compatible = "sandbox,nop_sandbox2";
425 bind = "True";
426 };
427 nop-test_2 {
428 compatible = "sandbox,nop_sandbox2";
429 bind = "False";
430 };
431 };
432
Mario Six004e67c2018-07-31 14:24:14 +0200433 misc-test {
434 compatible = "sandbox,misc_sandbox";
435 };
436
Simon Glasse48eeb92017-04-23 20:02:07 -0600437 mmc2 {
438 compatible = "sandbox,mmc";
439 };
440
441 mmc1 {
442 compatible = "sandbox,mmc";
443 };
444
445 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600446 compatible = "sandbox,mmc";
447 };
448
Simon Glassb45c8332019-02-16 20:24:50 -0700449 pch {
450 compatible = "sandbox,pch";
451 };
452
Bin Mengdee4d752018-08-03 01:14:41 -0700453 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700454 compatible = "sandbox,pci";
455 device_type = "pci";
456 #address-cells = <3>;
457 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600458 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700459 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700460 pci@0,0 {
461 compatible = "pci-generic";
462 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600463 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700464 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300465 pci@1,0 {
466 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600467 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
468 reg = <0x02000814 0 0 0 0
469 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600470 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300471 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700472 pci@1f,0 {
473 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600474 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
475 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600476 sandbox,emul = <&swap_case_emul0_1f>;
477 };
478 };
479
480 pci-emul0 {
481 compatible = "sandbox,pci-emul-parent";
482 swap_case_emul0_0: emul0@0,0 {
483 compatible = "sandbox,swap-case";
484 };
485 swap_case_emul0_1: emul0@1,0 {
486 compatible = "sandbox,swap-case";
487 use-ea;
488 };
489 swap_case_emul0_1f: emul0@1f,0 {
490 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700491 };
492 };
493
Bin Mengdee4d752018-08-03 01:14:41 -0700494 pci1: pci-controller1 {
495 compatible = "sandbox,pci";
496 device_type = "pci";
497 #address-cells = <3>;
498 #size-cells = <2>;
499 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
500 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700501 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200502 0x0c 0x00 0x1234 0x5678
503 0x10 0x00 0x1234 0x5678>;
504 pci@10,0 {
505 reg = <0x8000 0 0 0 0>;
506 };
Bin Mengdee4d752018-08-03 01:14:41 -0700507 };
508
Bin Meng3ed214a2018-08-03 01:14:50 -0700509 pci2: pci-controller2 {
510 compatible = "sandbox,pci";
511 device_type = "pci";
512 #address-cells = <3>;
513 #size-cells = <2>;
514 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
515 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
516 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
517 pci@1f,0 {
518 compatible = "pci-generic";
519 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600520 sandbox,emul = <&swap_case_emul2_1f>;
521 };
522 };
523
524 pci-emul2 {
525 compatible = "sandbox,pci-emul-parent";
526 swap_case_emul2_1f: emul2@1f,0 {
527 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700528 };
529 };
530
Ramon Friedbb413332019-04-27 11:15:23 +0300531 pci_ep: pci_ep {
532 compatible = "sandbox,pci_ep";
533 };
534
Simon Glass98561572017-04-23 20:10:44 -0600535 probing {
536 compatible = "simple-bus";
537 test1 {
538 compatible = "denx,u-boot-probe-test";
539 };
540
541 test2 {
542 compatible = "denx,u-boot-probe-test";
543 };
544
545 test3 {
546 compatible = "denx,u-boot-probe-test";
547 };
548
549 test4 {
550 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100551 first-syscon = <&syscon0>;
552 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100553 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600554 };
555 };
556
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600557 pwrdom: power-domain {
558 compatible = "sandbox,power-domain";
559 #power-domain-cells = <1>;
560 };
561
562 power-domain-test {
563 compatible = "sandbox,power-domain-test";
564 power-domains = <&pwrdom 2>;
565 };
566
Simon Glass5d9a88f2018-10-01 12:22:40 -0600567 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600568 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600569 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600570 };
571
572 pwm2 {
573 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600574 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600575 };
576
Simon Glass64ce0ca2015-07-06 12:54:31 -0600577 ram {
578 compatible = "sandbox,ram";
579 };
580
Simon Glass5010d982015-07-06 12:54:29 -0600581 reset@0 {
582 compatible = "sandbox,warm-reset";
583 };
584
585 reset@1 {
586 compatible = "sandbox,reset";
587 };
588
Stephen Warren4581b712016-06-17 09:43:59 -0600589 resetc: reset-ctl {
590 compatible = "sandbox,reset-ctl";
591 #reset-cells = <1>;
592 };
593
594 reset-ctl-test {
595 compatible = "sandbox,reset-ctl-test";
596 resets = <&resetc 100>, <&resetc 2>;
597 reset-names = "other", "test";
598 };
599
Nishanth Menon52159402015-09-17 15:42:41 -0500600 rproc_1: rproc@1 {
601 compatible = "sandbox,test-processor";
602 remoteproc-name = "remoteproc-test-dev1";
603 };
604
605 rproc_2: rproc@2 {
606 compatible = "sandbox,test-processor";
607 internal-memory-mapped;
608 remoteproc-name = "remoteproc-test-dev2";
609 };
610
Simon Glass5d9a88f2018-10-01 12:22:40 -0600611 panel {
612 compatible = "simple-panel";
613 backlight = <&backlight 0 100>;
614 };
615
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300616 smem@0 {
617 compatible = "sandbox,smem";
618 };
619
Simon Glassd4901892018-12-10 10:37:36 -0700620 sound {
621 compatible = "sandbox,sound";
622 cpu {
623 sound-dai = <&i2s 0>;
624 };
625
626 codec {
627 sound-dai = <&audio 0>;
628 };
629 };
630
Simon Glass0ae0cb72014-10-13 23:42:11 -0600631 spi@0 {
632 #address-cells = <1>;
633 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600634 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600635 compatible = "sandbox,spi";
636 cs-gpios = <0>, <&gpio_a 0>;
637 spi.bin@0 {
638 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000639 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600640 spi-max-frequency = <40000000>;
641 sandbox,filename = "spi.bin";
642 };
643 };
644
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100645 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600646 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200647 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600648 };
649
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100650 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600651 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600652 reg = <0x20 5
653 0x28 6
654 0x30 7
655 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600656 };
657
Patrick Delaunaya442e612019-03-07 09:57:13 +0100658 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900659 compatible = "simple-mfd", "syscon";
660 reg = <0x40 5
661 0x48 6
662 0x50 7
663 0x58 8>;
664 };
665
Thomas Choue7cc8d12015-12-11 16:27:34 +0800666 timer {
667 compatible = "sandbox,timer";
668 clock-frequency = <1000000>;
669 };
670
Miquel Raynalb91ad162018-05-15 11:57:27 +0200671 tpm2 {
672 compatible = "sandbox,tpm2";
673 };
674
Simon Glass171e9912015-05-22 15:42:15 -0600675 uart0: serial {
676 compatible = "sandbox,serial";
677 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500678 };
679
Simon Glasse00cb222015-03-25 12:23:05 -0600680 usb_0: usb@0 {
681 compatible = "sandbox,usb";
682 status = "disabled";
683 hub {
684 compatible = "sandbox,usb-hub";
685 #address-cells = <1>;
686 #size-cells = <0>;
687 flash-stick {
688 reg = <0>;
689 compatible = "sandbox,usb-flash";
690 };
691 };
692 };
693
694 usb_1: usb@1 {
695 compatible = "sandbox,usb";
696 hub {
697 compatible = "usb-hub";
698 usb,device-class = <9>;
699 hub-emul {
700 compatible = "sandbox,usb-hub";
701 #address-cells = <1>;
702 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700703 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600704 reg = <0>;
705 compatible = "sandbox,usb-flash";
706 sandbox,filepath = "testflash.bin";
707 };
708
Simon Glass431cbd62015-11-08 23:48:01 -0700709 flash-stick@1 {
710 reg = <1>;
711 compatible = "sandbox,usb-flash";
712 sandbox,filepath = "testflash1.bin";
713 };
714
715 flash-stick@2 {
716 reg = <2>;
717 compatible = "sandbox,usb-flash";
718 sandbox,filepath = "testflash2.bin";
719 };
720
Simon Glassbff1a712015-11-08 23:48:08 -0700721 keyb@3 {
722 reg = <3>;
723 compatible = "sandbox,usb-keyb";
724 };
725
Simon Glasse00cb222015-03-25 12:23:05 -0600726 };
727 };
728 };
729
730 usb_2: usb@2 {
731 compatible = "sandbox,usb";
732 status = "disabled";
733 };
734
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200735 spmi: spmi@0 {
736 compatible = "sandbox,spmi";
737 #address-cells = <0x1>;
738 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600739 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200740 pm8916@0 {
741 compatible = "qcom,spmi-pmic";
742 reg = <0x0 0x1>;
743 #address-cells = <0x1>;
744 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600745 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200746
747 spmi_gpios: gpios@c000 {
748 compatible = "qcom,pm8916-gpio";
749 reg = <0xc000 0x400>;
750 gpio-controller;
751 gpio-count = <4>;
752 #gpio-cells = <2>;
753 gpio-bank-name="spmi";
754 };
755 };
756 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700757
758 wdt0: wdt@0 {
759 compatible = "sandbox,wdt";
760 };
Rob Clarkf2006802018-01-10 11:33:30 +0100761
Mario Six957983e2018-08-09 14:51:19 +0200762 axi: axi@0 {
763 compatible = "sandbox,axi";
764 #address-cells = <0x1>;
765 #size-cells = <0x1>;
766 store@0 {
767 compatible = "sandbox,sandbox_store";
768 reg = <0x0 0x400>;
769 };
770 };
771
Rob Clarkf2006802018-01-10 11:33:30 +0100772 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700773 #address-cells = <1>;
774 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100775 chosen-test {
776 compatible = "denx,u-boot-fdt-test";
777 reg = <9 1>;
778 };
779 };
Mario Sixe8d52912018-03-12 14:53:33 +0100780
781 translation-test@8000 {
782 compatible = "simple-bus";
783 reg = <0x8000 0x4000>;
784
785 #address-cells = <0x2>;
786 #size-cells = <0x1>;
787
788 ranges = <0 0x0 0x8000 0x1000
789 1 0x100 0x9000 0x1000
790 2 0x200 0xA000 0x1000
791 3 0x300 0xB000 0x1000
792 >;
793
Fabien Dessenne641067f2019-05-31 15:11:30 +0200794 dma-ranges = <0 0x000 0x10000000 0x1000
795 1 0x100 0x20000000 0x1000
796 >;
797
Mario Sixe8d52912018-03-12 14:53:33 +0100798 dev@0,0 {
799 compatible = "denx,u-boot-fdt-dummy";
800 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100801 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100802 };
803
804 dev@1,100 {
805 compatible = "denx,u-boot-fdt-dummy";
806 reg = <1 0x100 0x1000>;
807
808 };
809
810 dev@2,200 {
811 compatible = "denx,u-boot-fdt-dummy";
812 reg = <2 0x200 0x1000>;
813 };
814
815
816 noxlatebus@3,300 {
817 compatible = "simple-bus";
818 reg = <3 0x300 0x1000>;
819
820 #address-cells = <0x1>;
821 #size-cells = <0x0>;
822
823 dev@42 {
824 compatible = "denx,u-boot-fdt-dummy";
825 reg = <0x42>;
826 };
827 };
828 };
Mario Six4eea5312018-09-27 09:19:31 +0200829
830 osd {
831 compatible = "sandbox,sandbox_osd";
832 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400833
Mario Sixe6fd0182018-07-31 11:44:13 +0200834 board {
835 compatible = "sandbox,board_sandbox";
836 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200837
838 sandbox_tee {
839 compatible = "sandbox,tee";
840 };
Bin Meng4f89d492018-10-15 02:21:26 -0700841
842 sandbox_virtio1 {
843 compatible = "sandbox,virtio1";
844 };
845
846 sandbox_virtio2 {
847 compatible = "sandbox,virtio2";
848 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200849
850 pinctrl {
851 compatible = "sandbox,pinctrl";
852 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +0100853
854 hwspinlock@0 {
855 compatible = "sandbox,hwspinlock";
856 };
Grygorii Strashkob3309912018-11-28 19:17:51 +0100857
858 dma: dma {
859 compatible = "sandbox,dma";
860 #dma-cells = <1>;
861
862 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
863 dma-names = "m2m", "tx0", "rx0";
864 };
Alex Margineanec9594a2019-06-03 19:12:28 +0300865
Alex Margineanc3d9f3f2019-07-12 10:13:53 +0300866 /*
867 * keep mdio-mux ahead of mdio so that the mux is removed first at the
868 * end of the test. If parent mdio is removed first, clean-up of the
869 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
870 * active at the end of the test. That it turn doesn't allow the mdio
871 * class to be destroyed, triggering an error.
872 */
873 mdio-mux-test {
874 compatible = "sandbox,mdio-mux";
875 #address-cells = <1>;
876 #size-cells = <0>;
877 mdio-parent-bus = <&mdio>;
878
879 mdio-ch-test@0 {
880 reg = <0>;
881 };
882 mdio-ch-test@1 {
883 reg = <1>;
884 };
885 };
886
887 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +0300888 compatible = "sandbox,mdio";
889 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700890};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200891
892#include "sandbox_pmic.dtsi"