Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | menu "MIPS architecture" |
| 2 | depends on MIPS |
| 3 | |
| 4 | config SYS_ARCH |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 5 | default "mips" |
| 6 | |
Daniel Schwierzeck | b9863b6 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 7 | config SYS_CPU |
Paul Burton | 20286cd | 2016-05-16 10:52:11 +0100 | [diff] [blame] | 8 | default "mips32" if CPU_MIPS32 |
| 9 | default "mips64" if CPU_MIPS64 |
Daniel Schwierzeck | b9863b6 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 10 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 11 | choice |
| 12 | prompt "Target select" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 13 | optional |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 14 | |
| 15 | config TARGET_QEMU_MIPS |
| 16 | bool "Support qemu-mips" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 17 | select SUPPORTS_BIG_ENDIAN |
| 18 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 19 | select SUPPORTS_CPU_MIPS32_R1 |
| 20 | select SUPPORTS_CPU_MIPS32_R2 |
Daniel Schwierzeck | aa45f75 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 21 | select SUPPORTS_CPU_MIPS64_R1 |
| 22 | select SUPPORTS_CPU_MIPS64_R2 |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 23 | select ROM_EXCEPTION_VECTORS |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 24 | |
| 25 | config TARGET_MALTA |
| 26 | bool "Support malta" |
Paul Burton | 6242aa1 | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 27 | select DM |
| 28 | select DM_SERIAL |
Paul Burton | 05e3425 | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 29 | select DYNAMIC_IO_PORT_BASE |
Paul Burton | 566ce04d | 2016-09-21 11:18:56 +0100 | [diff] [blame] | 30 | select MIPS_CM |
| 31 | select MIPS_L2_CACHE |
Paul Burton | 6242aa1 | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 32 | select OF_CONTROL |
| 33 | select OF_ISA_BUS |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 34 | select SUPPORTS_BIG_ENDIAN |
| 35 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 36 | select SUPPORTS_CPU_MIPS32_R1 |
| 37 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 40ba13c | 2016-05-16 10:52:14 +0100 | [diff] [blame] | 38 | select SUPPORTS_CPU_MIPS32_R6 |
Paul Burton | 0f832b9 | 2016-05-26 14:49:36 +0100 | [diff] [blame] | 39 | select SUPPORTS_CPU_MIPS64_R1 |
| 40 | select SUPPORTS_CPU_MIPS64_R2 |
| 41 | select SUPPORTS_CPU_MIPS64_R6 |
Daniel Schwierzeck | 9d638ee | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 42 | select SWAP_IO_SPACE |
Daniel Schwierzeck | f53830e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 43 | select MIPS_L1_CACHE_SHIFT_6 |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 44 | select ROM_EXCEPTION_VECTORS |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 45 | |
| 46 | config TARGET_VCT |
| 47 | bool "Support vct" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 48 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 49 | select SUPPORTS_CPU_MIPS32_R1 |
| 50 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 51 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 52 | select ROM_EXCEPTION_VECTORS |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 53 | |
| 54 | config TARGET_DBAU1X00 |
| 55 | bool "Support dbau1x00" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 56 | select SUPPORTS_BIG_ENDIAN |
| 57 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 58 | select SUPPORTS_CPU_MIPS32_R1 |
| 59 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 60 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 61 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | 0315a28 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 62 | select MIPS_TUNE_4KC |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 63 | |
| 64 | config TARGET_PB1X00 |
| 65 | bool "Support pb1x00" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 66 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 67 | select SUPPORTS_CPU_MIPS32_R1 |
| 68 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 69 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 70 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | 0315a28 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 71 | select MIPS_TUNE_4KC |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 72 | |
Wills Wang | 1d3d0f1 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 73 | config ARCH_ATH79 |
| 74 | bool "Support QCA/Atheros ath79" |
| 75 | select OF_CONTROL |
| 76 | select DM |
| 77 | |
Álvaro Fernández Rojas | ee42214 | 2017-04-25 00:39:20 +0200 | [diff] [blame^] | 78 | config ARCH_BMIPS |
| 79 | bool "Support BMIPS SoCs" |
| 80 | select OF_CONTROL |
| 81 | select DM |
| 82 | select CLK |
| 83 | select CPU |
| 84 | select RAM |
| 85 | select SYSRESET |
| 86 | |
Purna Chandra Mandal | 32c1a6e | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 87 | config MACH_PIC32 |
| 88 | bool "Support Microchip PIC32" |
| 89 | select OF_CONTROL |
| 90 | select DM |
| 91 | |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 92 | config TARGET_BOSTON |
| 93 | bool "Support Boston" |
| 94 | select DM |
| 95 | select DM_SERIAL |
| 96 | select OF_CONTROL |
| 97 | select MIPS_CM |
| 98 | select MIPS_L1_CACHE_SHIFT_6 |
| 99 | select MIPS_L2_CACHE |
| 100 | select SUPPORTS_BIG_ENDIAN |
| 101 | select SUPPORTS_LITTLE_ENDIAN |
| 102 | select SUPPORTS_CPU_MIPS32_R1 |
| 103 | select SUPPORTS_CPU_MIPS32_R2 |
| 104 | select SUPPORTS_CPU_MIPS32_R6 |
| 105 | select SUPPORTS_CPU_MIPS64_R1 |
| 106 | select SUPPORTS_CPU_MIPS64_R2 |
| 107 | select SUPPORTS_CPU_MIPS64_R6 |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 108 | select ROM_EXCEPTION_VECTORS |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 109 | |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 110 | config TARGET_XILFPGA |
| 111 | bool "Support Imagination Xilfpga" |
| 112 | select OF_CONTROL |
| 113 | select DM |
| 114 | select DM_SERIAL |
| 115 | select DM_GPIO |
| 116 | select DM_ETH |
| 117 | select SUPPORTS_LITTLE_ENDIAN |
| 118 | select SUPPORTS_CPU_MIPS32_R1 |
| 119 | select SUPPORTS_CPU_MIPS32_R2 |
| 120 | select MIPS_L1_CACHE_SHIFT_4 |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 121 | select ROM_EXCEPTION_VECTORS |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 122 | help |
| 123 | This supports IMGTEC MIPSfpga platform |
| 124 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 125 | endchoice |
| 126 | |
| 127 | source "board/dbau1x00/Kconfig" |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 128 | source "board/imgtec/boston/Kconfig" |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 129 | source "board/imgtec/malta/Kconfig" |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 130 | source "board/imgtec/xilfpga/Kconfig" |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 131 | source "board/micronas/vct/Kconfig" |
| 132 | source "board/pb1x00/Kconfig" |
| 133 | source "board/qemu-mips/Kconfig" |
Wills Wang | 1d3d0f1 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 134 | source "arch/mips/mach-ath79/Kconfig" |
Álvaro Fernández Rojas | ee42214 | 2017-04-25 00:39:20 +0200 | [diff] [blame^] | 135 | source "arch/mips/mach-bmips/Kconfig" |
Purna Chandra Mandal | 32c1a6e | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 136 | source "arch/mips/mach-pic32/Kconfig" |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 137 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 138 | if MIPS |
| 139 | |
| 140 | choice |
| 141 | prompt "Endianness selection" |
| 142 | help |
| 143 | Some MIPS boards can be configured for either little or big endian |
| 144 | byte order. These modes require different U-Boot images. In general there |
| 145 | is one preferred byteorder for a particular system but some systems are |
| 146 | just as commonly used in the one or the other endianness. |
| 147 | |
| 148 | config SYS_BIG_ENDIAN |
| 149 | bool "Big endian" |
| 150 | depends on SUPPORTS_BIG_ENDIAN |
| 151 | |
| 152 | config SYS_LITTLE_ENDIAN |
| 153 | bool "Little endian" |
| 154 | depends on SUPPORTS_LITTLE_ENDIAN |
| 155 | |
| 156 | endchoice |
| 157 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 158 | choice |
| 159 | prompt "CPU selection" |
| 160 | default CPU_MIPS32_R2 |
| 161 | |
| 162 | config CPU_MIPS32_R1 |
| 163 | bool "MIPS32 Release 1" |
| 164 | depends on SUPPORTS_CPU_MIPS32_R1 |
| 165 | select 32BIT |
| 166 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 167 | Choose this option to build an U-Boot for release 1 through 5 of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 168 | MIPS32 architecture. |
| 169 | |
| 170 | config CPU_MIPS32_R2 |
| 171 | bool "MIPS32 Release 2" |
| 172 | depends on SUPPORTS_CPU_MIPS32_R2 |
| 173 | select 32BIT |
| 174 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 175 | Choose this option to build an U-Boot for release 2 through 5 of the |
| 176 | MIPS32 architecture. |
| 177 | |
| 178 | config CPU_MIPS32_R6 |
| 179 | bool "MIPS32 Release 6" |
| 180 | depends on SUPPORTS_CPU_MIPS32_R6 |
| 181 | select 32BIT |
| 182 | help |
| 183 | Choose this option to build an U-Boot for release 6 or later of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 184 | MIPS32 architecture. |
| 185 | |
| 186 | config CPU_MIPS64_R1 |
| 187 | bool "MIPS64 Release 1" |
| 188 | depends on SUPPORTS_CPU_MIPS64_R1 |
| 189 | select 64BIT |
| 190 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 191 | Choose this option to build a kernel for release 1 through 5 of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 192 | MIPS64 architecture. |
| 193 | |
| 194 | config CPU_MIPS64_R2 |
| 195 | bool "MIPS64 Release 2" |
| 196 | depends on SUPPORTS_CPU_MIPS64_R2 |
| 197 | select 64BIT |
| 198 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 199 | Choose this option to build a kernel for release 2 through 5 of the |
| 200 | MIPS64 architecture. |
| 201 | |
| 202 | config CPU_MIPS64_R6 |
| 203 | bool "MIPS64 Release 6" |
| 204 | depends on SUPPORTS_CPU_MIPS64_R6 |
| 205 | select 64BIT |
| 206 | help |
| 207 | Choose this option to build a kernel for release 6 or later of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 208 | MIPS64 architecture. |
| 209 | |
| 210 | endchoice |
| 211 | |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 212 | menu "General setup" |
| 213 | |
| 214 | config ROM_EXCEPTION_VECTORS |
| 215 | bool "Build U-Boot image with exception vectors" |
| 216 | help |
| 217 | Enable this to include exception vectors in the U-Boot image. This is |
| 218 | required if the U-Boot entry point is equal to the address of the |
| 219 | CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, |
| 220 | U-Boot booted from parallel NOR flash). |
| 221 | Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). |
| 222 | In that case the image size will be reduced by 0x500 bytes. |
| 223 | |
| 224 | endmenu |
| 225 | |
Daniel Schwierzeck | 25fc664 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 226 | menu "OS boot interface" |
| 227 | |
| 228 | config MIPS_BOOT_CMDLINE_LEGACY |
| 229 | bool "Hand over legacy command line to Linux kernel" |
| 230 | default y |
| 231 | help |
| 232 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 233 | command line to the kernel. All bootargs will be prepared as argc/argv |
| 234 | compatible list. The argument count (argc) is stored in register $a0. |
| 235 | The address of the argument list (argv) is stored in register $a1. |
| 236 | |
Daniel Schwierzeck | ca65e58 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 237 | config MIPS_BOOT_ENV_LEGACY |
| 238 | bool "Hand over legacy environment to Linux kernel" |
| 239 | default y |
| 240 | help |
| 241 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 242 | environment to the kernel. Information like memory size, initrd |
| 243 | address and size will be prepared as zero-terminated key/value list. |
Robert P. J. Day | 1cc0a9f | 2016-05-04 04:47:31 -0400 | [diff] [blame] | 244 | The address of the environment is stored in register $a2. |
Daniel Schwierzeck | ca65e58 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 245 | |
Daniel Schwierzeck | 5002d8c | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 246 | config MIPS_BOOT_FDT |
Daniel Schwierzeck | 90b1c9f | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 247 | bool "Hand over a flattened device tree to Linux kernel" |
Daniel Schwierzeck | 5002d8c | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 248 | default n |
| 249 | help |
| 250 | Enable this option if you want U-Boot to hand over a flattened |
Daniel Schwierzeck | 90b1c9f | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 251 | device tree to the kernel. According to UHI register $a0 will be set |
| 252 | to -2 and the FDT address is stored in $a1. |
Daniel Schwierzeck | 5002d8c | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 253 | |
Daniel Schwierzeck | 25fc664 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 254 | endmenu |
| 255 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 256 | config SUPPORTS_BIG_ENDIAN |
| 257 | bool |
| 258 | |
| 259 | config SUPPORTS_LITTLE_ENDIAN |
| 260 | bool |
| 261 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 262 | config SUPPORTS_CPU_MIPS32_R1 |
| 263 | bool |
| 264 | |
| 265 | config SUPPORTS_CPU_MIPS32_R2 |
| 266 | bool |
| 267 | |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 268 | config SUPPORTS_CPU_MIPS32_R6 |
| 269 | bool |
| 270 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 271 | config SUPPORTS_CPU_MIPS64_R1 |
| 272 | bool |
| 273 | |
| 274 | config SUPPORTS_CPU_MIPS64_R2 |
| 275 | bool |
| 276 | |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 277 | config SUPPORTS_CPU_MIPS64_R6 |
| 278 | bool |
| 279 | |
Daniel Schwierzeck | c57dafb | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 280 | config CPU_MIPS32 |
| 281 | bool |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 282 | default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 |
Daniel Schwierzeck | c57dafb | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 283 | |
| 284 | config CPU_MIPS64 |
| 285 | bool |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 286 | default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 |
Daniel Schwierzeck | c57dafb | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 287 | |
Daniel Schwierzeck | 0315a28 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 288 | config MIPS_TUNE_4KC |
| 289 | bool |
| 290 | |
| 291 | config MIPS_TUNE_14KC |
| 292 | bool |
| 293 | |
| 294 | config MIPS_TUNE_24KC |
| 295 | bool |
| 296 | |
Daniel Schwierzeck | 5f9cc36 | 2016-05-27 15:39:39 +0200 | [diff] [blame] | 297 | config MIPS_TUNE_34KC |
| 298 | bool |
| 299 | |
Marek Vasut | 0a0a958 | 2016-05-06 20:10:33 +0200 | [diff] [blame] | 300 | config MIPS_TUNE_74KC |
| 301 | bool |
| 302 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 303 | config 32BIT |
| 304 | bool |
| 305 | |
| 306 | config 64BIT |
| 307 | bool |
| 308 | |
Daniel Schwierzeck | 9d638ee | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 309 | config SWAP_IO_SPACE |
| 310 | bool |
| 311 | |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 312 | config SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 313 | bool |
| 314 | |
Daniel Schwierzeck | 924ad86 | 2016-06-04 16:13:21 +0200 | [diff] [blame] | 315 | config MIPS_INIT_STACK_IN_SRAM |
| 316 | bool |
| 317 | default n |
| 318 | help |
| 319 | Select this if the initial stack frame could be setup in SRAM. |
| 320 | Normally the initial stack frame is set up in DRAM which is often |
| 321 | only available after lowlevel_init. With this option the initial |
| 322 | stack frame and the early C environment is set up before |
| 323 | lowlevel_init. Thus lowlevel_init does not need to be implemented |
| 324 | in assembler. |
| 325 | |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 326 | config SYS_DCACHE_SIZE |
| 327 | int |
| 328 | default 0 |
| 329 | help |
| 330 | The total size of the L1 Dcache, if known at compile time. |
| 331 | |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 332 | config SYS_DCACHE_LINE_SIZE |
Paul Burton | 4b7b0a0 | 2016-06-09 13:09:52 +0100 | [diff] [blame] | 333 | int |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 334 | default 0 |
| 335 | help |
| 336 | The size of L1 Dcache lines, if known at compile time. |
| 337 | |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 338 | config SYS_ICACHE_SIZE |
| 339 | int |
| 340 | default 0 |
| 341 | help |
| 342 | The total size of the L1 ICache, if known at compile time. |
| 343 | |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 344 | config SYS_ICACHE_LINE_SIZE |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 345 | int |
| 346 | default 0 |
| 347 | help |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 348 | The size of L1 Icache lines, if known at compile time. |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 349 | |
| 350 | config SYS_CACHE_SIZE_AUTO |
| 351 | def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 352 | SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 353 | help |
| 354 | Select this (or let it be auto-selected by not defining any cache |
| 355 | sizes) in order to allow U-Boot to automatically detect the sizes |
| 356 | of caches at runtime. This has a small cost in code size & runtime |
| 357 | so if you know the cache configuration for your system at compile |
| 358 | time it would be beneficial to configure it. |
| 359 | |
Daniel Schwierzeck | f53830e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 360 | config MIPS_L1_CACHE_SHIFT_4 |
| 361 | bool |
| 362 | |
| 363 | config MIPS_L1_CACHE_SHIFT_5 |
| 364 | bool |
| 365 | |
| 366 | config MIPS_L1_CACHE_SHIFT_6 |
| 367 | bool |
| 368 | |
| 369 | config MIPS_L1_CACHE_SHIFT_7 |
| 370 | bool |
| 371 | |
| 372 | config MIPS_L1_CACHE_SHIFT |
| 373 | int |
| 374 | default "7" if MIPS_L1_CACHE_SHIFT_7 |
| 375 | default "6" if MIPS_L1_CACHE_SHIFT_6 |
| 376 | default "5" if MIPS_L1_CACHE_SHIFT_5 |
| 377 | default "4" if MIPS_L1_CACHE_SHIFT_4 |
| 378 | default "5" |
| 379 | |
Paul Burton | 4baa0ab | 2016-09-21 11:18:54 +0100 | [diff] [blame] | 380 | config MIPS_L2_CACHE |
| 381 | bool |
| 382 | help |
| 383 | Select this if your system includes an L2 cache and you want U-Boot |
| 384 | to initialise & maintain it. |
| 385 | |
Paul Burton | 05e3425 | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 386 | config DYNAMIC_IO_PORT_BASE |
| 387 | bool |
| 388 | |
Paul Burton | b2b135d | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 389 | config MIPS_CM |
| 390 | bool |
| 391 | help |
| 392 | Select this if your system contains a MIPS Coherence Manager and you |
| 393 | wish U-Boot to configure it or make use of it to retrieve system |
| 394 | information such as cache configuration. |
| 395 | |
| 396 | config MIPS_CM_BASE |
| 397 | hex |
| 398 | default 0x1fbf8000 |
| 399 | help |
| 400 | The physical base address at which to map the MIPS Coherence Manager |
| 401 | Global Configuration Registers (GCRs). This should be set such that |
| 402 | the GCRs occupy a region of the physical address space which is |
| 403 | otherwise unused, or at minimum that software doesn't need to access. |
| 404 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 405 | endif |
| 406 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 407 | endmenu |