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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010017 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010019 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +010021 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010023 select ROM_EXCEPTION_VECTORS
Masahiro Yamadadd840582014-07-30 14:08:14 +090024
25config TARGET_MALTA
26 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +010027 select DM
28 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +000029 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +010030 select MIPS_CM
31 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +010032 select OF_CONTROL
33 select OF_ISA_BUS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010034 select SUPPORTS_BIG_ENDIAN
35 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010036 select SUPPORTS_CPU_MIPS32_R1
37 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010038 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010039 select SUPPORTS_CPU_MIPS64_R1
40 select SUPPORTS_CPU_MIPS64_R2
41 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010042 select SWAP_IO_SPACE
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +010043 select MIPS_L1_CACHE_SHIFT_6
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010044 select ROM_EXCEPTION_VECTORS
Masahiro Yamadadd840582014-07-30 14:08:14 +090045
46config TARGET_VCT
47 bool "Support vct"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010048 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010049 select SUPPORTS_CPU_MIPS32_R1
50 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000051 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010052 select ROM_EXCEPTION_VECTORS
Masahiro Yamadadd840582014-07-30 14:08:14 +090053
54config TARGET_DBAU1X00
55 bool "Support dbau1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010056 select SUPPORTS_BIG_ENDIAN
57 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010058 select SUPPORTS_CPU_MIPS32_R1
59 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000060 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010061 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010062 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090063
64config TARGET_PB1X00
65 bool "Support pb1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010066 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010067 select SUPPORTS_CPU_MIPS32_R1
68 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000069 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +010070 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010071 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090072
Wills Wang1d3d0f12016-03-16 16:59:52 +080073config ARCH_ATH79
74 bool "Support QCA/Atheros ath79"
75 select OF_CONTROL
76 select DM
77
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020078config ARCH_BMIPS
79 bool "Support BMIPS SoCs"
80 select OF_CONTROL
81 select DM
82 select CLK
83 select CPU
84 select RAM
85 select SYSRESET
86
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053087config MACH_PIC32
88 bool "Support Microchip PIC32"
89 select OF_CONTROL
90 select DM
91
Paul Burtonad8783c2016-09-08 07:47:39 +010092config TARGET_BOSTON
93 bool "Support Boston"
94 select DM
95 select DM_SERIAL
96 select OF_CONTROL
97 select MIPS_CM
98 select MIPS_L1_CACHE_SHIFT_6
99 select MIPS_L2_CACHE
100 select SUPPORTS_BIG_ENDIAN
101 select SUPPORTS_LITTLE_ENDIAN
102 select SUPPORTS_CPU_MIPS32_R1
103 select SUPPORTS_CPU_MIPS32_R2
104 select SUPPORTS_CPU_MIPS32_R6
105 select SUPPORTS_CPU_MIPS64_R1
106 select SUPPORTS_CPU_MIPS64_R2
107 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100108 select ROM_EXCEPTION_VECTORS
Paul Burtonad8783c2016-09-08 07:47:39 +0100109
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100110config TARGET_XILFPGA
111 bool "Support Imagination Xilfpga"
112 select OF_CONTROL
113 select DM
114 select DM_SERIAL
115 select DM_GPIO
116 select DM_ETH
117 select SUPPORTS_LITTLE_ENDIAN
118 select SUPPORTS_CPU_MIPS32_R1
119 select SUPPORTS_CPU_MIPS32_R2
120 select MIPS_L1_CACHE_SHIFT_4
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100121 select ROM_EXCEPTION_VECTORS
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100122 help
123 This supports IMGTEC MIPSfpga platform
124
Masahiro Yamadadd840582014-07-30 14:08:14 +0900125endchoice
126
127source "board/dbau1x00/Kconfig"
Paul Burtonad8783c2016-09-08 07:47:39 +0100128source "board/imgtec/boston/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900129source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100130source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900131source "board/micronas/vct/Kconfig"
132source "board/pb1x00/Kconfig"
133source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800134source "arch/mips/mach-ath79/Kconfig"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +0200135source "arch/mips/mach-bmips/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530136source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900137
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100138if MIPS
139
140choice
141 prompt "Endianness selection"
142 help
143 Some MIPS boards can be configured for either little or big endian
144 byte order. These modes require different U-Boot images. In general there
145 is one preferred byteorder for a particular system but some systems are
146 just as commonly used in the one or the other endianness.
147
148config SYS_BIG_ENDIAN
149 bool "Big endian"
150 depends on SUPPORTS_BIG_ENDIAN
151
152config SYS_LITTLE_ENDIAN
153 bool "Little endian"
154 depends on SUPPORTS_LITTLE_ENDIAN
155
156endchoice
157
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100158choice
159 prompt "CPU selection"
160 default CPU_MIPS32_R2
161
162config CPU_MIPS32_R1
163 bool "MIPS32 Release 1"
164 depends on SUPPORTS_CPU_MIPS32_R1
165 select 32BIT
166 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100167 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100168 MIPS32 architecture.
169
170config CPU_MIPS32_R2
171 bool "MIPS32 Release 2"
172 depends on SUPPORTS_CPU_MIPS32_R2
173 select 32BIT
174 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100175 Choose this option to build an U-Boot for release 2 through 5 of the
176 MIPS32 architecture.
177
178config CPU_MIPS32_R6
179 bool "MIPS32 Release 6"
180 depends on SUPPORTS_CPU_MIPS32_R6
181 select 32BIT
182 help
183 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100184 MIPS32 architecture.
185
186config CPU_MIPS64_R1
187 bool "MIPS64 Release 1"
188 depends on SUPPORTS_CPU_MIPS64_R1
189 select 64BIT
190 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100191 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100192 MIPS64 architecture.
193
194config CPU_MIPS64_R2
195 bool "MIPS64 Release 2"
196 depends on SUPPORTS_CPU_MIPS64_R2
197 select 64BIT
198 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100199 Choose this option to build a kernel for release 2 through 5 of the
200 MIPS64 architecture.
201
202config CPU_MIPS64_R6
203 bool "MIPS64 Release 6"
204 depends on SUPPORTS_CPU_MIPS64_R6
205 select 64BIT
206 help
207 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100208 MIPS64 architecture.
209
210endchoice
211
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100212menu "General setup"
213
214config ROM_EXCEPTION_VECTORS
215 bool "Build U-Boot image with exception vectors"
216 help
217 Enable this to include exception vectors in the U-Boot image. This is
218 required if the U-Boot entry point is equal to the address of the
219 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
220 U-Boot booted from parallel NOR flash).
221 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
222 In that case the image size will be reduced by 0x500 bytes.
223
224endmenu
225
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100226menu "OS boot interface"
227
228config MIPS_BOOT_CMDLINE_LEGACY
229 bool "Hand over legacy command line to Linux kernel"
230 default y
231 help
232 Enable this option if you want U-Boot to hand over the Yamon-style
233 command line to the kernel. All bootargs will be prepared as argc/argv
234 compatible list. The argument count (argc) is stored in register $a0.
235 The address of the argument list (argv) is stored in register $a1.
236
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100237config MIPS_BOOT_ENV_LEGACY
238 bool "Hand over legacy environment to Linux kernel"
239 default y
240 help
241 Enable this option if you want U-Boot to hand over the Yamon-style
242 environment to the kernel. Information like memory size, initrd
243 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400244 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100245
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100246config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100247 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100248 default n
249 help
250 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100251 device tree to the kernel. According to UHI register $a0 will be set
252 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100253
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100254endmenu
255
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100256config SUPPORTS_BIG_ENDIAN
257 bool
258
259config SUPPORTS_LITTLE_ENDIAN
260 bool
261
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100262config SUPPORTS_CPU_MIPS32_R1
263 bool
264
265config SUPPORTS_CPU_MIPS32_R2
266 bool
267
Paul Burtonc52ebea2016-05-16 10:52:12 +0100268config SUPPORTS_CPU_MIPS32_R6
269 bool
270
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100271config SUPPORTS_CPU_MIPS64_R1
272 bool
273
274config SUPPORTS_CPU_MIPS64_R2
275 bool
276
Paul Burtonc52ebea2016-05-16 10:52:12 +0100277config SUPPORTS_CPU_MIPS64_R6
278 bool
279
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100280config CPU_MIPS32
281 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100282 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100283
284config CPU_MIPS64
285 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100286 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100287
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100288config MIPS_TUNE_4KC
289 bool
290
291config MIPS_TUNE_14KC
292 bool
293
294config MIPS_TUNE_24KC
295 bool
296
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200297config MIPS_TUNE_34KC
298 bool
299
Marek Vasut0a0a9582016-05-06 20:10:33 +0200300config MIPS_TUNE_74KC
301 bool
302
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100303config 32BIT
304 bool
305
306config 64BIT
307 bool
308
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100309config SWAP_IO_SPACE
310 bool
311
Paul Burtondd7c7202015-01-29 01:28:02 +0000312config SYS_MIPS_CACHE_INIT_RAM_LOAD
313 bool
314
Daniel Schwierzeck924ad862016-06-04 16:13:21 +0200315config MIPS_INIT_STACK_IN_SRAM
316 bool
317 default n
318 help
319 Select this if the initial stack frame could be setup in SRAM.
320 Normally the initial stack frame is set up in DRAM which is often
321 only available after lowlevel_init. With this option the initial
322 stack frame and the early C environment is set up before
323 lowlevel_init. Thus lowlevel_init does not need to be implemented
324 in assembler.
325
Paul Burtonace3be42016-05-27 14:28:04 +0100326config SYS_DCACHE_SIZE
327 int
328 default 0
329 help
330 The total size of the L1 Dcache, if known at compile time.
331
Paul Burton37228622016-05-27 14:28:05 +0100332config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100333 int
Paul Burton37228622016-05-27 14:28:05 +0100334 default 0
335 help
336 The size of L1 Dcache lines, if known at compile time.
337
Paul Burtonace3be42016-05-27 14:28:04 +0100338config SYS_ICACHE_SIZE
339 int
340 default 0
341 help
342 The total size of the L1 ICache, if known at compile time.
343
Paul Burton37228622016-05-27 14:28:05 +0100344config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100345 int
346 default 0
347 help
Paul Burton37228622016-05-27 14:28:05 +0100348 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100349
350config SYS_CACHE_SIZE_AUTO
351 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100352 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100353 help
354 Select this (or let it be auto-selected by not defining any cache
355 sizes) in order to allow U-Boot to automatically detect the sizes
356 of caches at runtime. This has a small cost in code size & runtime
357 so if you know the cache configuration for your system at compile
358 time it would be beneficial to configure it.
359
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100360config MIPS_L1_CACHE_SHIFT_4
361 bool
362
363config MIPS_L1_CACHE_SHIFT_5
364 bool
365
366config MIPS_L1_CACHE_SHIFT_6
367 bool
368
369config MIPS_L1_CACHE_SHIFT_7
370 bool
371
372config MIPS_L1_CACHE_SHIFT
373 int
374 default "7" if MIPS_L1_CACHE_SHIFT_7
375 default "6" if MIPS_L1_CACHE_SHIFT_6
376 default "5" if MIPS_L1_CACHE_SHIFT_5
377 default "4" if MIPS_L1_CACHE_SHIFT_4
378 default "5"
379
Paul Burton4baa0ab2016-09-21 11:18:54 +0100380config MIPS_L2_CACHE
381 bool
382 help
383 Select this if your system includes an L2 cache and you want U-Boot
384 to initialise & maintain it.
385
Paul Burton05e34252016-01-29 13:54:52 +0000386config DYNAMIC_IO_PORT_BASE
387 bool
388
Paul Burtonb2b135d2016-09-21 11:18:53 +0100389config MIPS_CM
390 bool
391 help
392 Select this if your system contains a MIPS Coherence Manager and you
393 wish U-Boot to configure it or make use of it to retrieve system
394 information such as cache configuration.
395
396config MIPS_CM_BASE
397 hex
398 default 0x1fbf8000
399 help
400 The physical base address at which to map the MIPS Coherence Manager
401 Global Configuration Registers (GCRs). This should be set such that
402 the GCRs occupy a region of the physical address space which is
403 otherwise unused, or at minimum that software doesn't need to access.
404
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100405endif
406
Masahiro Yamadadd840582014-07-30 14:08:14 +0900407endmenu