blob: db47baba6d1ae8377cbe51bafa325d4dd4f950bc [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
Patrick Delaunay97f7e392020-07-24 11:13:31 +02004 select SPL_BOARD_INIT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01005 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Simon Glass9ca00682021-07-10 21:14:31 -06008 select SPL_DRIVERS_MISC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
Simon Glass83061db2021-07-10 21:14:30 -060010 select SPL_GPIO
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010011 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Simon Glass2a736062021-08-08 12:20:12 -060018 select SPL_SERIAL
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010019 select SPL_SYSCON
Simon Glass078111b2021-07-10 21:14:28 -060020 select SPL_WATCHDOG if WATCHDOG
Patrick Delaunay27a986d2019-04-18 17:32:47 +020021 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010023 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010024 imply SPL_LIBDISK_SUPPORT
Simon Glassea2ca7e2021-08-08 12:20:14 -060025 imply SPL_SPI_LOAD if SPL_SPI
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010026
27config SYS_SOC
28 default "stm32mp"
29
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020030config SYS_MALLOC_LEN
31 default 0x2000000
32
Patrick Delaunay579a3e72019-04-18 17:32:37 +020033config ENV_SIZE
Patrice Chotard1538e1a2019-05-07 18:40:47 +020034 default 0x2000
Patrick Delaunay579a3e72019-04-18 17:32:37 +020035
Patrick Delaunay647d3192022-05-20 18:24:43 +020036choice
37 prompt "Select STMicroelectronics STM32MPxxx Soc"
38 default STM32MP15x
39
Patrick Delaunay960debb2022-05-20 18:24:46 +020040config STM32MP13x
41 bool "Support STMicroelectronics STM32MP13x Soc"
42 select ARM_SMCCC
43 select CPU_V7A
44 select CPU_V7_HAS_NONSEC
45 select CPU_V7_HAS_VIRT
46 select OF_BOARD
47 select OF_BOARD_SETUP
48 select PINCTRL_STM32
49 select STM32_RCC
50 select STM32_RESET
51 select STM32_SERIAL
52 select SYS_ARCH_TIMER
53 imply CMD_NVEDIT_INFO
54 help
55 support of STMicroelectronics SOC STM32MP13x family
56 STMicroelectronics MPU with core ARMv7
57
Patrick Delaunay84625482020-01-13 15:17:42 +010058config STM32MP15x
59 bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunay17aeb582021-10-11 09:52:49 +020060 select ARCH_SUPPORT_PSCI
Patrick Delaunay5564b4c2021-10-13 15:11:18 +020061 select BINMAN
Lokesh Vutlaacf15002018-04-26 18:21:26 +053062 select CPU_V7A
Patrick Delaunay17aeb582021-10-11 09:52:49 +020063 select CPU_V7_HAS_NONSEC
Patrick Delaunay41c79772018-04-16 10:13:24 +020064 select CPU_V7_HAS_VIRT
Patrice Chotard22c08152022-01-20 08:19:15 +010065 select OF_BOARD if TFABOOT
Patrick Delaunaye81f8d12019-07-02 13:26:07 +020066 select OF_BOARD_SETUP
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010067 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020068 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010069 select STM32_RESET
Patrick Delaunay16a07222019-07-30 19:16:25 +020070 select STM32_SERIAL
Patrick Delaunay2ff08662022-05-20 18:24:40 +020071 select SUPPORT_SPL
Andre Przywara7842b6a2018-04-12 04:24:46 +030072 select SYS_ARCH_TIMER
Patrick Delaunayc16cba82020-07-02 17:43:45 +020073 imply CMD_NVEDIT_INFO
Patrick Delaunay84625482020-01-13 15:17:42 +010074 help
75 support of STMicroelectronics SOC STM32MP15x family
76 STM32MP157, STM32MP153 or STM32MP151
77 STMicroelectronics MPU with core ARMv7
78 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay647d3192022-05-20 18:24:43 +020079endchoice
80
Patrick Delaunay45ccdb62019-02-27 17:01:15 +010081config NR_DRAM_BANKS
82 default 1
83
Patrick Delaunay67f9f112020-09-04 12:55:19 +020084config DDR_CACHEABLE_SIZE
85 hex "Size of the DDR marked cacheable in pre-reloc stage"
Patrick Delaunay67f9f112020-09-04 12:55:19 +020086 default 0x40000000
87 help
88 Define the size of the DDR marked as cacheable in U-Boot
89 pre-reloc stage.
90 This option can be useful to avoid speculatif access
91 to secured area of DDR used by TF-A or OP-TEE before U-Boot
92 initialization.
93 The areas marked "no-map" in device tree should be located
94 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
95
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +010096config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
97 hex "Partition on MMC2 to use to load U-Boot from"
98 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
99 default 1
100 help
101 Partition on the second MMC to load U-Boot from when the MMC is being
102 used in raw mode
103
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200104config STM32_ETZPC
105 bool "STM32 Extended TrustZone Protection"
Patrick Delaunay960debb2022-05-20 18:24:46 +0200106 depends on STM32MP15x || STM32MP13x
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200107 default y
Simon Glassd3877fb2021-12-18 11:27:51 -0700108 imply BOOTP_SERVERIP
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200109 help
110 Say y to enable STM32 Extended TrustZone Protection
111
Alexandru Gagniucee870852021-07-29 11:47:17 -0500112config STM32_ECDSA_VERIFY
113 bool "STM32 ECDSA verification via the ROM API"
114 depends on SPL_ECDSA_VERIFY
115 default y
116 help
117 Say y to enable the uclass driver for ECDSA verification using the
118 ROM API provided on STM32MP.
119 The ROM API is only available during SPL for now.
120
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200121config CMD_STM32KEY
122 bool "command stm32key to fuse public key hash"
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200123 help
124 fuse public key hash in corresponding fuse used to authenticate
125 binary.
Patrick Delaunay3a994812021-06-28 14:55:57 +0200126 This command is used to evaluate the secure boot on stm32mp SOC,
127 it is deactivated by default in real products.
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200128
Patrick Delaunay960debb2022-05-20 18:24:46 +0200129source "arch/arm/mach-stm32mp/Kconfig.13x"
Patrick Delaunayd8b78fd2022-05-20 18:24:44 +0200130source "arch/arm/mach-stm32mp/Kconfig.15x"
Patrick Delaunay320d2662018-05-17 14:50:46 +0200131
Patrick Delaunay2dc22162021-02-25 13:37:00 +0100132source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100133endif