blob: 5d7eca649a87313e605fa3546f0cb4b93f35bba4 [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
Patrick Delaunay97f7e392020-07-24 11:13:31 +02004 select SPL_BOARD_INIT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01005 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Simon Glass9ca00682021-07-10 21:14:31 -06008 select SPL_DRIVERS_MISC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
Simon Glass83061db2021-07-10 21:14:30 -060010 select SPL_GPIO
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010011 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
19 select SPL_SYSCON
Simon Glass078111b2021-07-10 21:14:28 -060020 select SPL_WATCHDOG if WATCHDOG
Patrick Delaunay27a986d2019-04-18 17:32:47 +020021 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010023 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010024 imply SPL_LIBDISK_SUPPORT
Jagan Teki14dcdc62021-03-16 21:52:02 +053025 imply SPL_SPI_LOAD if SPL_SPI_SUPPORT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010026
27config SYS_SOC
28 default "stm32mp"
29
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020030config SYS_MALLOC_LEN
31 default 0x2000000
32
Patrick Delaunay579a3e72019-04-18 17:32:37 +020033config ENV_SIZE
Patrice Chotard1538e1a2019-05-07 18:40:47 +020034 default 0x2000
Patrick Delaunay579a3e72019-04-18 17:32:37 +020035
Patrick Delaunay84625482020-01-13 15:17:42 +010036config STM32MP15x
37 bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunay654706b2020-04-01 09:07:33 +020038 select ARCH_SUPPORT_PSCI if !TFABOOT
39 select ARM_SMCCC if TFABOOT
Lokesh Vutlaacf15002018-04-26 18:21:26 +053040 select CPU_V7A
Patrick Delaunay654706b2020-04-01 09:07:33 +020041 select CPU_V7_HAS_NONSEC if !TFABOOT
Patrick Delaunay41c79772018-04-16 10:13:24 +020042 select CPU_V7_HAS_VIRT
Patrick Delaunaye81f8d12019-07-02 13:26:07 +020043 select OF_BOARD_SETUP
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010044 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020045 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010046 select STM32_RESET
Patrick Delaunay16a07222019-07-30 19:16:25 +020047 select STM32_SERIAL
Andre Przywara7842b6a2018-04-12 04:24:46 +030048 select SYS_ARCH_TIMER
Patrick Delaunayc16cba82020-07-02 17:43:45 +020049 imply CMD_NVEDIT_INFO
Patrick Delaunay654706b2020-04-01 09:07:33 +020050 imply SYSRESET_PSCI if TFABOOT
51 imply SYSRESET_SYSCON if !TFABOOT
Patrick Delaunay84625482020-01-13 15:17:42 +010052 help
53 support of STMicroelectronics SOC STM32MP15x family
54 STM32MP157, STM32MP153 or STM32MP151
55 STMicroelectronics MPU with core ARMv7
56 dual core A7 for STM32MP157/3, monocore for STM32MP151
57 target all the STMicroelectronics board with SOC STM32MP1 family
58
Patrick Delaunay6de57b42021-07-26 11:21:34 +020059config STM32MP15x_STM32IMAGE
60 bool "Support STM32 image for generated U-Boot image"
61 depends on STM32MP15x && TFABOOT
62 help
63 Support of STM32 image generation for SOC STM32MP15x
64 for TF-A boot when FIP container is not used
65
Patrick Delaunay84625482020-01-13 15:17:42 +010066choice
67 prompt "STM32MP15x board select"
68 optional
69
70config TARGET_ST_STM32MP15x
71 bool "STMicroelectronics STM32MP15x boards"
72 select STM32MP15x
Patrick Delaunay34199822019-04-18 17:32:45 +020073 imply BOOTCOUNT_LIMIT
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010074 imply BOOTSTAGE
Patrick Delaunay34199822019-04-18 17:32:45 +020075 imply CMD_BOOTCOUNT
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010076 imply CMD_BOOTSTAGE
Patrick Delaunayeee15802019-12-03 09:38:58 +010077 imply CMD_CLS if CMD_BMP
Patrick Delaunaya67d9582019-07-30 19:16:26 +020078 imply DISABLE_CONSOLE
Patrick Delaunay67551982019-07-30 19:16:23 +020079 imply PRE_CONSOLE_BUFFER
Patrick Delaunayc50c9282019-07-30 19:16:22 +020080 imply SILENT_CONSOLE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010081 help
Patrick Delaunay84625482020-01-13 15:17:42 +010082 target the STMicroelectronics board with SOC STM32MP15x
83 managed by board/st/stm32mp1:
84 Evalulation board (EV1) or Discovery board (DK1 and DK2).
85 The difference between board are managed with devicetree
86
Jagan Tekifd4dc092021-03-16 21:52:06 +053087config TARGET_MICROGEA_STM32MP1
88 bool "Engicam MicroGEA STM32MP1 SOM"
89 select STM32MP15x
90 imply BOOTCOUNT_LIMIT
91 imply BOOTSTAGE
92 imply CMD_BOOTCOUNT
93 imply CMD_BOOTSTAGE
94 imply CMD_CLS if CMD_BMP
95 imply DISABLE_CONSOLE
96 imply PRE_CONSOLE_BUFFER
97 imply SILENT_CONSOLE
98 help
99 MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
100
101 MicroGEA STM32MP1 MicroDev 2.0:
102 * MicroDev 2.0 is a general purpose miniature carrier board with CAN,
103 LTE and LVDS panel interfaces.
104 * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
105 for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
106
Jagan Teki0441b482021-03-16 21:52:07 +0530107 MicroGEA STM32MP1 MicroDev 2.0 7" OF:
108 * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
109 panel and toucscreen.
110 * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
111 pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
112 Open Frame Solution board.
113
Jagan Teki30edf402021-03-16 21:52:03 +0530114config TARGET_ICORE_STM32MP1
115 bool "Engicam i.Core STM32MP1 SOM"
116 select STM32MP15x
117 imply BOOTCOUNT_LIMIT
118 imply BOOTSTAGE
119 imply CMD_BOOTCOUNT
120 imply CMD_BOOTSTAGE
121 imply CMD_CLS if CMD_BMP
122 imply DISABLE_CONSOLE
123 imply PRE_CONSOLE_BUFFER
124 imply SILENT_CONSOLE
125 help
126 i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
127
128 i.Core STM32MP1 EDIMM2.2:
129 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
130 * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
131 creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
132
Jagan Tekib594ec82021-03-16 21:52:04 +0530133 i.Core STM32MP1 C.TOUCH 2.0
134 * C.TOUCH 2.0 is a general purpose Carrier board.
135 * i.Core STM32MP1 needs to mount on top of this Carrier board
136 for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
137
Marek Vasut19953732020-01-24 18:39:16 +0100138config TARGET_DH_STM32MP1_PDK2
139 bool "DH STM32MP1 PDK2"
140 select STM32MP15x
141 imply BOOTCOUNT_LIMIT
142 imply CMD_BOOTCOUNT
143 help
144 Target the DH PDK2 development kit with STM32MP15x SoM.
145
Patrick Delaunay84625482020-01-13 15:17:42 +0100146endchoice
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100147
148config SYS_TEXT_BASE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100149 default 0xC0100000
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100150
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100151config NR_DRAM_BANKS
152 default 1
153
Patrick Delaunay67f9f112020-09-04 12:55:19 +0200154config DDR_CACHEABLE_SIZE
155 hex "Size of the DDR marked cacheable in pre-reloc stage"
156 default 0x10000000 if TFABOOT
157 default 0x40000000
158 help
159 Define the size of the DDR marked as cacheable in U-Boot
160 pre-reloc stage.
161 This option can be useful to avoid speculatif access
162 to secured area of DDR used by TF-A or OP-TEE before U-Boot
163 initialization.
164 The areas marked "no-map" in device tree should be located
165 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
166
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +0100167config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
168 hex "Partition on MMC2 to use to load U-Boot from"
169 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
170 default 1
171 help
172 Partition on the second MMC to load U-Boot from when the MMC is being
173 used in raw mode
174
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200175config STM32_ETZPC
176 bool "STM32 Extended TrustZone Protection"
Patrick Delaunay7a02e4d2020-03-10 16:05:43 +0100177 depends on STM32MP15x
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200178 default y
179 help
180 Say y to enable STM32 Extended TrustZone Protection
181
Alexandru Gagniucee870852021-07-29 11:47:17 -0500182config STM32_ECDSA_VERIFY
183 bool "STM32 ECDSA verification via the ROM API"
184 depends on SPL_ECDSA_VERIFY
185 default y
186 help
187 Say y to enable the uclass driver for ECDSA verification using the
188 ROM API provided on STM32MP.
189 The ROM API is only available during SPL for now.
190
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200191config CMD_STM32KEY
192 bool "command stm32key to fuse public key hash"
Patrick Delaunay3a994812021-06-28 14:55:57 +0200193 default n
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200194 help
195 fuse public key hash in corresponding fuse used to authenticate
196 binary.
Patrick Delaunay3a994812021-06-28 14:55:57 +0200197 This command is used to evaluate the secure boot on stm32mp SOC,
198 it is deactivated by default in real products.
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200199
Patrick Delaunay67551982019-07-30 19:16:23 +0200200config PRE_CON_BUF_ADDR
201 default 0xC02FF000
202
203config PRE_CON_BUF_SZ
204 default 4096
205
Patrick Delaunay27a986d2019-04-18 17:32:47 +0200206config BOOTSTAGE_STASH_ADDR
207 default 0xC3000000
208
Patrick Delaunay34199822019-04-18 17:32:45 +0200209if BOOTCOUNT_LIMIT
210config SYS_BOOTCOUNT_SINGLEWORD
211 default y
212
213# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
214config SYS_BOOTCOUNT_ADDR
215 default 0x5C00A154
216endif
217
Patrick Delaunay320d2662018-05-17 14:50:46 +0200218if DEBUG_UART
219
220config DEBUG_UART_BOARD_INIT
221 default y
222
223# debug on UART4 by default
224config DEBUG_UART_BASE
225 default 0x40010000
226
227# clock source is HSI on reset
228config DEBUG_UART_CLOCK
229 default 64000000
230endif
231
Patrick Delaunay2dc22162021-02-25 13:37:00 +0100232source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Marek Vasut19953732020-01-24 18:39:16 +0100233source "board/dhelectronics/dh_stm32mp1/Kconfig"
Jagan Teki30edf402021-03-16 21:52:03 +0530234source "board/engicam/stm32mp1/Kconfig"
235source "board/st/stm32mp1/Kconfig"
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100236
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100237endif