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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f152febb2a97696f7c7e6df46bf585cfc962a835 / . / arch / riscv / Kconfig
blob: 9da609b33b148dc2ac1e172d2a7c915d87c2777e [file] [log] [blame]
Bin Meng117a4332018-09-26 06:55:06 -0700[diff] [blame]1menu "RISC-V architecture"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]2 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]11config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]13
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]14config TARGET_QEMU_VIRT
15 bool "Support QEMU Virt Board"
16
Anup Patel3fda0262019-02-25 08:15:19 +0000[diff] [blame]17config TARGET_SIFIVE_FU540
18 bool "Support SiFive FU540 Board"
19
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]20endchoice
21
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]22# board-specific options below
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]23source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]24source "board/emulation/qemu-riscv/Kconfig"
Anup Patel3fda0262019-02-25 08:15:19 +0000[diff] [blame]25source "board/sifive/fu540/Kconfig"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]26
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]27# platform-specific options below
28source "arch/riscv/cpu/ax25/Kconfig"
Anup Patelfdff1f92019-02-25 08:14:10 +0000[diff] [blame]29source "arch/riscv/cpu/generic/Kconfig"
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]30
31# architecture-specific options below
32
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]33choice
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]34 prompt "Base ISA"
35 default ARCH_RV32I
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]36
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]37config ARCH_RV32I
38 bool "RV32I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]39 select 32BIT
40 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]41 Choose this option to target the RV32I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]42
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]43config ARCH_RV64I
44 bool "RV64I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]45 select 64BIT
Lukas Auer71158562018-11-22 11:26:13 +0100[diff] [blame]46 select PHYS_64BIT
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]47 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]48 Choose this option to target the RV64I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]49
50endchoice
51
Lukas Auer8176ea42018-12-12 06:12:23 -0800[diff] [blame]52choice
53 prompt "Code Model"
54 default CMODEL_MEDLOW
55
56config CMODEL_MEDLOW
57 bool "medium low code model"
58 help
59 U-Boot and its statically defined symbols must lie within a single 2 GiB
60 address range and must lie between absolute addresses -2 GiB and +2 GiB.
61
62config CMODEL_MEDANY
63 bool "medium any code model"
64 help
65 U-Boot and its statically defined symbols must be within any single 2 GiB
66 address range.
67
68endchoice
69
Anup Patel3cfc8252018-12-12 06:12:29 -0800[diff] [blame]70choice
71 prompt "Run Mode"
72 default RISCV_MMODE
73
74config RISCV_MMODE
75 bool "Machine"
76 help
77 Choose this option to build U-Boot for RISC-V M-Mode.
78
79config RISCV_SMODE
80 bool "Supervisor"
81 help
82 Choose this option to build U-Boot for RISC-V S-Mode.
83
84endchoice
85
Lukas Auerd57ffa62018-11-22 11:26:14 +0100[diff] [blame]86config RISCV_ISA_C
87 bool "Emit compressed instructions"
88 default y
89 help
90 Adds "C" to the ISA subsets that the toolchain is allowed to emit
91 when building U-Boot, which results in compressed instructions in the
92 U-Boot binary.
93
94config RISCV_ISA_A
95 def_bool y
96
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]97config 32BIT
98 bool
99
100config 64BIT
101 bool
102
Bin Meng644a3cd2018-12-12 06:12:30 -0800[diff] [blame]103config SIFIVE_CLINT
104 bool
105 depends on RISCV_MMODE
106 select REGMAP
107 select SYSCON
108 help
109 The SiFive CLINT block holds memory-mapped control and status registers
110 associated with software and timer interrupts.
111
Anup Patel511107d2018-12-12 06:12:31 -0800[diff] [blame]112config RISCV_RDTIME
113 bool
114 default y if RISCV_SMODE
115 help
116 The provides the riscv_get_time() API that is implemented using the
117 standard rdtime instruction. This is the case for S-mode U-Boot, and
118 is useful for processors that support rdtime in M-mode too.
119
Bin Meng92b64fe2018-12-12 06:12:33 -0800[diff] [blame]120config SYS_MALLOC_F_LEN
121 default 0x1000
122
Lukas Auerfa33f082019-03-17 19:28:32 +0100[diff] [blame]123config SMP
124 bool "Symmetric Multi-Processing"
125 help
126 This enables support for systems with more than one CPU. If
127 you say N here, U-Boot will run on single and multiprocessor
128 machines, but will use only one CPU of a multiprocessor
129 machine. If you say Y here, U-Boot will run on many, but not
130 all, single processor machines.
131
132config NR_CPUS
133 int "Maximum number of CPUs (2-32)"
134 range 2 32
135 depends on SMP
136 default 8
137 help
138 On multiprocessor machines, U-Boot sets up a stack for each CPU.
139 Stack memory is pre-allocated. U-Boot must therefore know the
140 maximum number of CPUs that may be present.
141
Lukas Auerf152feb2019-03-17 19:28:34 +0100[diff] [blame^]142config SBI_IPI
143 bool
144 default y if RISCV_SMODE
145 depends on SMP
146
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]147endmenu