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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010017 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010019 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +010021 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Masahiro Yamadadd840582014-07-30 14:08:14 +090023
24config TARGET_MALTA
25 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +010026 select DM
27 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +000028 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +010029 select MIPS_CM
30 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +010031 select OF_CONTROL
32 select OF_ISA_BUS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010033 select SUPPORTS_BIG_ENDIAN
34 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010035 select SUPPORTS_CPU_MIPS32_R1
36 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010037 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010038 select SUPPORTS_CPU_MIPS64_R1
39 select SUPPORTS_CPU_MIPS64_R2
40 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010041 select SWAP_IO_SPACE
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +010042 select MIPS_L1_CACHE_SHIFT_6
Masahiro Yamadadd840582014-07-30 14:08:14 +090043
44config TARGET_VCT
45 bool "Support vct"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010046 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010047 select SUPPORTS_CPU_MIPS32_R1
48 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000049 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090050
51config TARGET_DBAU1X00
52 bool "Support dbau1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010053 select SUPPORTS_BIG_ENDIAN
54 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010055 select SUPPORTS_CPU_MIPS32_R1
56 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000057 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010058 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090059
60config TARGET_PB1X00
61 bool "Support pb1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010062 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010063 select SUPPORTS_CPU_MIPS32_R1
64 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000065 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010066 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090067
Wills Wang1d3d0f12016-03-16 16:59:52 +080068config ARCH_ATH79
69 bool "Support QCA/Atheros ath79"
70 select OF_CONTROL
71 select DM
72
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053073config MACH_PIC32
74 bool "Support Microchip PIC32"
75 select OF_CONTROL
76 select DM
77
Paul Burtonad8783c2016-09-08 07:47:39 +010078config TARGET_BOSTON
79 bool "Support Boston"
80 select DM
81 select DM_SERIAL
82 select OF_CONTROL
83 select MIPS_CM
84 select MIPS_L1_CACHE_SHIFT_6
85 select MIPS_L2_CACHE
86 select SUPPORTS_BIG_ENDIAN
87 select SUPPORTS_LITTLE_ENDIAN
88 select SUPPORTS_CPU_MIPS32_R1
89 select SUPPORTS_CPU_MIPS32_R2
90 select SUPPORTS_CPU_MIPS32_R6
91 select SUPPORTS_CPU_MIPS64_R1
92 select SUPPORTS_CPU_MIPS64_R2
93 select SUPPORTS_CPU_MIPS64_R6
94
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010095config TARGET_XILFPGA
96 bool "Support Imagination Xilfpga"
97 select OF_CONTROL
98 select DM
99 select DM_SERIAL
100 select DM_GPIO
101 select DM_ETH
102 select SUPPORTS_LITTLE_ENDIAN
103 select SUPPORTS_CPU_MIPS32_R1
104 select SUPPORTS_CPU_MIPS32_R2
105 select MIPS_L1_CACHE_SHIFT_4
106 help
107 This supports IMGTEC MIPSfpga platform
108
Masahiro Yamadadd840582014-07-30 14:08:14 +0900109endchoice
110
111source "board/dbau1x00/Kconfig"
Paul Burtonad8783c2016-09-08 07:47:39 +0100112source "board/imgtec/boston/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900113source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100114source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900115source "board/micronas/vct/Kconfig"
116source "board/pb1x00/Kconfig"
117source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800118source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530119source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900120
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100121if MIPS
122
123choice
124 prompt "Endianness selection"
125 help
126 Some MIPS boards can be configured for either little or big endian
127 byte order. These modes require different U-Boot images. In general there
128 is one preferred byteorder for a particular system but some systems are
129 just as commonly used in the one or the other endianness.
130
131config SYS_BIG_ENDIAN
132 bool "Big endian"
133 depends on SUPPORTS_BIG_ENDIAN
134
135config SYS_LITTLE_ENDIAN
136 bool "Little endian"
137 depends on SUPPORTS_LITTLE_ENDIAN
138
139endchoice
140
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100141choice
142 prompt "CPU selection"
143 default CPU_MIPS32_R2
144
145config CPU_MIPS32_R1
146 bool "MIPS32 Release 1"
147 depends on SUPPORTS_CPU_MIPS32_R1
148 select 32BIT
149 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100150 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100151 MIPS32 architecture.
152
153config CPU_MIPS32_R2
154 bool "MIPS32 Release 2"
155 depends on SUPPORTS_CPU_MIPS32_R2
156 select 32BIT
157 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100158 Choose this option to build an U-Boot for release 2 through 5 of the
159 MIPS32 architecture.
160
161config CPU_MIPS32_R6
162 bool "MIPS32 Release 6"
163 depends on SUPPORTS_CPU_MIPS32_R6
164 select 32BIT
165 help
166 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100167 MIPS32 architecture.
168
169config CPU_MIPS64_R1
170 bool "MIPS64 Release 1"
171 depends on SUPPORTS_CPU_MIPS64_R1
172 select 64BIT
173 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100174 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100175 MIPS64 architecture.
176
177config CPU_MIPS64_R2
178 bool "MIPS64 Release 2"
179 depends on SUPPORTS_CPU_MIPS64_R2
180 select 64BIT
181 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100182 Choose this option to build a kernel for release 2 through 5 of the
183 MIPS64 architecture.
184
185config CPU_MIPS64_R6
186 bool "MIPS64 Release 6"
187 depends on SUPPORTS_CPU_MIPS64_R6
188 select 64BIT
189 help
190 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100191 MIPS64 architecture.
192
193endchoice
194
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100195menu "OS boot interface"
196
197config MIPS_BOOT_CMDLINE_LEGACY
198 bool "Hand over legacy command line to Linux kernel"
199 default y
200 help
201 Enable this option if you want U-Boot to hand over the Yamon-style
202 command line to the kernel. All bootargs will be prepared as argc/argv
203 compatible list. The argument count (argc) is stored in register $a0.
204 The address of the argument list (argv) is stored in register $a1.
205
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100206config MIPS_BOOT_ENV_LEGACY
207 bool "Hand over legacy environment to Linux kernel"
208 default y
209 help
210 Enable this option if you want U-Boot to hand over the Yamon-style
211 environment to the kernel. Information like memory size, initrd
212 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400213 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100214
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100215config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100216 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100217 default n
218 help
219 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100220 device tree to the kernel. According to UHI register $a0 will be set
221 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100222
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100223endmenu
224
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100225config SUPPORTS_BIG_ENDIAN
226 bool
227
228config SUPPORTS_LITTLE_ENDIAN
229 bool
230
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100231config SUPPORTS_CPU_MIPS32_R1
232 bool
233
234config SUPPORTS_CPU_MIPS32_R2
235 bool
236
Paul Burtonc52ebea2016-05-16 10:52:12 +0100237config SUPPORTS_CPU_MIPS32_R6
238 bool
239
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100240config SUPPORTS_CPU_MIPS64_R1
241 bool
242
243config SUPPORTS_CPU_MIPS64_R2
244 bool
245
Paul Burtonc52ebea2016-05-16 10:52:12 +0100246config SUPPORTS_CPU_MIPS64_R6
247 bool
248
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100249config CPU_MIPS32
250 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100251 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100252
253config CPU_MIPS64
254 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100255 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100256
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100257config MIPS_TUNE_4KC
258 bool
259
260config MIPS_TUNE_14KC
261 bool
262
263config MIPS_TUNE_24KC
264 bool
265
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200266config MIPS_TUNE_34KC
267 bool
268
Marek Vasut0a0a9582016-05-06 20:10:33 +0200269config MIPS_TUNE_74KC
270 bool
271
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100272config 32BIT
273 bool
274
275config 64BIT
276 bool
277
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100278config SWAP_IO_SPACE
279 bool
280
Paul Burtondd7c7202015-01-29 01:28:02 +0000281config SYS_MIPS_CACHE_INIT_RAM_LOAD
282 bool
283
Paul Burtonace3be42016-05-27 14:28:04 +0100284config SYS_DCACHE_SIZE
285 int
286 default 0
287 help
288 The total size of the L1 Dcache, if known at compile time.
289
Paul Burton37228622016-05-27 14:28:05 +0100290config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100291 int
Paul Burton37228622016-05-27 14:28:05 +0100292 default 0
293 help
294 The size of L1 Dcache lines, if known at compile time.
295
Paul Burtonace3be42016-05-27 14:28:04 +0100296config SYS_ICACHE_SIZE
297 int
298 default 0
299 help
300 The total size of the L1 ICache, if known at compile time.
301
Paul Burton37228622016-05-27 14:28:05 +0100302config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100303 int
304 default 0
305 help
Paul Burton37228622016-05-27 14:28:05 +0100306 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100307
308config SYS_CACHE_SIZE_AUTO
309 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100310 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100311 help
312 Select this (or let it be auto-selected by not defining any cache
313 sizes) in order to allow U-Boot to automatically detect the sizes
314 of caches at runtime. This has a small cost in code size & runtime
315 so if you know the cache configuration for your system at compile
316 time it would be beneficial to configure it.
317
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100318config MIPS_L1_CACHE_SHIFT_4
319 bool
320
321config MIPS_L1_CACHE_SHIFT_5
322 bool
323
324config MIPS_L1_CACHE_SHIFT_6
325 bool
326
327config MIPS_L1_CACHE_SHIFT_7
328 bool
329
330config MIPS_L1_CACHE_SHIFT
331 int
332 default "7" if MIPS_L1_CACHE_SHIFT_7
333 default "6" if MIPS_L1_CACHE_SHIFT_6
334 default "5" if MIPS_L1_CACHE_SHIFT_5
335 default "4" if MIPS_L1_CACHE_SHIFT_4
336 default "5"
337
Paul Burton4baa0ab2016-09-21 11:18:54 +0100338config MIPS_L2_CACHE
339 bool
340 help
341 Select this if your system includes an L2 cache and you want U-Boot
342 to initialise & maintain it.
343
Paul Burton05e34252016-01-29 13:54:52 +0000344config DYNAMIC_IO_PORT_BASE
345 bool
346
Paul Burtonb2b135d2016-09-21 11:18:53 +0100347config MIPS_CM
348 bool
349 help
350 Select this if your system contains a MIPS Coherence Manager and you
351 wish U-Boot to configure it or make use of it to retrieve system
352 information such as cache configuration.
353
354config MIPS_CM_BASE
355 hex
356 default 0x1fbf8000
357 help
358 The physical base address at which to map the MIPS Coherence Manager
359 Global Configuration Registers (GCRs). This should be set such that
360 the GCRs occupy a region of the physical address space which is
361 otherwise unused, or at minimum that software doesn't need to access.
362
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100363endif
364
Masahiro Yamadadd840582014-07-30 14:08:14 +0900365endmenu