blob: 94ba9626800c052c4dee7408054c3bb154742240 [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Simon Glass53b5bf32016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glass77d2f7f2016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glass1646eba2016-09-12 23:18:42 -06009config SPL_LIBDISK_SUPPORT
10 default y
11
Hans de Goede44d8ae52015-04-06 20:33:34 +020012# Note only one of these may be selected at a time! But hidden choices are
13# not supported by Kconfig
14config SUNXI_GEN_SUN4I
15 bool
16 ---help---
17 Select this for sunxi SoCs which have resets and clocks set up
18 as the original A10 (mach-sun4i).
19
20config SUNXI_GEN_SUN6I
21 bool
22 ---help---
23 Select this for sunxi SoCs which have sun6i like periphery, like
24 separate ahb reset control registers, custom pmic bus, new style
25 watchdog, etc.
26
27
Ian Campbell2c7e3b92014-10-24 21:20:44 +010028choice
29 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020030 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010031
Ian Campbellc3be2792014-10-24 21:20:45 +010032config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033 bool "sun4i (Allwinner A10)"
34 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020035 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 select SUPPORT_SPL
37
Ian Campbellc3be2792014-10-24 21:20:45 +010038config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010039 bool "sun5i (Allwinner A13)"
40 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020041 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010042 select SUPPORT_SPL
43
Ian Campbellc3be2792014-10-24 21:20:45 +010044config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010045 bool "sun6i (Allwinner A31)"
46 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090049 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020050 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020051 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080052 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010053
Ian Campbellc3be2792014-10-24 21:20:45 +010054config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010055 bool "sun7i (Allwinner A20)"
56 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010057 select CPU_V7_HAS_NONSEC
58 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090059 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020060 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010061 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020062 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010063
Hans de Goede5e6bacd2015-04-06 20:55:39 +020064config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010065 bool "sun8i (Allwinner A23)"
66 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080067 select CPU_V7_HAS_NONSEC
68 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090069 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020070 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010071 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080072 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010073
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053074config MACH_SUN8I_A33
75 bool "sun8i (Allwinner A33)"
76 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080077 select CPU_V7_HAS_NONSEC
78 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090079 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053080 select SUNXI_GEN_SUN6I
81 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080082 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053083
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +080084config MACH_SUN8I_A83T
85 bool "sun8i (Allwinner A83T)"
86 select CPU_V7
87 select SUNXI_GEN_SUN6I
88 select SUPPORT_SPL
89
Jens Kuske1c27b7d2015-11-17 15:12:58 +010090config MACH_SUN8I_H3
91 bool "sun8i (Allwinner H3)"
92 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080093 select CPU_V7_HAS_NONSEC
94 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090095 select ARCH_SUPPORT_PSCI
Jens Kuske1c27b7d2015-11-17 15:12:58 +010096 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +010097 select SUPPORT_SPL
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080098 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +010099
Hans de Goede1871a8c2015-01-13 19:25:06 +0100100config MACH_SUN9I
101 bool "sun9i (Allwinner A80)"
102 select CPU_V7
103 select SUNXI_GEN_SUN6I
104
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800105config MACH_SUN50I
106 bool "sun50i (Allwinner A64)"
107 select ARM64
108 select SUNXI_GEN_SUN6I
109
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100110endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800111
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200112# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
113config MACH_SUN8I
114 bool
vishnupatekar762e24a2015-11-29 01:07:19 +0800115 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200116
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800117config DRAM_TYPE
118 int "sunxi dram type"
119 depends on MACH_SUN8I_A83T
120 default 3
121 ---help---
122 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200123
Hans de Goede37781a12014-11-15 19:46:39 +0100124config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100125 int "sunxi dram clock speed"
126 default 312 if MACH_SUN6I || MACH_SUN8I
127 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100128 ---help---
129 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +0100130 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +0100131
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200132if MACH_SUN5I || MACH_SUN7I
133config DRAM_MBUS_CLK
134 int "sunxi mbus clock speed"
135 default 300
136 ---help---
137 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
138
139endif
140
Hans de Goede37781a12014-11-15 19:46:39 +0100141config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100142 int "sunxi dram zq value"
143 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
144 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100145 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100146 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100147
Hans de Goede8975cdf2015-05-13 15:00:46 +0200148config DRAM_ODT_EN
149 bool "sunxi dram odt enable"
150 default n if !MACH_SUN8I_A23
151 default y if MACH_SUN8I_A23
152 ---help---
153 Select this to enable dram odt (on die termination).
154
Hans de Goede8ffc4872015-01-17 14:24:55 +0100155if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
156config DRAM_EMR1
157 int "sunxi dram emr1 value"
158 default 0 if MACH_SUN4I
159 default 4 if MACH_SUN5I || MACH_SUN7I
160 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100161 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200162
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200163config DRAM_TPR3
164 hex "sunxi dram tpr3 value"
165 default 0
166 ---help---
167 Set the dram controller tpr3 parameter. This parameter configures
168 the delay on the command lane and also phase shifts, which are
169 applied for sampling incoming read data. The default value 0
170 means that no phase/delay adjustments are necessary. Properly
171 configuring this parameter increases reliability at high DRAM
172 clock speeds.
173
174config DRAM_DQS_GATING_DELAY
175 hex "sunxi dram dqs_gating_delay value"
176 default 0
177 ---help---
178 Set the dram controller dqs_gating_delay parmeter. Each byte
179 encodes the DQS gating delay for each byte lane. The delay
180 granularity is 1/4 cycle. For example, the value 0x05060606
181 means that the delay is 5 quarter-cycles for one lane (1.25
182 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
183 The default value 0 means autodetection. The results of hardware
184 autodetection are not very reliable and depend on the chip
185 temperature (sometimes producing different results on cold start
186 and warm reboot). But the accuracy of hardware autodetection
187 is usually good enough, unless running at really high DRAM
188 clocks speeds (up to 600MHz). If unsure, keep as 0.
189
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200190choice
191 prompt "sunxi dram timings"
192 default DRAM_TIMINGS_VENDOR_MAGIC
193 ---help---
194 Select the timings of the DDR3 chips.
195
196config DRAM_TIMINGS_VENDOR_MAGIC
197 bool "Magic vendor timings from Android"
198 ---help---
199 The same DRAM timings as in the Allwinner boot0 bootloader.
200
201config DRAM_TIMINGS_DDR3_1066F_1333H
202 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
203 ---help---
204 Use the timings of the standard JEDEC DDR3-1066F speed bin for
205 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
206 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
207 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
208 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
209 that down binning to DDR3-1066F is supported (because DDR3-1066F
210 uses a bit faster timings than DDR3-1333H).
211
212config DRAM_TIMINGS_DDR3_800E_1066G_1333J
213 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
214 ---help---
215 Use the timings of the slowest possible JEDEC speed bin for the
216 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
217 DDR3-800E, DDR3-1066G or DDR3-1333J.
218
219endchoice
220
Hans de Goede37781a12014-11-15 19:46:39 +0100221endif
222
Hans de Goede8975cdf2015-05-13 15:00:46 +0200223if MACH_SUN8I_A23
224config DRAM_ODT_CORRECTION
225 int "sunxi dram odt correction value"
226 default 0
227 ---help---
228 Set the dram odt correction value (range -255 - 255). In allwinner
229 fex files, this option is found in bits 8-15 of the u32 odt_en variable
230 in the [dram] section. When bit 31 of the odt_en variable is set
231 then the correction is negative. Usually the value for this is 0.
232endif
233
Iain Patone71b4222015-03-28 10:26:38 +0000234config SYS_CLK_FREQ
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200235 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000236 default 912000000 if MACH_SUN7I
237 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
238
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800239config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100240 default "sun4i" if MACH_SUN4I
241 default "sun5i" if MACH_SUN5I
242 default "sun6i" if MACH_SUN6I
243 default "sun7i" if MACH_SUN7I
244 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100245 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200246 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200247
Masahiro Yamadadd840582014-07-30 14:08:14 +0900248config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900249 default "sunxi"
250
251config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900252 default "sunxi"
253
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200254config UART0_PORT_F
255 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200256 default n
257 ---help---
258 Repurpose the SD card slot for getting access to the UART0 serial
259 console. Primarily useful only for low level u-boot debugging on
260 tablets, where normal UART0 is difficult to access and requires
261 device disassembly and/or soldering. As the SD card can't be used
262 at the same time, the system can be only booted in the FEL mode.
263 Only enable this if you really know what you are doing.
264
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200265config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900266 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200267 default n
268 ---help---
269 Set this to enable various workarounds for old kernels, this results in
270 sub-optimal settings for newer kernels, only enable if needed.
271
Maxime Ripard44c79872015-10-15 22:04:07 +0200272config MMC
273 depends on !UART0_PORT_F
274 default y if ARCH_SUNXI
275
Hans de Goedecd821132014-10-02 20:29:26 +0200276config MMC0_CD_PIN
277 string "Card detect pin for mmc0"
Chen-Yu Tsaiacdab172016-05-02 10:28:08 +0800278 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200279 default ""
280 ---help---
281 Set the card detect pin for mmc0, leave empty to not use cd. This
282 takes a string in the format understood by sunxi_name_to_gpio, e.g.
283 PH1 for pin 1 of port H.
284
285config MMC1_CD_PIN
286 string "Card detect pin for mmc1"
287 default ""
288 ---help---
289 See MMC0_CD_PIN help text.
290
291config MMC2_CD_PIN
292 string "Card detect pin for mmc2"
293 default ""
294 ---help---
295 See MMC0_CD_PIN help text.
296
297config MMC3_CD_PIN
298 string "Card detect pin for mmc3"
299 default ""
300 ---help---
301 See MMC0_CD_PIN help text.
302
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100303config MMC1_PINS
304 string "Pins for mmc1"
305 default ""
306 ---help---
307 Set the pins used for mmc1, when applicable. This takes a string in the
308 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
309
310config MMC2_PINS
311 string "Pins for mmc2"
312 default ""
313 ---help---
314 See MMC1_PINS help text.
315
316config MMC3_PINS
317 string "Pins for mmc3"
318 default ""
319 ---help---
320 See MMC1_PINS help text.
321
Hans de Goede2ccfac02014-10-02 20:43:50 +0200322config MMC_SUNXI_SLOT_EXTRA
323 int "mmc extra slot number"
324 default -1
325 ---help---
326 sunxi builds always enable mmc0, some boards also have a second sdcard
327 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
328 support for this.
329
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200330config INITIAL_USB_SCAN_DELAY
331 int "delay initial usb scan by x ms to allow builtin devices to init"
332 default 0
333 ---help---
334 Some boards have on board usb devices which need longer than the
335 USB spec's 1 second to connect from board powerup. Set this config
336 option to a non 0 value to add an extra delay before the first usb
337 bus scan.
338
Hans de Goede4458b7a2015-01-07 15:26:06 +0100339config USB0_VBUS_PIN
340 string "Vbus enable pin for usb0 (otg)"
341 default ""
342 ---help---
343 Set the Vbus enable pin for usb0 (otg). This takes a string in the
344 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
345
Hans de Goede52defe82015-02-16 22:13:43 +0100346config USB0_VBUS_DET
347 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100348 default ""
349 ---help---
350 Set the Vbus detect pin for usb0 (otg). This takes a string in the
351 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
352
Hans de Goede48c06c92015-06-14 17:29:53 +0200353config USB0_ID_DET
354 string "ID detect pin for usb0 (otg)"
355 default ""
356 ---help---
357 Set the ID detect pin for usb0 (otg). This takes a string in the
358 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
359
Hans de Goede115200c2014-11-07 16:09:00 +0100360config USB1_VBUS_PIN
361 string "Vbus enable pin for usb1 (ehci0)"
362 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100363 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100364 ---help---
365 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
366 a string in the format understood by sunxi_name_to_gpio, e.g.
367 PH1 for pin 1 of port H.
368
369config USB2_VBUS_PIN
370 string "Vbus enable pin for usb2 (ehci1)"
371 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100372 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100373 ---help---
374 See USB1_VBUS_PIN help text.
375
Hans de Goede60fa6302016-03-18 08:42:01 +0100376config USB3_VBUS_PIN
377 string "Vbus enable pin for usb3 (ehci2)"
378 default ""
379 ---help---
380 See USB1_VBUS_PIN help text.
381
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200382config I2C0_ENABLE
383 bool "Enable I2C/TWI controller 0"
384 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
385 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200386 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200387 ---help---
388 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
389 its clock and setting up the bus. This is especially useful on devices
390 with slaves connected to the bus or with pins exposed through e.g. an
391 expansion port/header.
392
393config I2C1_ENABLE
394 bool "Enable I2C/TWI controller 1"
395 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200396 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200397 ---help---
398 See I2C0_ENABLE help text.
399
400config I2C2_ENABLE
401 bool "Enable I2C/TWI controller 2"
402 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200403 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200404 ---help---
405 See I2C0_ENABLE help text.
406
407if MACH_SUN6I || MACH_SUN7I
408config I2C3_ENABLE
409 bool "Enable I2C/TWI controller 3"
410 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200411 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200412 ---help---
413 See I2C0_ENABLE help text.
414endif
415
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100416if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100417config R_I2C_ENABLE
418 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100419 # This is used for the pmic on H3
420 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200421 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100422 ---help---
423 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100424endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100425
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200426if MACH_SUN7I
427config I2C4_ENABLE
428 bool "Enable I2C/TWI controller 4"
429 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200430 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200431 ---help---
432 See I2C0_ENABLE help text.
433endif
434
Hans de Goede2fcf0332015-04-25 17:25:14 +0200435config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900436 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200437 default n
438 ---help---
439 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
440
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200441config VIDEO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900442 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywarafa855d32016-09-05 01:32:40 +0100443 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200444 default y
445 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100446 Say Y here to add support for using a cfb console on the HDMI, LCD
447 or VGA output found on most sunxi devices. See doc/README.video for
448 info on how to select the video output and mode.
449
Hans de Goede2fbf0912014-12-23 23:04:35 +0100450config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900451 bool "HDMI output support"
Hans de Goede2fbf0912014-12-23 23:04:35 +0100452 depends on VIDEO && !MACH_SUN8I
453 default y
454 ---help---
455 Say Y here to add support for outputting video over HDMI.
456
Hans de Goeded9786d22014-12-25 13:58:06 +0100457config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900458 bool "VGA output support"
Hans de Goeded9786d22014-12-25 13:58:06 +0100459 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
460 default n
461 ---help---
462 Say Y here to add support for outputting video over VGA.
463
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100464config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900465 bool "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800466 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100467 default n
468 ---help---
469 Say Y here to add support for external DACs connected to the parallel
470 LCD interface driving a VGA connector, such as found on the
471 Olimex A13 boards.
472
Hans de Goedefb75d972015-01-25 15:33:07 +0100473config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900474 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100475 depends on VIDEO_VGA_VIA_LCD
476 default n
477 ---help---
478 Say Y here if you've a board which uses opendrain drivers for the vga
479 hsync and vsync signals. Opendrain drivers cannot generate steep enough
480 positive edges for a stable video output, so on boards with opendrain
481 drivers the sync signals must always be active high.
482
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800483config VIDEO_VGA_EXTERNAL_DAC_EN
484 string "LCD panel power enable pin"
485 depends on VIDEO_VGA_VIA_LCD
486 default ""
487 ---help---
488 Set the enable pin for the external VGA DAC. This takes a string in the
489 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
490
Hans de Goede39920c82015-08-03 19:20:26 +0200491config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900492 bool "Composite video output support"
Hans de Goede39920c82015-08-03 19:20:26 +0200493 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
494 default n
495 ---help---
496 Say Y here to add support for outputting composite video.
497
Hans de Goede2dae8002014-12-21 16:28:32 +0100498config VIDEO_LCD_MODE
499 string "LCD panel timing details"
500 depends on VIDEO
501 default ""
502 ---help---
503 LCD panel timing details string, leave empty if there is no LCD panel.
504 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
505 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200506 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100507
Hans de Goede65150322015-01-13 13:21:46 +0100508config VIDEO_LCD_DCLK_PHASE
509 int "LCD panel display clock phase"
510 depends on VIDEO
511 default 1
512 ---help---
513 Select LCD panel display clock phase shift, range 0-3.
514
Hans de Goede2dae8002014-12-21 16:28:32 +0100515config VIDEO_LCD_POWER
516 string "LCD panel power enable pin"
517 depends on VIDEO
518 default ""
519 ---help---
520 Set the power enable pin for the LCD panel. This takes a string in the
521 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
522
Hans de Goede242e3d82015-02-16 17:26:41 +0100523config VIDEO_LCD_RESET
524 string "LCD panel reset pin"
525 depends on VIDEO
526 default ""
527 ---help---
528 Set the reset pin for the LCD panel. This takes a string in the format
529 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
530
Hans de Goede2dae8002014-12-21 16:28:32 +0100531config VIDEO_LCD_BL_EN
532 string "LCD panel backlight enable pin"
533 depends on VIDEO
534 default ""
535 ---help---
536 Set the backlight enable pin for the LCD panel. This takes a string in the
537 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
538 port H.
539
540config VIDEO_LCD_BL_PWM
541 string "LCD panel backlight pwm pin"
542 depends on VIDEO
543 default ""
544 ---help---
545 Set the backlight pwm pin for the LCD panel. This takes a string in the
546 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200547
Hans de Goedea7403ae2015-01-22 21:02:42 +0100548config VIDEO_LCD_BL_PWM_ACTIVE_LOW
549 bool "LCD panel backlight pwm is inverted"
550 depends on VIDEO
551 default y
552 ---help---
553 Set this if the backlight pwm output is active low.
554
Hans de Goede55410082015-02-16 17:23:25 +0100555config VIDEO_LCD_PANEL_I2C
556 bool "LCD panel needs to be configured via i2c"
557 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100558 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200559 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100560 ---help---
561 Say y here if the LCD panel needs to be configured via i2c. This
562 will add a bitbang i2c controller using gpios to talk to the LCD.
563
564config VIDEO_LCD_PANEL_I2C_SDA
565 string "LCD panel i2c interface SDA pin"
566 depends on VIDEO_LCD_PANEL_I2C
567 default "PG12"
568 ---help---
569 Set the SDA pin for the LCD i2c interface. This takes a string in the
570 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
571
572config VIDEO_LCD_PANEL_I2C_SCL
573 string "LCD panel i2c interface SCL pin"
574 depends on VIDEO_LCD_PANEL_I2C
575 default "PG10"
576 ---help---
577 Set the SCL pin for the LCD i2c interface. This takes a string in the
578 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
579
Hans de Goede213480e2015-01-01 22:04:34 +0100580
581# Note only one of these may be selected at a time! But hidden choices are
582# not supported by Kconfig
583config VIDEO_LCD_IF_PARALLEL
584 bool
585
586config VIDEO_LCD_IF_LVDS
587 bool
588
589
590choice
591 prompt "LCD panel support"
592 depends on VIDEO
593 ---help---
594 Select which type of LCD panel to support.
595
596config VIDEO_LCD_PANEL_PARALLEL
597 bool "Generic parallel interface LCD panel"
598 select VIDEO_LCD_IF_PARALLEL
599
600config VIDEO_LCD_PANEL_LVDS
601 bool "Generic lvds interface LCD panel"
602 select VIDEO_LCD_IF_LVDS
603
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200604config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
605 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
606 select VIDEO_LCD_SSD2828
607 select VIDEO_LCD_IF_PARALLEL
608 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200609 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
610
611config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
612 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
613 select VIDEO_LCD_ANX9804
614 select VIDEO_LCD_IF_PARALLEL
615 select VIDEO_LCD_PANEL_I2C
616 ---help---
617 Select this for eDP LCD panels with 4 lanes running at 1.62G,
618 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200619
Hans de Goede27515b22015-01-20 09:23:36 +0100620config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
621 bool "Hitachi tx18d42vm LCD panel"
622 select VIDEO_LCD_HITACHI_TX18D42VM
623 select VIDEO_LCD_IF_LVDS
624 ---help---
625 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
626
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100627config VIDEO_LCD_TL059WV5C0
628 bool "tl059wv5c0 LCD panel"
629 select VIDEO_LCD_PANEL_I2C
630 select VIDEO_LCD_IF_PARALLEL
631 ---help---
632 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
633 Aigo M60/M608/M606 tablets.
634
Hans de Goede213480e2015-01-01 22:04:34 +0100635endchoice
636
637
Hans de Goedec13f60d2015-01-25 12:10:48 +0100638config GMAC_TX_DELAY
639 int "GMAC Transmit Clock Delay Chain"
640 default 0
641 ---help---
642 Set the GMAC Transmit Clock Delay Chain value.
643
Hans de Goedeff42d102015-09-13 13:02:48 +0200644config SPL_STACK_R_ADDR
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200645 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200646 default 0x2fe00000 if MACH_SUN9I
647
Masahiro Yamadadd840582014-07-30 14:08:14 +0900648endif