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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson38127742022-04-22 16:11:37 -040019 default MISC
Simon Glassaaba7032018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson38127742022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glassaaba7032018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Thomas Chouca844dd2015-10-14 08:43:31 +080046config ALTERA_SYSID
47 bool "Altera Sysid support"
48 depends on MISC
49 help
50 Select this to enable a sysid for Altera devices. Please find
51 details on the "Embedded Peripherals IP User Guide" of Altera.
52
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020053config ATSHA204A
54 bool "Support for Atmel ATSHA204A module"
Pali Rohár467f0c42022-04-12 11:20:44 +020055 select BITREVERSE
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020056 depends on MISC
57 help
58 Enable support for I2C connected Atmel's ATSHA204A
59 CryptoAuthentication module found for example on the Turris Omnia
60 board.
61
Tim Harvey8479b9e2022-03-07 16:24:04 -080062config GATEWORKS_SC
63 bool "Gateworks System Controller Support"
64 depends on MISC
65 help
66 Enable access for the Gateworks System Controller used on Gateworks
67 boards to provide a boot watchdog, power control, temperature monitor,
68 voltage ADCs, and EEPROM.
69
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020070config ROCKCHIP_EFUSE
71 bool "Rockchip e-fuse support"
72 depends on MISC
73 help
74 Enable (read-only) access for the e-fuse block found in Rockchip
75 SoCs: accesses can either be made using byte addressing and a length
76 or through child-nodes that are generated based on the e-fuse map
77 retrieved from the DTS.
78
79 This driver currently supports the RK3399 only, but can easily be
80 extended (by porting the read function from the Linux kernel sources)
81 to support other recent Rockchip devices.
82
Finley Xiaoa907dc32019-09-25 17:57:49 +020083config ROCKCHIP_OTP
84 bool "Rockchip OTP Support"
85 depends on MISC
86 help
87 Enable (read-only) access for the one-time-programmable memory block
88 found in Rockchip SoCs: accesses can either be made using byte
89 addressing and a length or through child-nodes that are generated
90 based on the e-fuse map retrieved from the DTS.
91
Pragnesh Patel05307212020-05-29 11:33:21 +053092config SIFIVE_OTP
93 bool "SiFive eMemory OTP driver"
94 depends on MISC
95 help
96 Enable support for reading and writing the eMemory OTP on the
97 SiFive SoCs.
98
Liviu Dudau0fabfeb2018-09-28 13:43:31 +010099config VEXPRESS_CONFIG
100 bool "Enable support for Arm Versatile Express config bus"
101 depends on MISC
102 help
103 If you say Y here, you will get support for accessing the
104 configuration bus on the Arm Versatile Express boards via
105 a sysreg driver.
106
Simon Glass6fb9ac12015-02-13 12:20:47 -0700107config CMD_CROS_EC
108 bool "Enable crosec command"
109 depends on CROS_EC
110 help
111 Enable command-line access to the Chrome OS EC (Embedded
112 Controller). This provides the 'crosec' command which has
113 a number of sub-commands for performing EC tasks such as
114 updating its flash, accessing a small saved context area
115 and talking to the I2C bus behind the EC (if there is one).
116
117config CROS_EC
118 bool "Enable Chrome OS EC"
119 help
120 Enable access to the Chrome OS EC. This is a separate
121 microcontroller typically available on a SPI bus on Chromebooks. It
122 provides access to the keyboard, some internal storage and may
123 control access to the battery and main PMIC depending on the
124 device. You can use the 'crosec' command to access it.
125
Simon Glassaaba7032018-11-18 08:14:27 -0700126config SPL_CROS_EC
127 bool "Enable Chrome OS EC in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400128 depends on SPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700129 help
130 Enable access to the Chrome OS EC in SPL. This is a separate
131 microcontroller typically available on a SPI bus on Chromebooks. It
132 provides access to the keyboard, some internal storage and may
133 control access to the battery and main PMIC depending on the
134 device. You can use the 'crosec' command to access it.
135
136config TPL_CROS_EC
137 bool "Enable Chrome OS EC in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400138 depends on TPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700139 help
140 Enable access to the Chrome OS EC in TPL. This is a separate
141 microcontroller typically available on a SPI bus on Chromebooks. It
142 provides access to the keyboard, some internal storage and may
143 control access to the battery and main PMIC depending on the
144 device. You can use the 'crosec' command to access it.
145
Simon Glass747093d2022-04-30 00:56:53 -0600146config VPL_CROS_EC
147 bool "Enable Chrome OS EC in VPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400148 depends on VPL_MISC
Simon Glass747093d2022-04-30 00:56:53 -0600149 help
150 Enable access to the Chrome OS EC in VPL. This is a separate
151 microcontroller typically available on a SPI bus on Chromebooks. It
152 provides access to the keyboard, some internal storage and may
153 control access to the battery and main PMIC depending on the
154 device. You can use the 'crosec' command to access it.
155
Simon Glass6fb9ac12015-02-13 12:20:47 -0700156config CROS_EC_I2C
157 bool "Enable Chrome OS EC I2C driver"
158 depends on CROS_EC
159 help
160 Enable I2C access to the Chrome OS EC. This is used on older
161 ARM Chromebooks such as snow and spring before the standard bus
162 changed to SPI. The EC will accept commands across the I2C using
163 a special message protocol, and provide responses.
164
165config CROS_EC_LPC
166 bool "Enable Chrome OS EC LPC driver"
167 depends on CROS_EC
168 help
169 Enable I2C access to the Chrome OS EC. This is used on x86
170 Chromebooks such as link and falco. The keyboard is provided
171 through a legacy port interface, so on x86 machines the main
172 function of the EC is power and thermal management.
173
Simon Glassaaba7032018-11-18 08:14:27 -0700174config SPL_CROS_EC_LPC
175 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400176 depends on CROS_EC && SPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700177 help
178 Enable I2C access to the Chrome OS EC. This is used on x86
179 Chromebooks such as link and falco. The keyboard is provided
180 through a legacy port interface, so on x86 machines the main
181 function of the EC is power and thermal management.
182
183config TPL_CROS_EC_LPC
184 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400185 depends on CROS_EC && TPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700186 help
187 Enable I2C access to the Chrome OS EC. This is used on x86
188 Chromebooks such as link and falco. The keyboard is provided
189 through a legacy port interface, so on x86 machines the main
190 function of the EC is power and thermal management.
191
Simon Glass747093d2022-04-30 00:56:53 -0600192config VPL_CROS_EC_LPC
193 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400194 depends on CROS_EC && VPL_MISC
Simon Glass747093d2022-04-30 00:56:53 -0600195 help
196 Enable I2C access to the Chrome OS EC. This is used on x86
197 Chromebooks such as link and falco. The keyboard is provided
198 through a legacy port interface, so on x86 machines the main
199 function of the EC is power and thermal management.
200
Simon Glass47cb8c62015-03-26 09:29:40 -0600201config CROS_EC_SANDBOX
202 bool "Enable Chrome OS EC sandbox driver"
203 depends on CROS_EC && SANDBOX
204 help
205 Enable a sandbox emulation of the Chrome OS EC. This supports
206 keyboard (use the -l flag to enable the LCD), verified boot context,
207 EC flash read/write/erase support and a few other things. It is
208 enough to perform a Chrome OS verified boot on sandbox.
209
Simon Glassaaba7032018-11-18 08:14:27 -0700210config SPL_CROS_EC_SANDBOX
211 bool "Enable Chrome OS EC sandbox driver in SPL"
212 depends on SPL_CROS_EC && SANDBOX
213 help
214 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
215 keyboard (use the -l flag to enable the LCD), verified boot context,
216 EC flash read/write/erase support and a few other things. It is
217 enough to perform a Chrome OS verified boot on sandbox.
218
219config TPL_CROS_EC_SANDBOX
220 bool "Enable Chrome OS EC sandbox driver in TPL"
221 depends on TPL_CROS_EC && SANDBOX
222 help
223 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
224 keyboard (use the -l flag to enable the LCD), verified boot context,
225 EC flash read/write/erase support and a few other things. It is
226 enough to perform a Chrome OS verified boot on sandbox.
227
Simon Glass747093d2022-04-30 00:56:53 -0600228config VPL_CROS_EC_SANDBOX
229 bool "Enable Chrome OS EC sandbox driver in VPL"
230 depends on VPL_CROS_EC && SANDBOX
231 help
232 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
233 keyboard (use the -l flag to enable the LCD), verified boot context,
234 EC flash read/write/erase support and a few other things. It is
235 enough to perform a Chrome OS verified boot on sandbox.
236
Simon Glass6fb9ac12015-02-13 12:20:47 -0700237config CROS_EC_SPI
238 bool "Enable Chrome OS EC SPI driver"
239 depends on CROS_EC
240 help
241 Enable SPI access to the Chrome OS EC. This is used on newer
242 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
243 provides a faster and more robust interface than I2C but the bugs
244 are less interesting.
245
Simon Glass879704d2017-05-17 03:25:02 -0600246config DS4510
247 bool "Enable support for DS4510 CPU supervisor"
248 help
249 Enable support for the Maxim DS4510 CPU supervisor. It has an
250 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
251 and a configurable timer for the supervisor function. The device is
252 connected over I2C.
253
Peng Fanc12e0d92015-08-26 15:41:33 +0800254config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530255 bool "Enable FSL SEC_MON Driver"
256 help
257 Freescale Security Monitor block is responsible for monitoring
258 system states.
259 Security Monitor can be transitioned on any security failures,
260 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100261
Simon Glass79d66a62019-12-06 21:41:58 -0700262config IRQ
Wasim Khan182c5f12021-03-08 16:48:13 +0100263 bool "Interrupt controller"
Simon Glass79d66a62019-12-06 21:41:58 -0700264 help
Wasim Khan182c5f12021-03-08 16:48:13 +0100265 This enables support for interrupt controllers, including ITSS.
Simon Glass79d66a62019-12-06 21:41:58 -0700266 Some devices have extra features, such as Apollo Lake. The
267 device has its own uclass since there are several operations
268 involved.
269
Paul Burtonb5392c52018-12-16 19:25:19 -0300270config JZ4780_EFUSE
271 bool "Ingenic JZ4780 eFUSE support"
272 depends on ARCH_JZ47XX
273 help
274 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
275
Peng Fan3e020f02015-08-27 14:49:05 +0800276config MXC_OCOTP
277 bool "Enable MXC OCOTP Driver"
Peng Fan994ab732019-07-22 01:24:55 +0000278 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100279 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800280 help
281 If you say Y here, you will get support for the One Time
282 Programmable memory pages that are stored on the some
283 Freescale i.MX processors.
284
Michael Scott33e9a692021-09-25 19:49:28 +0300285config SPL_MXC_OCOTP
286 bool "Enable MXC OCOTP driver in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400287 depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott33e9a692021-09-25 19:49:28 +0300288 default y
289 help
290 If you say Y here, you will get support for the One Time
291 Programmable memory pages, that are stored on some
292 Freescale i.MX processors, in SPL.
293
Stefan Roese4cf9e462016-07-19 07:45:46 +0200294config NUVOTON_NCT6102D
295 bool "Enable Nuvoton NCT6102D Super I/O driver"
296 help
297 If you say Y here, you will get support for the Nuvoton
298 NCT6102D Super I/O driver. This can be used to enable or
299 disable the legacy UART, the watchdog or other devices
300 in the Nuvoton Super IO chips on X86 platforms.
301
Simon Glass5bee27a2019-12-06 21:41:55 -0700302config P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200303 bool "Intel Primary to Sideband Bridge"
Simon Glass5bee27a2019-12-06 21:41:55 -0700304 depends on X86 || SANDBOX
305 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200306 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass5bee27a2019-12-06 21:41:55 -0700307 abbreviated to P2SB. The P2SB is used to access various peripherals
308 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
309 space. The space is segmented into different channels and peripherals
310 are accessed by device-specific means within those channels. Devices
311 should be added in the device tree as subnodes of the P2SB. A
312 Peripheral Channel Register? (PCR) API is provided to access those
313 devices - see pcr_readl(), etc.
314
315config SPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200316 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400317 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass5bee27a2019-12-06 21:41:55 -0700318 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200319 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700320 through memory-mapped I/O in a large chunk of PCI space. The space is
321 segmented into different channels and peripherals are accessed by
322 device-specific means within those channels. Devices should be added
323 in the device tree as subnodes of the p2sb.
324
325config TPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200326 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400327 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass5bee27a2019-12-06 21:41:55 -0700328 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200329 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700330 through memory-mapped I/O in a large chunk of PCI space. The space is
331 segmented into different channels and peripherals are accessed by
332 device-specific means within those channels. Devices should be added
333 in the device tree as subnodes of the p2sb.
334
Simon Glass5fd6bad2016-01-21 19:43:31 -0700335config PWRSEQ
336 bool "Enable power-sequencing drivers"
337 depends on DM
338 help
339 Power-sequencing drivers provide support for controlling power for
340 devices. They are typically referenced by a phandle from another
341 device. When the device is started up, its power sequence can be
342 initiated.
343
344config SPL_PWRSEQ
345 bool "Enable power-sequencing drivers for SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400346 depends on SPL_MISC && PWRSEQ
Simon Glass5fd6bad2016-01-21 19:43:31 -0700347 help
348 Power-sequencing drivers provide support for controlling power for
349 devices. They are typically referenced by a phandle from another
350 device. When the device is started up, its power sequence can be
351 initiated.
352
Stefan Roese1cdd9412015-03-12 11:22:46 +0100353config PCA9551_LED
354 bool "Enable PCA9551 LED driver"
355 help
356 Enable driver for PCA9551 LED controller. This controller
357 is connected via I2C. So I2C needs to be enabled.
358
359config PCA9551_I2C_ADDR
360 hex "I2C address of PCA9551 LED controller"
361 depends on PCA9551_LED
362 default 0x60
363 help
364 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600365
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200366config STM32MP_FUSE
367 bool "Enable STM32MP fuse wrapper providing the fuse API"
368 depends on ARCH_STM32MP && MISC
369 default y if CMD_FUSE
370 help
371 If you say Y here, you will get support for the fuse API (OTP)
372 for STM32MP architecture.
373 This API is needed for CMD_FUSE.
374
Christophe Kerello4e280b92017-09-13 18:00:08 +0200375config STM32_RCC
376 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner71f63542020-05-06 08:02:42 -0400377 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200378 help
379 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
380 block) is responsible of the management of the clock and reset
381 generation.
382 This driver is similar to an MFD driver in the Linux kernel.
383
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600384config TEGRA_CAR
385 bool "Enable support for the Tegra CAR driver"
386 depends on TEGRA_NO_BPMP
387 help
388 The Tegra CAR (Clock and Reset Controller) is a HW module that
389 controls almost all clocks and resets in a Tegra SoC.
390
Stephen Warren73dd5c42016-08-08 09:41:34 -0600391config TEGRA186_BPMP
392 bool "Enable support for the Tegra186 BPMP driver"
393 depends on TEGRA186
394 help
395 The Tegra BPMP (Boot and Power Management Processor) is a separate
396 auxiliary CPU embedded into Tegra to perform power management work,
397 and controls related features such as clocks, resets, power domains,
398 PMIC I2C bus, etc. This driver provides the core low-level
399 communication path by which feature-specific drivers (such as clock)
400 can make requests to the BPMP. This driver is similar to an MFD
401 driver in the Linux kernel.
402
Simon Glass079ac592020-12-23 08:11:18 -0700403config TEST_DRV
404 bool "Enable support for test drivers"
405 default y if SANDBOX
406 help
407 This enables drivers and uclasses that provides a way of testing the
408 operations of memory allocation and driver/uclass methods in driver
409 model. This should only be enabled for testing as it is not useful for
410 anything else.
411
Adam Fordcc3fedb2018-08-06 14:26:50 -0500412config TWL4030_LED
413 bool "Enable TWL4030 LED controller"
414 help
415 Enable this to add support for the TWL4030 LED controller.
416
Stefan Roese85056932016-01-19 14:05:10 +0100417config WINBOND_W83627
418 bool "Enable Winbond Super I/O driver"
419 help
420 If you say Y here, you will get support for the Winbond
421 W83627 Super I/O driver. This can be used to enable the
422 legacy UART or other devices in the Winbond Super IO chips
423 on X86 platforms.
424
Miao Yanfcf5c042016-05-22 19:37:14 -0700425config QFW
426 bool
427 help
Asherah Connor5b0b43e2021-03-19 18:21:40 +1100428 Hidden option to enable QEMU fw_cfg interface and uclass. This will
429 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
430
431config QFW_PIO
432 bool
433 depends on QFW
434 help
435 Hidden option to enable PIO QEMU fw_cfg interface. This will be
436 selected by the appropriate QEMU board.
Miao Yanfcf5c042016-05-22 19:37:14 -0700437
Asherah Connor5830b572021-03-19 18:21:42 +1100438config QFW_MMIO
439 bool
440 depends on QFW
441 help
442 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
443 selected by the appropriate QEMU board.
444
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200445config I2C_EEPROM
446 bool "Enable driver for generic I2C-attached EEPROMs"
447 depends on MISC
448 help
449 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500450
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800451
452config SPL_I2C_EEPROM
453 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400454 depends on SPL_MISC
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800455 help
456 This option is an SPL-variant of the I2C_EEPROM option.
457 See the help of I2C_EEPROM for details.
458
Adam Forde3f24d42017-08-13 09:00:28 -0500459config SYS_I2C_EEPROM_ADDR
460 hex "Chip address of the EEPROM device"
Tom Rini88cd7d02021-08-17 17:59:45 -0400461 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500462 default 0
463
Tom Rini88cd7d02021-08-17 17:59:45 -0400464if I2C_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500465
466config SYS_I2C_EEPROM_ADDR_OVERFLOW
467 hex "EEPROM Address Overflow"
Tom Rini5fd4a7e2021-12-11 14:55:47 -0500468 default 0x0
Adam Forde3f24d42017-08-13 09:00:28 -0500469 help
470 EEPROM chips that implement "address overflow" are ones
471 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
472 address and the extra bits end up in the "chip address" bit
473 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
474 byte chips.
475
476endif
477
Mario Six86da8c12018-04-27 14:53:33 +0200478config GDSYS_RXAUI_CTRL
479 bool "Enable gdsys RXAUI control driver"
480 depends on MISC
481 help
482 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200483
484config GDSYS_IOEP
485 bool "Enable gdsys IOEP driver"
486 depends on MISC
487 help
488 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200489
490config MPC83XX_SERDES
491 bool "Enable MPC83xx serdes driver"
492 depends on MISC
493 help
494 Support for serdes found on MPC83xx SoCs.
495
Tien Fong Chee62030002018-07-06 16:28:03 +0800496config FS_LOADER
497 bool "Enable loader driver for file system"
498 help
499 This is file system generic loader which can be used to load
500 the file image from the storage into target such as memory.
501
502 The consumer driver would then use this loader to program whatever,
503 ie. the FPGA device.
504
Keerthyb071a072022-01-27 13:16:53 +0100505config SPL_FS_LOADER
506 bool "Enable loader driver for file system"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400507 depends on SPL
Keerthyb071a072022-01-27 13:16:53 +0100508 help
509 This is file system generic loader which can be used to load
510 the file image from the storage into target such as memory.
511
512 The consumer driver would then use this loader to program whatever,
513 ie. the FPGA device.
514
Mario Sixc0a2b082018-10-04 09:00:54 +0200515config GDSYS_SOC
516 bool "Enable gdsys SOC driver"
517 depends on MISC
518 help
519 Support for gdsys IHS SOC, a simple bus associated with each gdsys
520 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
521 register maps are contained within the FPGA's register map.
522
Mario Sixab88bd22018-10-04 09:00:55 +0200523config IHS_FPGA
524 bool "Enable IHS FPGA driver"
525 depends on MISC
526 help
527 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
528 gdsys devices, which supply the majority of the functionality offered
529 by the devices. This driver supports both CON and CPU variants of the
530 devices, depending on the device tree entry.
Tero Kristo344eb6d2020-02-14 11:18:15 +0200531config ESM_K3
532 bool "Enable K3 ESM driver"
533 depends on ARCH_K3
534 help
535 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Sixab88bd22018-10-04 09:00:55 +0200536
Eugen Hristevf8164952019-10-09 09:23:39 +0000537config MICROCHIP_FLEXCOM
538 bool "Enable Microchip Flexcom driver"
539 depends on MISC
540 help
541 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
542 an I2C controller and an USART.
543 Only one function can be used at a time and is chosen at boot time
544 according to the device tree.
545
Tero Kristo9d233b42019-10-24 15:00:46 +0530546config K3_AVS0
547 depends on ARCH_K3 && SPL_DM_REGULATOR
548 bool "AVS class 0 support for K3 devices"
549 help
550 K3 devices have the optimized voltage values for the main voltage
551 domains stored in efuse within the VTM IP. This driver reads the
552 optimized voltage from the efuse, so that it can be programmed
553 to the PMIC on board.
554
Tero Kristo3b36b382020-02-14 11:18:16 +0200555config ESM_PMIC
556 bool "Enable PMIC ESM driver"
557 depends on DM_PMIC
558 help
559 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
560 typically to reboot the board in error condition.
561
Tom Rini98ab8312021-12-11 14:55:49 -0500562config FSL_IFC
563 bool
564
Michael Walle42595eb2022-02-25 18:06:24 +0530565config SL28CPLD
566 bool "Enable Kontron sl28cpld multi-function driver"
567 depends on DM_I2C
568 help
569 Support for the Kontron sl28cpld management controller. This is
570 the base driver which provides common access methods for the
571 sub-drivers.
572
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900573endmenu