Blame - arch/riscv/Kconfig - platform/external/u-boot

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Bin Meng	117a433	2018-09-26 06:55:06 -0700	[diff] [blame]	1	menu "RISC-V architecture"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	2	depends on RISCV
				3
				4	config SYS_ARCH
				5	default "riscv"
				6
				7	choice
				8	prompt "Target select"
				9	optional
				10
Rick Chen	6f4dd62	2018-05-29 09:54:40 +0800	[diff] [blame]	11	config TARGET_AX25_AE350
				12	bool "Support ax25-ae350"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	13
Bin Meng	510e379	2018-09-26 06:55:21 -0700	[diff] [blame]	14	config TARGET_QEMU_VIRT
				15	bool "Support QEMU Virt Board"
				16
Anup Patel	3fda026	2019-02-25 08:15:19 +0000	[diff] [blame]	17	config TARGET_SIFIVE_FU540
				18	bool "Support SiFive FU540 Board"
				19
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	20	endchoice
				21
Rick Chen	52923c6	2018-11-07 09:34:06 +0800	[diff] [blame]	22	# board-specific options below
Rick Chen	6f4dd62	2018-05-29 09:54:40 +0800	[diff] [blame]	23	source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng	510e379	2018-09-26 06:55:21 -0700	[diff] [blame]	24	source "board/emulation/qemu-riscv/Kconfig"
Anup Patel	3fda026	2019-02-25 08:15:19 +0000	[diff] [blame]	25	source "board/sifive/fu540/Kconfig"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	26
Rick Chen	52923c6	2018-11-07 09:34:06 +0800	[diff] [blame]	27	# platform-specific options below
				28	source "arch/riscv/cpu/ax25/Kconfig"
Anup Patel	fdff1f9	2019-02-25 08:14:10 +0000	[diff] [blame]	29	source "arch/riscv/cpu/generic/Kconfig"
Rick Chen	52923c6	2018-11-07 09:34:06 +0800	[diff] [blame]	30
				31	# architecture-specific options below
				32
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	33	choice
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	34	prompt "Base ISA"
				35	default ARCH_RV32I
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	36
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	37	config ARCH_RV32I
				38	bool "RV32I"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	39	select 32BIT
				40	help
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	41	Choose this option to target the RV32I base integer instruction set.
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	42
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	43	config ARCH_RV64I
				44	bool "RV64I"
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	45	select 64BIT
Lukas Auer	7115856	2018-11-22 11:26:13 +0100	[diff] [blame]	46	select PHYS_64BIT
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	47	help
Lukas Auer	862e2e7	2018-11-22 11:26:12 +0100	[diff] [blame]	48	Choose this option to target the RV64I base integer instruction set.
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	49
				50	endchoice
				51
Lukas Auer	8176ea4	2018-12-12 06:12:23 -0800	[diff] [blame]	52	choice
				53	prompt "Code Model"
				54	default CMODEL_MEDLOW
				55
				56	config CMODEL_MEDLOW
				57	bool "medium low code model"
				58	help
				59	U-Boot and its statically defined symbols must lie within a single 2 GiB
				60	address range and must lie between absolute addresses -2 GiB and +2 GiB.
				61
				62	config CMODEL_MEDANY
				63	bool "medium any code model"
				64	help
				65	U-Boot and its statically defined symbols must be within any single 2 GiB
				66	address range.
				67
				68	endchoice
				69
Anup Patel	3cfc825	2018-12-12 06:12:29 -0800	[diff] [blame]	70	choice
				71	prompt "Run Mode"
				72	default RISCV_MMODE
				73
				74	config RISCV_MMODE
				75	bool "Machine"
				76	help
				77	Choose this option to build U-Boot for RISC-V M-Mode.
				78
				79	config RISCV_SMODE
				80	bool "Supervisor"
				81	help
				82	Choose this option to build U-Boot for RISC-V S-Mode.
				83
				84	endchoice
				85
Lukas Auer	d57ffa6	2018-11-22 11:26:14 +0100	[diff] [blame]	86	config RISCV_ISA_C
				87	bool "Emit compressed instructions"
				88	default y
				89	help
				90	Adds "C" to the ISA subsets that the toolchain is allowed to emit
				91	when building U-Boot, which results in compressed instructions in the
				92	U-Boot binary.
				93
				94	config RISCV_ISA_A
				95	def_bool y
				96
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	97	config 32BIT
				98	bool
				99
				100	config 64BIT
				101	bool
				102
Bin Meng	644a3cd	2018-12-12 06:12:30 -0800	[diff] [blame]	103	config SIFIVE_CLINT
				104	bool
				105	depends on RISCV_MMODE
				106	select REGMAP
				107	select SYSCON
				108	help
				109	The SiFive CLINT block holds memory-mapped control and status registers
				110	associated with software and timer interrupts.
				111
Rick Chen	0d38946	2019-04-02 15:56:39 +0800	[diff] [blame]	112	config ANDES_PLIC
				113	bool
				114	depends on RISCV_MMODE
				115	select REGMAP
				116	select SYSCON
				117	help
				118	The Andes PLIC block holds memory-mapped claim and pending registers
				119	associated with software interrupt.
				120
Rick Chen	a1f2487	2019-04-02 15:56:40 +0800	[diff] [blame^]	121	config ANDES_PLMT
				122	bool
				123	depends on RISCV_MMODE
				124	select REGMAP
				125	select SYSCON
				126	help
				127	The Andes PLMT block holds memory-mapped mtime register
				128	associated with timer tick.
				129
Anup Patel	511107d	2018-12-12 06:12:31 -0800	[diff] [blame]	130	config RISCV_RDTIME
				131	bool
				132	default y if RISCV_SMODE
				133	help
				134	The provides the riscv_get_time() API that is implemented using the
				135	standard rdtime instruction. This is the case for S-mode U-Boot, and
				136	is useful for processors that support rdtime in M-mode too.
				137
Bin Meng	92b64fe	2018-12-12 06:12:33 -0800	[diff] [blame]	138	config SYS_MALLOC_F_LEN
				139	default 0x1000
				140
Lukas Auer	fa33f08	2019-03-17 19:28:32 +0100	[diff] [blame]	141	config SMP
				142	bool "Symmetric Multi-Processing"
				143	help
				144	This enables support for systems with more than one CPU. If
				145	you say N here, U-Boot will run on single and multiprocessor
				146	machines, but will use only one CPU of a multiprocessor
				147	machine. If you say Y here, U-Boot will run on many, but not
				148	all, single processor machines.
				149
				150	config NR_CPUS
				151	int "Maximum number of CPUs (2-32)"
				152	range 2 32
				153	depends on SMP
				154	default 8
				155	help
				156	On multiprocessor machines, U-Boot sets up a stack for each CPU.
				157	Stack memory is pre-allocated. U-Boot must therefore know the
				158	maximum number of CPUs that may be present.
				159
Lukas Auer	f152feb	2019-03-17 19:28:34 +0100	[diff] [blame]	160	config SBI_IPI
				161	bool
				162	default y if RISCV_SMODE
				163	depends on SMP
				164
Lukas Auer	3dea63c	2019-03-17 19:28:37 +0100	[diff] [blame]	165	config STACK_SIZE_SHIFT
				166	int
				167	default 13
				168
Rick Chen	f94c44e	2017-12-26 13:55:52 +0800	[diff] [blame]	169	endmenu