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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Michal Simek5ed063d2018-07-23 15:55:13 +020017 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010018 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010019 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +010021 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Michal Simek5ed063d2018-07-23 15:55:13 +020023 select SUPPORTS_LITTLE_ENDIAN
Masahiro Yamadadd840582014-07-30 14:08:14 +090024
25config TARGET_MALTA
26 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +010027 select DM
28 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +000029 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +010030 select MIPS_CM
Daniel Schwierzeckd1c3d8b2018-09-07 19:18:44 +020031 select MIPS_INSERT_BOOT_CONFIG
Michal Simek5ed063d2018-07-23 15:55:13 +020032 select MIPS_L1_CACHE_SHIFT_6
Paul Burton566ce04d2016-09-21 11:18:56 +010033 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +010034 select OF_CONTROL
35 select OF_ISA_BUS
Michal Simek5ed063d2018-07-23 15:55:13 +020036 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010037 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010038 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010040 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010041 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +020044 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010045 select SWAP_IO_SPACE
Michal Simek08a00cb2018-07-23 15:55:14 +020046 imply CMD_DM
Masahiro Yamadadd840582014-07-30 14:08:14 +090047
48config TARGET_VCT
49 bool "Support vct"
Michal Simek5ed063d2018-07-23 15:55:13 +020050 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010051 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010052 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000054 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090055
Wills Wang1d3d0f12016-03-16 16:59:52 +080056config ARCH_ATH79
57 bool "Support QCA/Atheros ath79"
Wills Wang1d3d0f12016-03-16 16:59:52 +080058 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +020059 select OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +020060 imply CMD_DM
Wills Wang1d3d0f12016-03-16 16:59:52 +080061
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020062config ARCH_BMIPS
63 bool "Support BMIPS SoCs"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020064 select CLK
65 select CPU
Michal Simek5ed063d2018-07-23 15:55:13 +020066 select DM
67 select OF_CONTROL
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020068 select RAM
69 select SYSRESET
Michal Simek08a00cb2018-07-23 15:55:14 +020070 imply CMD_DM
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020071
Stefan Roese4c835a62018-09-05 15:12:35 +020072config ARCH_MT7620
73 bool "Support MT7620/7688 SoCs"
74 imply CMD_DM
75 select DISPLAY_CPUINFO
76 select DM
Stefan Roeseb4a6a1b2018-10-09 08:59:09 +020077 imply DM_ETH
78 imply DM_GPIO
Stefan Roese4c835a62018-09-05 15:12:35 +020079 select DM_SERIAL
80 imply DM_SPI
81 imply DM_SPI_FLASH
82 select MIPS_TUNE_24KC
83 select OF_CONTROL
84 select ROM_EXCEPTION_VECTORS
85 select SUPPORTS_CPU_MIPS32_R1
86 select SUPPORTS_CPU_MIPS32_R2
87 select SUPPORTS_LITTLE_ENDIAN
Stefan Roese41f6e6e2018-08-16 15:27:32 +020088 select SYSRESET
Stefan Roese4c835a62018-09-05 15:12:35 +020089
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053090config MACH_PIC32
91 bool "Support Microchip PIC32"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053092 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +020093 select OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +020094 imply CMD_DM
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053095
Paul Burtonad8783c2016-09-08 07:47:39 +010096config TARGET_BOSTON
97 bool "Support Boston"
98 select DM
99 select DM_SERIAL
Paul Burtonad8783c2016-09-08 07:47:39 +0100100 select MIPS_CM
101 select MIPS_L1_CACHE_SHIFT_6
102 select MIPS_L2_CACHE
Paul Burtond2b12a52017-04-30 21:22:42 +0200103 select OF_BOARD_SETUP
Michal Simek5ed063d2018-07-23 15:55:13 +0200104 select OF_CONTROL
105 select ROM_EXCEPTION_VECTORS
Paul Burtonad8783c2016-09-08 07:47:39 +0100106 select SUPPORTS_BIG_ENDIAN
Paul Burtonad8783c2016-09-08 07:47:39 +0100107 select SUPPORTS_CPU_MIPS32_R1
108 select SUPPORTS_CPU_MIPS32_R2
109 select SUPPORTS_CPU_MIPS32_R6
110 select SUPPORTS_CPU_MIPS64_R1
111 select SUPPORTS_CPU_MIPS64_R2
112 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +0200113 select SUPPORTS_LITTLE_ENDIAN
Michal Simek08a00cb2018-07-23 15:55:14 +0200114 imply CMD_DM
Paul Burtonad8783c2016-09-08 07:47:39 +0100115
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100116config TARGET_XILFPGA
117 bool "Support Imagination Xilfpga"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100118 select DM
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100119 select DM_ETH
Michal Simek5ed063d2018-07-23 15:55:13 +0200120 select DM_GPIO
121 select DM_SERIAL
122 select MIPS_L1_CACHE_SHIFT_4
123 select OF_CONTROL
124 select ROM_EXCEPTION_VECTORS
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100125 select SUPPORTS_CPU_MIPS32_R1
126 select SUPPORTS_CPU_MIPS32_R2
Michal Simek5ed063d2018-07-23 15:55:13 +0200127 select SUPPORTS_LITTLE_ENDIAN
Michal Simek08a00cb2018-07-23 15:55:14 +0200128 imply CMD_DM
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100129 help
130 This supports IMGTEC MIPSfpga platform
131
Masahiro Yamadadd840582014-07-30 14:08:14 +0900132endchoice
133
Paul Burtonad8783c2016-09-08 07:47:39 +0100134source "board/imgtec/boston/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900135source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100136source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900137source "board/micronas/vct/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900138source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800139source "arch/mips/mach-ath79/Kconfig"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +0200140source "arch/mips/mach-bmips/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530141source "arch/mips/mach-pic32/Kconfig"
Stefan Roese4c835a62018-09-05 15:12:35 +0200142source "arch/mips/mach-mt7620/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900143
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100144if MIPS
145
146choice
147 prompt "Endianness selection"
148 help
149 Some MIPS boards can be configured for either little or big endian
150 byte order. These modes require different U-Boot images. In general there
151 is one preferred byteorder for a particular system but some systems are
152 just as commonly used in the one or the other endianness.
153
154config SYS_BIG_ENDIAN
155 bool "Big endian"
156 depends on SUPPORTS_BIG_ENDIAN
157
158config SYS_LITTLE_ENDIAN
159 bool "Little endian"
160 depends on SUPPORTS_LITTLE_ENDIAN
161
162endchoice
163
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100164choice
165 prompt "CPU selection"
166 default CPU_MIPS32_R2
167
168config CPU_MIPS32_R1
169 bool "MIPS32 Release 1"
170 depends on SUPPORTS_CPU_MIPS32_R1
171 select 32BIT
172 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100173 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100174 MIPS32 architecture.
175
176config CPU_MIPS32_R2
177 bool "MIPS32 Release 2"
178 depends on SUPPORTS_CPU_MIPS32_R2
179 select 32BIT
180 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100181 Choose this option to build an U-Boot for release 2 through 5 of the
182 MIPS32 architecture.
183
184config CPU_MIPS32_R6
185 bool "MIPS32 Release 6"
186 depends on SUPPORTS_CPU_MIPS32_R6
187 select 32BIT
188 help
189 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100190 MIPS32 architecture.
191
192config CPU_MIPS64_R1
193 bool "MIPS64 Release 1"
194 depends on SUPPORTS_CPU_MIPS64_R1
195 select 64BIT
196 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100197 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100198 MIPS64 architecture.
199
200config CPU_MIPS64_R2
201 bool "MIPS64 Release 2"
202 depends on SUPPORTS_CPU_MIPS64_R2
203 select 64BIT
204 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100205 Choose this option to build a kernel for release 2 through 5 of the
206 MIPS64 architecture.
207
208config CPU_MIPS64_R6
209 bool "MIPS64 Release 6"
210 depends on SUPPORTS_CPU_MIPS64_R6
211 select 64BIT
212 help
213 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100214 MIPS64 architecture.
215
216endchoice
217
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100218menu "General setup"
219
220config ROM_EXCEPTION_VECTORS
221 bool "Build U-Boot image with exception vectors"
222 help
223 Enable this to include exception vectors in the U-Boot image. This is
224 required if the U-Boot entry point is equal to the address of the
225 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
226 U-Boot booted from parallel NOR flash).
227 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
228 In that case the image size will be reduced by 0x500 bytes.
229
Paul Burton939a2552017-05-12 13:26:11 +0200230config MIPS_CM_BASE
231 hex "MIPS CM GCR Base Address"
232 depends on MIPS_CM
Paul Burtoned048e72017-04-30 21:22:41 +0200233 default 0x16100000 if TARGET_BOSTON
Paul Burton939a2552017-05-12 13:26:11 +0200234 default 0x1fbf8000
235 help
236 The physical base address at which to map the MIPS Coherence Manager
237 Global Configuration Registers (GCRs). This should be set such that
238 the GCRs occupy a region of the physical address space which is
239 otherwise unused, or at minimum that software doesn't need to access.
240
Daniel Schwierzeck5ef337a2018-09-07 19:02:05 +0200241config MIPS_CACHE_INDEX_BASE
242 hex "Index base address for cache initialisation"
243 default 0x80000000 if CPU_MIPS32
244 default 0xffffffff80000000 if CPU_MIPS64
245 help
246 This is the base address for a memory block, which is used for
247 initialising the cache lines. This is also the base address of a memory
248 block which is used for loading and filling cache lines when
249 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
250 Normally this is CKSEG0. If the MIPS system needs to move this block
251 to some SRAM or ScratchPad RAM, adapt this option accordingly.
252
Daniel Schwierzeck96301462018-11-01 02:02:21 +0100253config MIPS_RELOCATION_TABLE_SIZE
254 hex "Relocation table size"
255 range 0x100 0x10000
256 default "0x8000"
257 ---help---
258 A table of relocation data will be appended to the U-Boot binary
259 and parsed in relocate_code() to fix up all offsets in the relocated
260 U-Boot.
261
262 This option allows the amount of space reserved for the table to be
263 adjusted in a range from 256 up to 64k. The default is 32k and should
264 be ok in most cases. Reduce this value to shrink the size of U-Boot
265 binary.
266
267 The build will fail and a valid size suggested if this is too small.
268
269 If unsure, leave at the default value.
270
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100271endmenu
272
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100273menu "OS boot interface"
274
275config MIPS_BOOT_CMDLINE_LEGACY
276 bool "Hand over legacy command line to Linux kernel"
277 default y
278 help
279 Enable this option if you want U-Boot to hand over the Yamon-style
280 command line to the kernel. All bootargs will be prepared as argc/argv
281 compatible list. The argument count (argc) is stored in register $a0.
282 The address of the argument list (argv) is stored in register $a1.
283
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100284config MIPS_BOOT_ENV_LEGACY
285 bool "Hand over legacy environment to Linux kernel"
286 default y
287 help
288 Enable this option if you want U-Boot to hand over the Yamon-style
289 environment to the kernel. Information like memory size, initrd
290 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400291 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100292
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100293config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100294 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100295 default n
296 help
297 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100298 device tree to the kernel. According to UHI register $a0 will be set
299 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100300
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100301endmenu
302
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100303config SUPPORTS_BIG_ENDIAN
304 bool
305
306config SUPPORTS_LITTLE_ENDIAN
307 bool
308
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100309config SUPPORTS_CPU_MIPS32_R1
310 bool
311
312config SUPPORTS_CPU_MIPS32_R2
313 bool
314
Paul Burtonc52ebea2016-05-16 10:52:12 +0100315config SUPPORTS_CPU_MIPS32_R6
316 bool
317
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100318config SUPPORTS_CPU_MIPS64_R1
319 bool
320
321config SUPPORTS_CPU_MIPS64_R2
322 bool
323
Paul Burtonc52ebea2016-05-16 10:52:12 +0100324config SUPPORTS_CPU_MIPS64_R6
325 bool
326
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100327config CPU_MIPS32
328 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100329 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100330
331config CPU_MIPS64
332 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100333 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100334
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100335config MIPS_TUNE_4KC
336 bool
337
338config MIPS_TUNE_14KC
339 bool
340
341config MIPS_TUNE_24KC
342 bool
343
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200344config MIPS_TUNE_34KC
345 bool
346
Marek Vasut0a0a9582016-05-06 20:10:33 +0200347config MIPS_TUNE_74KC
348 bool
349
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100350config 32BIT
351 bool
352
353config 64BIT
354 bool
355
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100356config SWAP_IO_SPACE
357 bool
358
Paul Burtondd7c7202015-01-29 01:28:02 +0000359config SYS_MIPS_CACHE_INIT_RAM_LOAD
360 bool
361
Daniel Schwierzeck924ad862016-06-04 16:13:21 +0200362config MIPS_INIT_STACK_IN_SRAM
363 bool
364 default n
365 help
366 Select this if the initial stack frame could be setup in SRAM.
367 Normally the initial stack frame is set up in DRAM which is often
368 only available after lowlevel_init. With this option the initial
369 stack frame and the early C environment is set up before
370 lowlevel_init. Thus lowlevel_init does not need to be implemented
371 in assembler.
372
Paul Burtonace3be42016-05-27 14:28:04 +0100373config SYS_DCACHE_SIZE
374 int
375 default 0
376 help
377 The total size of the L1 Dcache, if known at compile time.
378
Paul Burton37228622016-05-27 14:28:05 +0100379config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100380 int
Paul Burton37228622016-05-27 14:28:05 +0100381 default 0
382 help
383 The size of L1 Dcache lines, if known at compile time.
384
Paul Burtonace3be42016-05-27 14:28:04 +0100385config SYS_ICACHE_SIZE
386 int
387 default 0
388 help
389 The total size of the L1 ICache, if known at compile time.
390
Paul Burton37228622016-05-27 14:28:05 +0100391config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100392 int
393 default 0
394 help
Paul Burton37228622016-05-27 14:28:05 +0100395 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100396
397config SYS_CACHE_SIZE_AUTO
398 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100399 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100400 help
401 Select this (or let it be auto-selected by not defining any cache
402 sizes) in order to allow U-Boot to automatically detect the sizes
403 of caches at runtime. This has a small cost in code size & runtime
404 so if you know the cache configuration for your system at compile
405 time it would be beneficial to configure it.
406
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100407config MIPS_L1_CACHE_SHIFT_4
408 bool
409
410config MIPS_L1_CACHE_SHIFT_5
411 bool
412
413config MIPS_L1_CACHE_SHIFT_6
414 bool
415
416config MIPS_L1_CACHE_SHIFT_7
417 bool
418
419config MIPS_L1_CACHE_SHIFT
420 int
421 default "7" if MIPS_L1_CACHE_SHIFT_7
422 default "6" if MIPS_L1_CACHE_SHIFT_6
423 default "5" if MIPS_L1_CACHE_SHIFT_5
424 default "4" if MIPS_L1_CACHE_SHIFT_4
425 default "5"
426
Paul Burton4baa0ab2016-09-21 11:18:54 +0100427config MIPS_L2_CACHE
428 bool
429 help
430 Select this if your system includes an L2 cache and you want U-Boot
431 to initialise & maintain it.
432
Paul Burton05e34252016-01-29 13:54:52 +0000433config DYNAMIC_IO_PORT_BASE
434 bool
435
Paul Burtonb2b135d2016-09-21 11:18:53 +0100436config MIPS_CM
437 bool
438 help
439 Select this if your system contains a MIPS Coherence Manager and you
440 wish U-Boot to configure it or make use of it to retrieve system
441 information such as cache configuration.
442
Daniel Schwierzeckd1c3d8b2018-09-07 19:18:44 +0200443config MIPS_INSERT_BOOT_CONFIG
444 bool
445 default n
446 help
447 Enable this to insert some board-specific boot configuration in
448 the U-Boot binary at offset 0x10.
449
450config MIPS_BOOT_CONFIG_WORD0
451 hex
452 depends on MIPS_INSERT_BOOT_CONFIG
453 default 0x420 if TARGET_MALTA
454 default 0x0
455 help
456 Value which is inserted as boot config word 0.
457
458config MIPS_BOOT_CONFIG_WORD1
459 hex
460 depends on MIPS_INSERT_BOOT_CONFIG
461 default 0x0
462 help
463 Value which is inserted as boot config word 1.
464
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100465endif
466
Masahiro Yamadadd840582014-07-30 14:08:14 +0900467endmenu