Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | menu "MIPS architecture" |
| 2 | depends on MIPS |
| 3 | |
| 4 | config SYS_ARCH |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 5 | default "mips" |
| 6 | |
Daniel Schwierzeck | b9863b6 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 7 | config SYS_CPU |
Paul Burton | 20286cd | 2016-05-16 10:52:11 +0100 | [diff] [blame] | 8 | default "mips32" if CPU_MIPS32 |
| 9 | default "mips64" if CPU_MIPS64 |
Daniel Schwierzeck | b9863b6 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 10 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 11 | choice |
| 12 | prompt "Target select" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 13 | optional |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 14 | |
| 15 | config TARGET_QEMU_MIPS |
| 16 | bool "Support qemu-mips" |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 17 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 18 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 19 | select SUPPORTS_CPU_MIPS32_R1 |
| 20 | select SUPPORTS_CPU_MIPS32_R2 |
Daniel Schwierzeck | aa45f75 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 21 | select SUPPORTS_CPU_MIPS64_R1 |
| 22 | select SUPPORTS_CPU_MIPS64_R2 |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 23 | select SUPPORTS_LITTLE_ENDIAN |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 24 | |
| 25 | config TARGET_MALTA |
| 26 | bool "Support malta" |
Paul Burton | 6242aa1 | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 27 | select DM |
| 28 | select DM_SERIAL |
Paul Burton | 05e3425 | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 29 | select DYNAMIC_IO_PORT_BASE |
Paul Burton | 566ce04d | 2016-09-21 11:18:56 +0100 | [diff] [blame] | 30 | select MIPS_CM |
Daniel Schwierzeck | d1c3d8b | 2018-09-07 19:18:44 +0200 | [diff] [blame] | 31 | select MIPS_INSERT_BOOT_CONFIG |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 32 | select MIPS_L1_CACHE_SHIFT_6 |
Paul Burton | 566ce04d | 2016-09-21 11:18:56 +0100 | [diff] [blame] | 33 | select MIPS_L2_CACHE |
Paul Burton | 6242aa1 | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 34 | select OF_CONTROL |
| 35 | select OF_ISA_BUS |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 36 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 37 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 38 | select SUPPORTS_CPU_MIPS32_R1 |
| 39 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 40ba13c | 2016-05-16 10:52:14 +0100 | [diff] [blame] | 40 | select SUPPORTS_CPU_MIPS32_R6 |
Paul Burton | 0f832b9 | 2016-05-26 14:49:36 +0100 | [diff] [blame] | 41 | select SUPPORTS_CPU_MIPS64_R1 |
| 42 | select SUPPORTS_CPU_MIPS64_R2 |
| 43 | select SUPPORTS_CPU_MIPS64_R6 |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 44 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 9d638ee | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 45 | select SWAP_IO_SPACE |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 46 | imply CMD_DM |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 47 | |
| 48 | config TARGET_VCT |
| 49 | bool "Support vct" |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 50 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 51 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 52 | select SUPPORTS_CPU_MIPS32_R1 |
| 53 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 54 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 55 | |
Wills Wang | 1d3d0f1 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 56 | config ARCH_ATH79 |
| 57 | bool "Support QCA/Atheros ath79" |
Wills Wang | 1d3d0f1 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 58 | select DM |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 59 | select OF_CONTROL |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 60 | imply CMD_DM |
Wills Wang | 1d3d0f1 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 61 | |
Álvaro Fernández Rojas | ee42214 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 62 | config ARCH_BMIPS |
| 63 | bool "Support BMIPS SoCs" |
Álvaro Fernández Rojas | ee42214 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 64 | select CLK |
| 65 | select CPU |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 66 | select DM |
| 67 | select OF_CONTROL |
Álvaro Fernández Rojas | ee42214 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 68 | select RAM |
| 69 | select SYSRESET |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 70 | imply CMD_DM |
Álvaro Fernández Rojas | ee42214 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 71 | |
Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 72 | config ARCH_MT7620 |
| 73 | bool "Support MT7620/7688 SoCs" |
| 74 | imply CMD_DM |
| 75 | select DISPLAY_CPUINFO |
| 76 | select DM |
Stefan Roese | b4a6a1b | 2018-10-09 08:59:09 +0200 | [diff] [blame^] | 77 | imply DM_ETH |
| 78 | imply DM_GPIO |
Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 79 | select DM_SERIAL |
| 80 | imply DM_SPI |
| 81 | imply DM_SPI_FLASH |
| 82 | select MIPS_TUNE_24KC |
| 83 | select OF_CONTROL |
| 84 | select ROM_EXCEPTION_VECTORS |
| 85 | select SUPPORTS_CPU_MIPS32_R1 |
| 86 | select SUPPORTS_CPU_MIPS32_R2 |
| 87 | select SUPPORTS_LITTLE_ENDIAN |
Stefan Roese | 41f6e6e | 2018-08-16 15:27:32 +0200 | [diff] [blame] | 88 | select SYSRESET |
Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 89 | |
Purna Chandra Mandal | 32c1a6e | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 90 | config MACH_PIC32 |
| 91 | bool "Support Microchip PIC32" |
Purna Chandra Mandal | 32c1a6e | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 92 | select DM |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 93 | select OF_CONTROL |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 94 | imply CMD_DM |
Purna Chandra Mandal | 32c1a6e | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 95 | |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 96 | config TARGET_BOSTON |
| 97 | bool "Support Boston" |
| 98 | select DM |
| 99 | select DM_SERIAL |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 100 | select MIPS_CM |
| 101 | select MIPS_L1_CACHE_SHIFT_6 |
| 102 | select MIPS_L2_CACHE |
Paul Burton | d2b12a5 | 2017-04-30 21:22:42 +0200 | [diff] [blame] | 103 | select OF_BOARD_SETUP |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 104 | select OF_CONTROL |
| 105 | select ROM_EXCEPTION_VECTORS |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 106 | select SUPPORTS_BIG_ENDIAN |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 107 | select SUPPORTS_CPU_MIPS32_R1 |
| 108 | select SUPPORTS_CPU_MIPS32_R2 |
| 109 | select SUPPORTS_CPU_MIPS32_R6 |
| 110 | select SUPPORTS_CPU_MIPS64_R1 |
| 111 | select SUPPORTS_CPU_MIPS64_R2 |
| 112 | select SUPPORTS_CPU_MIPS64_R6 |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 113 | select SUPPORTS_LITTLE_ENDIAN |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 114 | imply CMD_DM |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 115 | |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 116 | config TARGET_XILFPGA |
| 117 | bool "Support Imagination Xilfpga" |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 118 | select DM |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 119 | select DM_ETH |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 120 | select DM_GPIO |
| 121 | select DM_SERIAL |
| 122 | select MIPS_L1_CACHE_SHIFT_4 |
| 123 | select OF_CONTROL |
| 124 | select ROM_EXCEPTION_VECTORS |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 125 | select SUPPORTS_CPU_MIPS32_R1 |
| 126 | select SUPPORTS_CPU_MIPS32_R2 |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 127 | select SUPPORTS_LITTLE_ENDIAN |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 128 | imply CMD_DM |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 129 | help |
| 130 | This supports IMGTEC MIPSfpga platform |
| 131 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 132 | endchoice |
| 133 | |
Paul Burton | ad8783c | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 134 | source "board/imgtec/boston/Kconfig" |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 135 | source "board/imgtec/malta/Kconfig" |
Zubair Lutfullah Kakakhel | ebf2b9e | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 136 | source "board/imgtec/xilfpga/Kconfig" |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 137 | source "board/micronas/vct/Kconfig" |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 138 | source "board/qemu-mips/Kconfig" |
Wills Wang | 1d3d0f1 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 139 | source "arch/mips/mach-ath79/Kconfig" |
Álvaro Fernández Rojas | ee42214 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 140 | source "arch/mips/mach-bmips/Kconfig" |
Purna Chandra Mandal | 32c1a6e | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 141 | source "arch/mips/mach-pic32/Kconfig" |
Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 142 | source "arch/mips/mach-mt7620/Kconfig" |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 143 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 144 | if MIPS |
| 145 | |
| 146 | choice |
| 147 | prompt "Endianness selection" |
| 148 | help |
| 149 | Some MIPS boards can be configured for either little or big endian |
| 150 | byte order. These modes require different U-Boot images. In general there |
| 151 | is one preferred byteorder for a particular system but some systems are |
| 152 | just as commonly used in the one or the other endianness. |
| 153 | |
| 154 | config SYS_BIG_ENDIAN |
| 155 | bool "Big endian" |
| 156 | depends on SUPPORTS_BIG_ENDIAN |
| 157 | |
| 158 | config SYS_LITTLE_ENDIAN |
| 159 | bool "Little endian" |
| 160 | depends on SUPPORTS_LITTLE_ENDIAN |
| 161 | |
| 162 | endchoice |
| 163 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 164 | choice |
| 165 | prompt "CPU selection" |
| 166 | default CPU_MIPS32_R2 |
| 167 | |
| 168 | config CPU_MIPS32_R1 |
| 169 | bool "MIPS32 Release 1" |
| 170 | depends on SUPPORTS_CPU_MIPS32_R1 |
| 171 | select 32BIT |
| 172 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 173 | Choose this option to build an U-Boot for release 1 through 5 of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 174 | MIPS32 architecture. |
| 175 | |
| 176 | config CPU_MIPS32_R2 |
| 177 | bool "MIPS32 Release 2" |
| 178 | depends on SUPPORTS_CPU_MIPS32_R2 |
| 179 | select 32BIT |
| 180 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 181 | Choose this option to build an U-Boot for release 2 through 5 of the |
| 182 | MIPS32 architecture. |
| 183 | |
| 184 | config CPU_MIPS32_R6 |
| 185 | bool "MIPS32 Release 6" |
| 186 | depends on SUPPORTS_CPU_MIPS32_R6 |
| 187 | select 32BIT |
| 188 | help |
| 189 | Choose this option to build an U-Boot for release 6 or later of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 190 | MIPS32 architecture. |
| 191 | |
| 192 | config CPU_MIPS64_R1 |
| 193 | bool "MIPS64 Release 1" |
| 194 | depends on SUPPORTS_CPU_MIPS64_R1 |
| 195 | select 64BIT |
| 196 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 197 | Choose this option to build a kernel for release 1 through 5 of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 198 | MIPS64 architecture. |
| 199 | |
| 200 | config CPU_MIPS64_R2 |
| 201 | bool "MIPS64 Release 2" |
| 202 | depends on SUPPORTS_CPU_MIPS64_R2 |
| 203 | select 64BIT |
| 204 | help |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 205 | Choose this option to build a kernel for release 2 through 5 of the |
| 206 | MIPS64 architecture. |
| 207 | |
| 208 | config CPU_MIPS64_R6 |
| 209 | bool "MIPS64 Release 6" |
| 210 | depends on SUPPORTS_CPU_MIPS64_R6 |
| 211 | select 64BIT |
| 212 | help |
| 213 | Choose this option to build a kernel for release 6 or later of the |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 214 | MIPS64 architecture. |
| 215 | |
| 216 | endchoice |
| 217 | |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 218 | menu "General setup" |
| 219 | |
| 220 | config ROM_EXCEPTION_VECTORS |
| 221 | bool "Build U-Boot image with exception vectors" |
| 222 | help |
| 223 | Enable this to include exception vectors in the U-Boot image. This is |
| 224 | required if the U-Boot entry point is equal to the address of the |
| 225 | CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, |
| 226 | U-Boot booted from parallel NOR flash). |
| 227 | Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). |
| 228 | In that case the image size will be reduced by 0x500 bytes. |
| 229 | |
Paul Burton | 939a255 | 2017-05-12 13:26:11 +0200 | [diff] [blame] | 230 | config MIPS_CM_BASE |
| 231 | hex "MIPS CM GCR Base Address" |
| 232 | depends on MIPS_CM |
Paul Burton | ed048e7 | 2017-04-30 21:22:41 +0200 | [diff] [blame] | 233 | default 0x16100000 if TARGET_BOSTON |
Paul Burton | 939a255 | 2017-05-12 13:26:11 +0200 | [diff] [blame] | 234 | default 0x1fbf8000 |
| 235 | help |
| 236 | The physical base address at which to map the MIPS Coherence Manager |
| 237 | Global Configuration Registers (GCRs). This should be set such that |
| 238 | the GCRs occupy a region of the physical address space which is |
| 239 | otherwise unused, or at minimum that software doesn't need to access. |
| 240 | |
Daniel Schwierzeck | 5ef337a | 2018-09-07 19:02:05 +0200 | [diff] [blame] | 241 | config MIPS_CACHE_INDEX_BASE |
| 242 | hex "Index base address for cache initialisation" |
| 243 | default 0x80000000 if CPU_MIPS32 |
| 244 | default 0xffffffff80000000 if CPU_MIPS64 |
| 245 | help |
| 246 | This is the base address for a memory block, which is used for |
| 247 | initialising the cache lines. This is also the base address of a memory |
| 248 | block which is used for loading and filling cache lines when |
| 249 | SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. |
| 250 | Normally this is CKSEG0. If the MIPS system needs to move this block |
| 251 | to some SRAM or ScratchPad RAM, adapt this option accordingly. |
| 252 | |
Daniel Schwierzeck | 9630146 | 2018-11-01 02:02:21 +0100 | [diff] [blame] | 253 | config MIPS_RELOCATION_TABLE_SIZE |
| 254 | hex "Relocation table size" |
| 255 | range 0x100 0x10000 |
| 256 | default "0x8000" |
| 257 | ---help--- |
| 258 | A table of relocation data will be appended to the U-Boot binary |
| 259 | and parsed in relocate_code() to fix up all offsets in the relocated |
| 260 | U-Boot. |
| 261 | |
| 262 | This option allows the amount of space reserved for the table to be |
| 263 | adjusted in a range from 256 up to 64k. The default is 32k and should |
| 264 | be ok in most cases. Reduce this value to shrink the size of U-Boot |
| 265 | binary. |
| 266 | |
| 267 | The build will fail and a valid size suggested if this is too small. |
| 268 | |
| 269 | If unsure, leave at the default value. |
| 270 | |
Daniel Schwierzeck | af3971f | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 271 | endmenu |
| 272 | |
Daniel Schwierzeck | 25fc664 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 273 | menu "OS boot interface" |
| 274 | |
| 275 | config MIPS_BOOT_CMDLINE_LEGACY |
| 276 | bool "Hand over legacy command line to Linux kernel" |
| 277 | default y |
| 278 | help |
| 279 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 280 | command line to the kernel. All bootargs will be prepared as argc/argv |
| 281 | compatible list. The argument count (argc) is stored in register $a0. |
| 282 | The address of the argument list (argv) is stored in register $a1. |
| 283 | |
Daniel Schwierzeck | ca65e58 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 284 | config MIPS_BOOT_ENV_LEGACY |
| 285 | bool "Hand over legacy environment to Linux kernel" |
| 286 | default y |
| 287 | help |
| 288 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 289 | environment to the kernel. Information like memory size, initrd |
| 290 | address and size will be prepared as zero-terminated key/value list. |
Robert P. J. Day | 1cc0a9f | 2016-05-04 04:47:31 -0400 | [diff] [blame] | 291 | The address of the environment is stored in register $a2. |
Daniel Schwierzeck | ca65e58 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 292 | |
Daniel Schwierzeck | 5002d8c | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 293 | config MIPS_BOOT_FDT |
Daniel Schwierzeck | 90b1c9f | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 294 | bool "Hand over a flattened device tree to Linux kernel" |
Daniel Schwierzeck | 5002d8c | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 295 | default n |
| 296 | help |
| 297 | Enable this option if you want U-Boot to hand over a flattened |
Daniel Schwierzeck | 90b1c9f | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 298 | device tree to the kernel. According to UHI register $a0 will be set |
| 299 | to -2 and the FDT address is stored in $a1. |
Daniel Schwierzeck | 5002d8c | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 300 | |
Daniel Schwierzeck | 25fc664 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 301 | endmenu |
| 302 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 303 | config SUPPORTS_BIG_ENDIAN |
| 304 | bool |
| 305 | |
| 306 | config SUPPORTS_LITTLE_ENDIAN |
| 307 | bool |
| 308 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 309 | config SUPPORTS_CPU_MIPS32_R1 |
| 310 | bool |
| 311 | |
| 312 | config SUPPORTS_CPU_MIPS32_R2 |
| 313 | bool |
| 314 | |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 315 | config SUPPORTS_CPU_MIPS32_R6 |
| 316 | bool |
| 317 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 318 | config SUPPORTS_CPU_MIPS64_R1 |
| 319 | bool |
| 320 | |
| 321 | config SUPPORTS_CPU_MIPS64_R2 |
| 322 | bool |
| 323 | |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 324 | config SUPPORTS_CPU_MIPS64_R6 |
| 325 | bool |
| 326 | |
Daniel Schwierzeck | c57dafb | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 327 | config CPU_MIPS32 |
| 328 | bool |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 329 | default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 |
Daniel Schwierzeck | c57dafb | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 330 | |
| 331 | config CPU_MIPS64 |
| 332 | bool |
Paul Burton | c52ebea | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 333 | default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 |
Daniel Schwierzeck | c57dafb | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 334 | |
Daniel Schwierzeck | 0315a28 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 335 | config MIPS_TUNE_4KC |
| 336 | bool |
| 337 | |
| 338 | config MIPS_TUNE_14KC |
| 339 | bool |
| 340 | |
| 341 | config MIPS_TUNE_24KC |
| 342 | bool |
| 343 | |
Daniel Schwierzeck | 5f9cc36 | 2016-05-27 15:39:39 +0200 | [diff] [blame] | 344 | config MIPS_TUNE_34KC |
| 345 | bool |
| 346 | |
Marek Vasut | 0a0a958 | 2016-05-06 20:10:33 +0200 | [diff] [blame] | 347 | config MIPS_TUNE_74KC |
| 348 | bool |
| 349 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 350 | config 32BIT |
| 351 | bool |
| 352 | |
| 353 | config 64BIT |
| 354 | bool |
| 355 | |
Daniel Schwierzeck | 9d638ee | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 356 | config SWAP_IO_SPACE |
| 357 | bool |
| 358 | |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 359 | config SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 360 | bool |
| 361 | |
Daniel Schwierzeck | 924ad86 | 2016-06-04 16:13:21 +0200 | [diff] [blame] | 362 | config MIPS_INIT_STACK_IN_SRAM |
| 363 | bool |
| 364 | default n |
| 365 | help |
| 366 | Select this if the initial stack frame could be setup in SRAM. |
| 367 | Normally the initial stack frame is set up in DRAM which is often |
| 368 | only available after lowlevel_init. With this option the initial |
| 369 | stack frame and the early C environment is set up before |
| 370 | lowlevel_init. Thus lowlevel_init does not need to be implemented |
| 371 | in assembler. |
| 372 | |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 373 | config SYS_DCACHE_SIZE |
| 374 | int |
| 375 | default 0 |
| 376 | help |
| 377 | The total size of the L1 Dcache, if known at compile time. |
| 378 | |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 379 | config SYS_DCACHE_LINE_SIZE |
Paul Burton | 4b7b0a0 | 2016-06-09 13:09:52 +0100 | [diff] [blame] | 380 | int |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 381 | default 0 |
| 382 | help |
| 383 | The size of L1 Dcache lines, if known at compile time. |
| 384 | |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 385 | config SYS_ICACHE_SIZE |
| 386 | int |
| 387 | default 0 |
| 388 | help |
| 389 | The total size of the L1 ICache, if known at compile time. |
| 390 | |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 391 | config SYS_ICACHE_LINE_SIZE |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 392 | int |
| 393 | default 0 |
| 394 | help |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 395 | The size of L1 Icache lines, if known at compile time. |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 396 | |
| 397 | config SYS_CACHE_SIZE_AUTO |
| 398 | def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 399 | SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 |
Paul Burton | ace3be4 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 400 | help |
| 401 | Select this (or let it be auto-selected by not defining any cache |
| 402 | sizes) in order to allow U-Boot to automatically detect the sizes |
| 403 | of caches at runtime. This has a small cost in code size & runtime |
| 404 | so if you know the cache configuration for your system at compile |
| 405 | time it would be beneficial to configure it. |
| 406 | |
Daniel Schwierzeck | f53830e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 407 | config MIPS_L1_CACHE_SHIFT_4 |
| 408 | bool |
| 409 | |
| 410 | config MIPS_L1_CACHE_SHIFT_5 |
| 411 | bool |
| 412 | |
| 413 | config MIPS_L1_CACHE_SHIFT_6 |
| 414 | bool |
| 415 | |
| 416 | config MIPS_L1_CACHE_SHIFT_7 |
| 417 | bool |
| 418 | |
| 419 | config MIPS_L1_CACHE_SHIFT |
| 420 | int |
| 421 | default "7" if MIPS_L1_CACHE_SHIFT_7 |
| 422 | default "6" if MIPS_L1_CACHE_SHIFT_6 |
| 423 | default "5" if MIPS_L1_CACHE_SHIFT_5 |
| 424 | default "4" if MIPS_L1_CACHE_SHIFT_4 |
| 425 | default "5" |
| 426 | |
Paul Burton | 4baa0ab | 2016-09-21 11:18:54 +0100 | [diff] [blame] | 427 | config MIPS_L2_CACHE |
| 428 | bool |
| 429 | help |
| 430 | Select this if your system includes an L2 cache and you want U-Boot |
| 431 | to initialise & maintain it. |
| 432 | |
Paul Burton | 05e3425 | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 433 | config DYNAMIC_IO_PORT_BASE |
| 434 | bool |
| 435 | |
Paul Burton | b2b135d | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 436 | config MIPS_CM |
| 437 | bool |
| 438 | help |
| 439 | Select this if your system contains a MIPS Coherence Manager and you |
| 440 | wish U-Boot to configure it or make use of it to retrieve system |
| 441 | information such as cache configuration. |
| 442 | |
Daniel Schwierzeck | d1c3d8b | 2018-09-07 19:18:44 +0200 | [diff] [blame] | 443 | config MIPS_INSERT_BOOT_CONFIG |
| 444 | bool |
| 445 | default n |
| 446 | help |
| 447 | Enable this to insert some board-specific boot configuration in |
| 448 | the U-Boot binary at offset 0x10. |
| 449 | |
| 450 | config MIPS_BOOT_CONFIG_WORD0 |
| 451 | hex |
| 452 | depends on MIPS_INSERT_BOOT_CONFIG |
| 453 | default 0x420 if TARGET_MALTA |
| 454 | default 0x0 |
| 455 | help |
| 456 | Value which is inserted as boot config word 0. |
| 457 | |
| 458 | config MIPS_BOOT_CONFIG_WORD1 |
| 459 | hex |
| 460 | depends on MIPS_INSERT_BOOT_CONFIG |
| 461 | default 0x0 |
| 462 | help |
| 463 | Value which is inserted as boot config word 1. |
| 464 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 465 | endif |
| 466 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 467 | endmenu |