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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bd933bfd834364bca6cc6f3a62e4255090a5bec1 / . / arch / sandbox / dts / test.dts
blob: 347ea79077dfa358c060a88cbfa59331d5ba4e0b [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassce6d99a2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré23f965a2019-10-07 15:29:05 +0200[diff] [blame]79 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]83 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]84 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]85 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]86 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]87 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]88 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]89 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700[diff] [blame]94 int-value = <1234>;
95 uint-value = <(-1234)>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]96 };
97
98 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]99 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]100 compatible = "not,compatible";
101 };
102
103 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]104 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]105 };
106
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]107 backlight: backlight {
108 compatible = "pwm-backlight";
109 enable-gpios = <&gpio_a 1>;
110 power-supply = <&ldo_1>;
111 pwms = <&pwm 0 1000>;
112 default-brightness-level = <5>;
113 brightness-levels = <0 16 32 64 128 170 202 234 255>;
114 };
115
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]116 bind-test {
117 bind-test-child1 {
118 compatible = "sandbox,phy";
119 #phy-cells = <1>;
120 };
121
122 bind-test-child2 {
123 compatible = "simple-bus";
124 };
125 };
126
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]127 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]128 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]129 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]130 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]131 ping-add = <3>;
132 };
133
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]134 phy_provider0: gen_phy@0 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 phy_provider1: gen_phy@1 {
140 compatible = "sandbox,phy";
141 #phy-cells = <0>;
142 broken;
143 };
144
145 gen_phy_user: gen_phy_user {
146 compatible = "simple-bus";
147 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
148 phy-names = "phy1", "phy2", "phy3";
149 };
150
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]151 some-bus {
152 #address-cells = <1>;
153 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]154 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]155 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]156 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]157 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]158 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]159 compatible = "denx,u-boot-fdt-test";
160 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]161 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]162 ping-add = <5>;
163 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]164 c-test@0 {
165 compatible = "denx,u-boot-fdt-test";
166 reg = <0>;
167 ping-expect = <6>;
168 ping-add = <6>;
169 };
170 c-test@1 {
171 compatible = "denx,u-boot-fdt-test";
172 reg = <1>;
173 ping-expect = <7>;
174 ping-add = <7>;
175 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]176 };
177
178 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]179 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]180 ping-expect = <6>;
181 ping-add = <6>;
182 compatible = "google,another-fdt-test";
183 };
184
185 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]186 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]187 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]188 ping-add = <6>;
189 compatible = "google,another-fdt-test";
190 };
191
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]192 f-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
196 g-test {
197 compatible = "denx,u-boot-fdt-test";
198 };
199
Bin Meng2786cd72018-10-10 22:07:01 -0700[diff] [blame]200 h-test {
201 compatible = "denx,u-boot-fdt-test1";
202 };
203
Simon Glassdc12ebb2019-12-29 21:19:25 -0700[diff] [blame]204 devres-test {
205 compatible = "denx,u-boot-devres-test";
206 };
207
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]208 clocks {
209 clk_fixed: clk-fixed {
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <1234>;
213 };
Anup Patelb630d572019-02-25 08:14:55 +0000[diff] [blame]214
215 clk_fixed_factor: clk-fixed-factor {
216 compatible = "fixed-factor-clock";
217 #clock-cells = <0>;
218 clock-div = <3>;
219 clock-mult = <2>;
220 clocks = <&clk_fixed>;
221 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200[diff] [blame]222
223 osc {
224 compatible = "fixed-clock";
225 #clock-cells = <0>;
226 clock-frequency = <20000000>;
227 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]228 };
229
230 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]231 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]232 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200[diff] [blame]233 assigned-clocks = <&clk_sandbox 3>;
234 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]235 };
236
237 clk-test {
238 compatible = "sandbox,clk-test";
239 clocks = <&clk_fixed>,
240 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200[diff] [blame]241 <&clk_sandbox 0>,
242 <&clk_sandbox 3>,
243 <&clk_sandbox 2>;
244 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]245 };
246
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200[diff] [blame]247 ccf: clk-ccf {
248 compatible = "sandbox,clk-ccf";
249 };
250
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]251 eth@10002000 {
252 compatible = "sandbox,eth";
253 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]254 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]255 };
256
257 eth_5: eth@10003000 {
258 compatible = "sandbox,eth";
259 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]260 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]261 };
262
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]263 eth_3: sbe5 {
264 compatible = "sandbox,eth";
265 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]266 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]267 };
268
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]269 eth@10004000 {
270 compatible = "sandbox,eth";
271 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]272 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]273 };
274
Rajan Vaja31b82172018-09-19 03:43:46 -0700[diff] [blame]275 firmware {
276 sandbox_firmware: sandbox-firmware {
277 compatible = "sandbox,firmware";
278 };
279 };
280
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]281 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]282 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]283 gpio-controller;
284 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]285 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]286 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]287 };
288
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]289 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]290 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]291 gpio-controller;
292 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]293 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]294 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]295 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]296
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]297 i2c@0 {
298 #address-cells = <1>;
299 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]300 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]301 compatible = "sandbox,i2c";
302 clock-frequency = <100000>;
303 eeprom@2c {
304 reg = <0x2c>;
305 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]306 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]307 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]308
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]309 rtc_0: rtc@43 {
310 reg = <0x43>;
311 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]312 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]313 };
314
315 rtc_1: rtc@61 {
316 reg = <0x61>;
317 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]318 sandbox,emul = <&emul1>;
319 };
320
321 i2c_emul: emul {
322 reg = <0xff>;
323 compatible = "sandbox,i2c-emul-parent";
324 emul_eeprom: emul-eeprom {
325 compatible = "sandbox,i2c-eeprom";
326 sandbox,filename = "i2c.bin";
327 sandbox,size = <256>;
328 };
329 emul0: emul0 {
330 compatible = "sandbox,i2c-rtc";
331 };
332 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]333 compatible = "sandbox,i2c-rtc";
334 };
335 };
336
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]337 sandbox_pmic: sandbox_pmic {
338 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]339 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]340 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]341
342 mc34708: pmic@41 {
343 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]344 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]345 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]346 };
347
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100[diff] [blame]348 bootcount@0 {
349 compatible = "u-boot,bootcount-rtc";
350 rtc = <&rtc_1>;
351 offset = <0x13>;
352 };
353
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]354 adc@0 {
355 compatible = "sandbox,adc";
356 vdd-supply = <&buck2>;
357 vss-microvolts = <0>;
358 };
359
Simon Glassfbb0efd2019-12-06 21:41:59 -0700[diff] [blame]360 irq {
361 compatible = "sandbox,irq";
362 };
363
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]364 lcd {
365 u-boot,dm-pre-reloc;
366 compatible = "sandbox,lcd-sdl";
367 xres = <1366>;
368 yres = <768>;
369 };
370
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]371 leds {
372 compatible = "gpio-leds";
373
374 iracibble {
375 gpios = <&gpio_a 1 0>;
376 label = "sandbox:red";
377 };
378
379 martinet {
380 gpios = <&gpio_a 2 0>;
381 label = "sandbox:green";
382 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]383
384 default_on {
385 gpios = <&gpio_a 5 0>;
386 label = "sandbox:default_on";
387 default-state = "on";
388 };
389
390 default_off {
391 gpios = <&gpio_a 6 0>;
392 label = "sandbox:default_off";
393 default-state = "off";
394 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]395 };
396
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]397 mbox: mbox {
398 compatible = "sandbox,mbox";
399 #mbox-cells = <1>;
400 };
401
402 mbox-test {
403 compatible = "sandbox,mbox-test";
404 mboxes = <&mbox 100>, <&mbox 1>;
405 mbox-names = "other", "test";
406 };
407
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]408 cpus {
409 cpu-test1 {
410 compatible = "sandbox,cpu_sandbox";
411 u-boot,dm-pre-reloc;
412 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]413
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]414 cpu-test2 {
415 compatible = "sandbox,cpu_sandbox";
416 u-boot,dm-pre-reloc;
417 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]418
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]419 cpu-test3 {
420 compatible = "sandbox,cpu_sandbox";
421 u-boot,dm-pre-reloc;
422 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]423 };
424
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]425 i2s: i2s {
426 compatible = "sandbox,i2s";
427 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700[diff] [blame]428 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]429 };
430
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200[diff] [blame]431 nop-test_0 {
432 compatible = "sandbox,nop_sandbox1";
433 nop-test_1 {
434 compatible = "sandbox,nop_sandbox2";
435 bind = "True";
436 };
437 nop-test_2 {
438 compatible = "sandbox,nop_sandbox2";
439 bind = "False";
440 };
441 };
442
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]443 misc-test {
444 compatible = "sandbox,misc_sandbox";
445 };
446
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]447 mmc2 {
448 compatible = "sandbox,mmc";
449 };
450
451 mmc1 {
452 compatible = "sandbox,mmc";
453 };
454
455 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]456 compatible = "sandbox,mmc";
457 };
458
Simon Glassb45c8332019-02-16 20:24:50 -0700[diff] [blame]459 pch {
460 compatible = "sandbox,pch";
461 };
462
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]463 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]464 compatible = "sandbox,pci";
465 device_type = "pci";
466 #address-cells = <3>;
467 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600[diff] [blame]468 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]469 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]470 pci@0,0 {
471 compatible = "pci-generic";
472 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]473 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]474 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300[diff] [blame]475 pci@1,0 {
476 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600[diff] [blame]477 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
478 reg = <0x02000814 0 0 0 0
479 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]480 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300[diff] [blame]481 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700[diff] [blame]482 p2sb-pci@2,0 {
483 compatible = "sandbox,p2sb";
484 reg = <0x02001010 0 0 0 0>;
485 sandbox,emul = <&p2sb_emul>;
486
487 adder {
488 intel,p2sb-port-id = <3>;
489 compatible = "sandbox,adder";
490 };
491 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700[diff] [blame]492 pci@1e,0 {
493 compatible = "sandbox,pmc";
494 reg = <0xf000 0 0 0 0>;
495 sandbox,emul = <&pmc_emul1e>;
496 acpi-base = <0x400>;
497 gpe0-dwx-mask = <0xf>;
498 gpe0-dwx-shift-base = <4>;
499 gpe0-dw = <6 7 9>;
500 gpe0-sts = <0x20>;
501 gpe0-en = <0x30>;
502 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]503 pci@1f,0 {
504 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600[diff] [blame]505 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
506 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]507 sandbox,emul = <&swap_case_emul0_1f>;
508 };
509 };
510
511 pci-emul0 {
512 compatible = "sandbox,pci-emul-parent";
513 swap_case_emul0_0: emul0@0,0 {
514 compatible = "sandbox,swap-case";
515 };
516 swap_case_emul0_1: emul0@1,0 {
517 compatible = "sandbox,swap-case";
518 use-ea;
519 };
520 swap_case_emul0_1f: emul0@1f,0 {
521 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]522 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700[diff] [blame]523 p2sb_emul: emul@2,0 {
524 compatible = "sandbox,p2sb-emul";
525 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700[diff] [blame]526 pmc_emul1e: emul@1e,0 {
527 compatible = "sandbox,pmc-emul";
528 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]529 };
530
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]531 pci1: pci-controller1 {
532 compatible = "sandbox,pci";
533 device_type = "pci";
534 #address-cells = <3>;
535 #size-cells = <2>;
536 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
537 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]538 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200[diff] [blame]539 0x0c 0x00 0x1234 0x5678
540 0x10 0x00 0x1234 0x5678>;
541 pci@10,0 {
542 reg = <0x8000 0 0 0 0>;
543 };
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]544 };
545
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]546 pci2: pci-controller2 {
547 compatible = "sandbox,pci";
548 device_type = "pci";
549 #address-cells = <3>;
550 #size-cells = <2>;
551 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
552 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
553 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
554 pci@1f,0 {
555 compatible = "pci-generic";
556 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]557 sandbox,emul = <&swap_case_emul2_1f>;
558 };
559 };
560
561 pci-emul2 {
562 compatible = "sandbox,pci-emul-parent";
563 swap_case_emul2_1f: emul2@1f,0 {
564 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]565 };
566 };
567
Ramon Friedbb413332019-04-27 11:15:23 +0300[diff] [blame]568 pci_ep: pci_ep {
569 compatible = "sandbox,pci_ep";
570 };
571
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]572 probing {
573 compatible = "simple-bus";
574 test1 {
575 compatible = "denx,u-boot-probe-test";
576 };
577
578 test2 {
579 compatible = "denx,u-boot-probe-test";
580 };
581
582 test3 {
583 compatible = "denx,u-boot-probe-test";
584 };
585
586 test4 {
587 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]588 first-syscon = <&syscon0>;
589 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100[diff] [blame]590 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]591 };
592 };
593
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]594 pwrdom: power-domain {
595 compatible = "sandbox,power-domain";
596 #power-domain-cells = <1>;
597 };
598
599 power-domain-test {
600 compatible = "sandbox,power-domain-test";
601 power-domains = <&pwrdom 2>;
602 };
603
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]604 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]605 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]606 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]607 };
608
609 pwm2 {
610 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]611 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]612 };
613
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]614 ram {
615 compatible = "sandbox,ram";
616 };
617
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]618 reset@0 {
619 compatible = "sandbox,warm-reset";
620 };
621
622 reset@1 {
623 compatible = "sandbox,reset";
624 };
625
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]626 resetc: reset-ctl {
627 compatible = "sandbox,reset-ctl";
628 #reset-cells = <1>;
629 };
630
631 reset-ctl-test {
632 compatible = "sandbox,reset-ctl-test";
633 resets = <&resetc 100>, <&resetc 2>;
634 reset-names = "other", "test";
635 };
636
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530[diff] [blame]637 rng {
638 compatible = "sandbox,sandbox-rng";
639 };
640
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]641 rproc_1: rproc@1 {
642 compatible = "sandbox,test-processor";
643 remoteproc-name = "remoteproc-test-dev1";
644 };
645
646 rproc_2: rproc@2 {
647 compatible = "sandbox,test-processor";
648 internal-memory-mapped;
649 remoteproc-name = "remoteproc-test-dev2";
650 };
651
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]652 panel {
653 compatible = "simple-panel";
654 backlight = <&backlight 0 100>;
655 };
656
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]657 smem@0 {
658 compatible = "sandbox,smem";
659 };
660
Simon Glassd4901892018-12-10 10:37:36 -0700[diff] [blame]661 sound {
662 compatible = "sandbox,sound";
663 cpu {
664 sound-dai = <&i2s 0>;
665 };
666
667 codec {
668 sound-dai = <&audio 0>;
669 };
670 };
671
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]672 spi@0 {
673 #address-cells = <1>;
674 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]675 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]676 compatible = "sandbox,spi";
677 cs-gpios = <0>, <&gpio_a 0>;
678 spi.bin@0 {
679 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000[diff] [blame]680 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]681 spi-max-frequency = <40000000>;
682 sandbox,filename = "spi.bin";
683 };
684 };
685
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]686 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]687 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200[diff] [blame]688 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]689 };
690
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]691 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]692 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]693 reg = <0x20 5
694 0x28 6
695 0x30 7
696 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]697 };
698
Patrick Delaunaya442e612019-03-07 09:57:13 +0100[diff] [blame]699 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]700 compatible = "simple-mfd", "syscon";
701 reg = <0x40 5
702 0x48 6
703 0x50 7
704 0x58 8>;
705 };
706
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]707 timer {
708 compatible = "sandbox,timer";
709 clock-frequency = <1000000>;
710 };
711
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]712 tpm2 {
713 compatible = "sandbox,tpm2";
714 };
715
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]716 uart0: serial {
717 compatible = "sandbox,serial";
718 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]719 };
720
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]721 usb_0: usb@0 {
722 compatible = "sandbox,usb";
723 status = "disabled";
724 hub {
725 compatible = "sandbox,usb-hub";
726 #address-cells = <1>;
727 #size-cells = <0>;
728 flash-stick {
729 reg = <0>;
730 compatible = "sandbox,usb-flash";
731 };
732 };
733 };
734
735 usb_1: usb@1 {
736 compatible = "sandbox,usb";
737 hub {
738 compatible = "usb-hub";
739 usb,device-class = <9>;
740 hub-emul {
741 compatible = "sandbox,usb-hub";
742 #address-cells = <1>;
743 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]744 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]745 reg = <0>;
746 compatible = "sandbox,usb-flash";
747 sandbox,filepath = "testflash.bin";
748 };
749
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]750 flash-stick@1 {
751 reg = <1>;
752 compatible = "sandbox,usb-flash";
753 sandbox,filepath = "testflash1.bin";
754 };
755
756 flash-stick@2 {
757 reg = <2>;
758 compatible = "sandbox,usb-flash";
759 sandbox,filepath = "testflash2.bin";
760 };
761
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]762 keyb@3 {
763 reg = <3>;
764 compatible = "sandbox,usb-keyb";
765 };
766
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]767 };
768 };
769 };
770
771 usb_2: usb@2 {
772 compatible = "sandbox,usb";
773 status = "disabled";
774 };
775
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]776 spmi: spmi@0 {
777 compatible = "sandbox,spmi";
778 #address-cells = <0x1>;
779 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600[diff] [blame]780 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]781 pm8916@0 {
782 compatible = "qcom,spmi-pmic";
783 reg = <0x0 0x1>;
784 #address-cells = <0x1>;
785 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600[diff] [blame]786 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]787
788 spmi_gpios: gpios@c000 {
789 compatible = "qcom,pm8916-gpio";
790 reg = <0xc000 0x400>;
791 gpio-controller;
792 gpio-count = <4>;
793 #gpio-cells = <2>;
794 gpio-bank-name="spmi";
795 };
796 };
797 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]798
799 wdt0: wdt@0 {
800 compatible = "sandbox,wdt";
801 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]802
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]803 axi: axi@0 {
804 compatible = "sandbox,axi";
805 #address-cells = <0x1>;
806 #size-cells = <0x1>;
807 store@0 {
808 compatible = "sandbox,sandbox_store";
809 reg = <0x0 0x400>;
810 };
811 };
812
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]813 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]814 #address-cells = <1>;
815 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -0700[diff] [blame]816 setting = "sunrise ohoka";
817 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -0700[diff] [blame^]818 int-values = <0x1937 72993>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]819 chosen-test {
820 compatible = "denx,u-boot-fdt-test";
821 reg = <9 1>;
822 };
823 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]824
825 translation-test@8000 {
826 compatible = "simple-bus";
827 reg = <0x8000 0x4000>;
828
829 #address-cells = <0x2>;
830 #size-cells = <0x1>;
831
832 ranges = <0 0x0 0x8000 0x1000
833 1 0x100 0x9000 0x1000
834 2 0x200 0xA000 0x1000
835 3 0x300 0xB000 0x1000
836 >;
837
Fabien Dessenne641067f2019-05-31 15:11:30 +0200[diff] [blame]838 dma-ranges = <0 0x000 0x10000000 0x1000
839 1 0x100 0x20000000 0x1000
840 >;
841
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]842 dev@0,0 {
843 compatible = "denx,u-boot-fdt-dummy";
844 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100[diff] [blame]845 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]846 };
847
848 dev@1,100 {
849 compatible = "denx,u-boot-fdt-dummy";
850 reg = <1 0x100 0x1000>;
851
852 };
853
854 dev@2,200 {
855 compatible = "denx,u-boot-fdt-dummy";
856 reg = <2 0x200 0x1000>;
857 };
858
859
860 noxlatebus@3,300 {
861 compatible = "simple-bus";
862 reg = <3 0x300 0x1000>;
863
864 #address-cells = <0x1>;
865 #size-cells = <0x0>;
866
867 dev@42 {
868 compatible = "denx,u-boot-fdt-dummy";
869 reg = <0x42>;
870 };
871 };
872 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]873
874 osd {
875 compatible = "sandbox,sandbox_osd";
876 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400[diff] [blame]877
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]878 board {
879 compatible = "sandbox,board_sandbox";
880 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200[diff] [blame]881
882 sandbox_tee {
883 compatible = "sandbox,tee";
884 };
Bin Meng4f89d492018-10-15 02:21:26 -0700[diff] [blame]885
886 sandbox_virtio1 {
887 compatible = "sandbox,virtio1";
888 };
889
890 sandbox_virtio2 {
891 compatible = "sandbox,virtio2";
892 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200[diff] [blame]893
894 pinctrl {
895 compatible = "sandbox,pinctrl";
896 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +0100[diff] [blame]897
898 hwspinlock@0 {
899 compatible = "sandbox,hwspinlock";
900 };
Grygorii Strashkob3309912018-11-28 19:17:51 +0100[diff] [blame]901
902 dma: dma {
903 compatible = "sandbox,dma";
904 #dma-cells = <1>;
905
906 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
907 dma-names = "m2m", "tx0", "rx0";
908 };
Alex Margineanec9594a2019-06-03 19:12:28 +0300[diff] [blame]909
Alex Margineanc3d9f3f2019-07-12 10:13:53 +0300[diff] [blame]910 /*
911 * keep mdio-mux ahead of mdio so that the mux is removed first at the
912 * end of the test. If parent mdio is removed first, clean-up of the
913 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
914 * active at the end of the test. That it turn doesn't allow the mdio
915 * class to be destroyed, triggering an error.
916 */
917 mdio-mux-test {
918 compatible = "sandbox,mdio-mux";
919 #address-cells = <1>;
920 #size-cells = <0>;
921 mdio-parent-bus = <&mdio>;
922
923 mdio-ch-test@0 {
924 reg = <0>;
925 };
926 mdio-ch-test@1 {
927 reg = <1>;
928 };
929 };
930
931 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +0300[diff] [blame]932 compatible = "sandbox,mdio";
933 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]934};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]935
936#include "sandbox_pmic.dtsi"