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Bin Meng117a4332018-09-26 06:55:06 -07001menu "RISC-V architecture"
Rick Chenf94c44e2017-12-26 13:55:52 +08002 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
Rick Chen6f4dd622018-05-29 09:54:40 +080011config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
Rick Chenf94c44e2017-12-26 13:55:52 +080013
Padmarao Begari39494822019-05-28 15:47:51 +053014config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
16
Bin Meng510e3792018-09-26 06:55:21 -070017config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
19
Bin Mengae2d9502021-03-17 11:10:58 +080020config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
Anup Patel3fda0262019-02-25 08:15:19 +000022
Green Wan70415e12021-05-27 06:52:13 -070023config TARGET_SIFIVE_UNMATCHED
24 bool "Support SiFive Unmatched Board"
Tom Riniab92b382021-08-26 11:47:59 -040025 select SYS_CACHE_SHIFT_6
Green Wan70415e12021-05-27 06:52:13 -070026
Sean Andersona7c81fc2020-06-24 06:41:25 -040027config TARGET_SIPEED_MAIX
28 bool "Support Sipeed Maix Board"
Tom Riniab92b382021-08-26 11:47:59 -040029 select SYS_CACHE_SHIFT_6
Sean Andersona7c81fc2020-06-24 06:41:25 -040030
Tianrui Wei8a44fe62021-07-01 12:54:19 +080031config TARGET_OPENPITON_RISCV64
32 bool "Support RISC-V cores on OpenPiton SoC"
33
Rick Chenf94c44e2017-12-26 13:55:52 +080034endchoice
35
Trevor Woernera0aba8a2019-05-03 09:40:59 -040036config SYS_ICACHE_OFF
37 bool "Do not enable icache"
Trevor Woernera0aba8a2019-05-03 09:40:59 -040038 help
39 Do not enable instruction cache in U-Boot.
40
Trevor Woerner10015022019-05-03 09:41:00 -040041config SPL_SYS_ICACHE_OFF
42 bool "Do not enable icache in SPL"
43 depends on SPL
44 default SYS_ICACHE_OFF
45 help
46 Do not enable instruction cache in SPL.
47
Trevor Woernera0aba8a2019-05-03 09:40:59 -040048config SYS_DCACHE_OFF
49 bool "Do not enable dcache"
Trevor Woernera0aba8a2019-05-03 09:40:59 -040050 help
51 Do not enable data cache in U-Boot.
52
Trevor Woerner10015022019-05-03 09:41:00 -040053config SPL_SYS_DCACHE_OFF
54 bool "Do not enable dcache in SPL"
55 depends on SPL
56 default SYS_DCACHE_OFF
57 help
58 Do not enable data cache in SPL.
59
Rick Chen52923c62018-11-07 09:34:06 +080060# board-specific options below
Rick Chen6f4dd622018-05-29 09:54:40 +080061source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng510e3792018-09-26 06:55:21 -070062source "board/emulation/qemu-riscv/Kconfig"
Padmarao Begari39494822019-05-28 15:47:51 +053063source "board/microchip/mpfs_icicle/Kconfig"
Bin Mengae2d9502021-03-17 11:10:58 +080064source "board/sifive/unleashed/Kconfig"
Green Wan70415e12021-05-27 06:52:13 -070065source "board/sifive/unmatched/Kconfig"
Tianrui Wei8a44fe62021-07-01 12:54:19 +080066source "board/openpiton/riscv64/Kconfig"
Sean Andersona7c81fc2020-06-24 06:41:25 -040067source "board/sipeed/maix/Kconfig"
Rick Chenf94c44e2017-12-26 13:55:52 +080068
Rick Chen52923c62018-11-07 09:34:06 +080069# platform-specific options below
70source "arch/riscv/cpu/ax25/Kconfig"
Pragnesh Patel7c45fc92020-05-29 11:33:34 +053071source "arch/riscv/cpu/fu540/Kconfig"
Green Wana74e9d82021-05-27 06:52:07 -070072source "arch/riscv/cpu/fu740/Kconfig"
Anup Patelfdff1f92019-02-25 08:14:10 +000073source "arch/riscv/cpu/generic/Kconfig"
Rick Chen52923c62018-11-07 09:34:06 +080074
75# architecture-specific options below
76
Rick Chenf94c44e2017-12-26 13:55:52 +080077choice
Lukas Auer862e2e72018-11-22 11:26:12 +010078 prompt "Base ISA"
79 default ARCH_RV32I
Rick Chenf94c44e2017-12-26 13:55:52 +080080
Lukas Auer862e2e72018-11-22 11:26:12 +010081config ARCH_RV32I
82 bool "RV32I"
Rick Chenf94c44e2017-12-26 13:55:52 +080083 select 32BIT
84 help
Lukas Auer862e2e72018-11-22 11:26:12 +010085 Choose this option to target the RV32I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +080086
Lukas Auer862e2e72018-11-22 11:26:12 +010087config ARCH_RV64I
88 bool "RV64I"
Rick Chenf94c44e2017-12-26 13:55:52 +080089 select 64BIT
Lukas Auer71158562018-11-22 11:26:13 +010090 select PHYS_64BIT
Rick Chenf94c44e2017-12-26 13:55:52 +080091 help
Lukas Auer862e2e72018-11-22 11:26:12 +010092 Choose this option to target the RV64I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +080093
94endchoice
95
Lukas Auer8176ea42018-12-12 06:12:23 -080096choice
97 prompt "Code Model"
98 default CMODEL_MEDLOW
99
100config CMODEL_MEDLOW
101 bool "medium low code model"
102 help
103 U-Boot and its statically defined symbols must lie within a single 2 GiB
104 address range and must lie between absolute addresses -2 GiB and +2 GiB.
105
106config CMODEL_MEDANY
107 bool "medium any code model"
108 help
109 U-Boot and its statically defined symbols must be within any single 2 GiB
110 address range.
111
112endchoice
113
Anup Patel3cfc8252018-12-12 06:12:29 -0800114choice
115 prompt "Run Mode"
116 default RISCV_MMODE
117
118config RISCV_MMODE
119 bool "Machine"
120 help
121 Choose this option to build U-Boot for RISC-V M-Mode.
122
123config RISCV_SMODE
124 bool "Supervisor"
125 help
126 Choose this option to build U-Boot for RISC-V S-Mode.
127
128endchoice
129
Lukas Auerfbfd92b2019-08-21 21:14:43 +0200130choice
131 prompt "SPL Run Mode"
132 default SPL_RISCV_MMODE
133 depends on SPL
134
135config SPL_RISCV_MMODE
136 bool "Machine"
137 help
138 Choose this option to build U-Boot SPL for RISC-V M-Mode.
139
140config SPL_RISCV_SMODE
141 bool "Supervisor"
142 help
143 Choose this option to build U-Boot SPL for RISC-V S-Mode.
144
145endchoice
146
Lukas Auerd57ffa62018-11-22 11:26:14 +0100147config RISCV_ISA_C
148 bool "Emit compressed instructions"
149 default y
150 help
151 Adds "C" to the ISA subsets that the toolchain is allowed to emit
152 when building U-Boot, which results in compressed instructions in the
153 U-Boot binary.
154
155config RISCV_ISA_A
156 def_bool y
157
Rick Chenf94c44e2017-12-26 13:55:52 +0800158config 32BIT
159 bool
160
161config 64BIT
162 bool
163
Padmarao Begari5af35742021-01-15 08:20:35 +0530164config DMA_ADDR_T_64BIT
165 bool
166 default y if 64BIT
167
Bin Meng644a3cd2018-12-12 06:12:30 -0800168config SIFIVE_CLINT
169 bool
Bin Menga6d7e8c2021-05-11 20:04:12 +0800170 depends on RISCV_MMODE
171 help
172 The SiFive CLINT block holds memory-mapped control and status registers
173 associated with software and timer interrupts.
174
175config SPL_SIFIVE_CLINT
176 bool
177 depends on SPL_RISCV_MMODE
Bin Meng644a3cd2018-12-12 06:12:30 -0800178 help
179 The SiFive CLINT block holds memory-mapped control and status registers
180 associated with software and timer interrupts.
181
Zong Li213ed172021-09-01 15:01:41 +0800182config SIFIVE_CACHE
183 bool
184 help
185 This enables the operations to configure SiFive cache
186
Rick Chen0d389462019-04-02 15:56:39 +0800187config ANDES_PLIC
188 bool
Lukas Auerfbfd92b2019-08-21 21:14:43 +0200189 depends on RISCV_MMODE || SPL_RISCV_MMODE
Rick Chen0d389462019-04-02 15:56:39 +0800190 select REGMAP
191 select SYSCON
Lukas Auerfbfd92b2019-08-21 21:14:43 +0200192 select SPL_REGMAP if SPL
193 select SPL_SYSCON if SPL
Rick Chen0d389462019-04-02 15:56:39 +0800194 help
195 The Andes PLIC block holds memory-mapped claim and pending registers
196 associated with software interrupt.
197
Lukas Auerfa33f082019-03-17 19:28:32 +0100198config SMP
199 bool "Symmetric Multi-Processing"
Bin Meng6fa022e2020-04-16 08:09:31 -0700200 depends on SBI_V01 || !RISCV_SMODE
Lukas Auerfa33f082019-03-17 19:28:32 +0100201 help
202 This enables support for systems with more than one CPU. If
203 you say N here, U-Boot will run on single and multiprocessor
204 machines, but will use only one CPU of a multiprocessor
205 machine. If you say Y here, U-Boot will run on many, but not
206 all, single processor machines.
207
Bin Meng191636e2020-04-16 08:09:30 -0700208config SPL_SMP
209 bool "Symmetric Multi-Processing in SPL"
210 depends on SPL && SPL_RISCV_MMODE
211 default y
212 help
213 This enables support for systems with more than one CPU in SPL.
214 If you say N here, U-Boot SPL will run on single and multiprocessor
215 machines, but will use only one CPU of a multiprocessor
216 machine. If you say Y here, U-Boot SPL will run on many, but not
217 all, single processor machines.
218
Lukas Auerfa33f082019-03-17 19:28:32 +0100219config NR_CPUS
220 int "Maximum number of CPUs (2-32)"
221 range 2 32
Bin Meng191636e2020-04-16 08:09:30 -0700222 depends on SMP || SPL_SMP
Lukas Auerfa33f082019-03-17 19:28:32 +0100223 default 8
224 help
225 On multiprocessor machines, U-Boot sets up a stack for each CPU.
226 Stack memory is pre-allocated. U-Boot must therefore know the
227 maximum number of CPUs that may be present.
228
Bin Mengf58fc342020-03-09 19:35:28 -0700229config SBI
230 bool
231 default y if RISCV_SMODE || SPL_RISCV_SMODE
232
Bin Mengff0fa6c2020-04-16 08:09:32 -0700233choice
234 prompt "SBI support"
Bin Mengfa16ec22020-04-16 08:09:33 -0700235 default SBI_V02
Bin Mengff0fa6c2020-04-16 08:09:32 -0700236
Bin Meng1b3c8d62020-03-09 19:35:30 -0700237config SBI_V01
238 bool "SBI v0.1 support"
Bin Meng1b3c8d62020-03-09 19:35:30 -0700239 depends on SBI
240 help
241 This config allows kernel to use SBI v0.1 APIs. This will be
242 deprecated in future once legacy M-mode software are no longer in use.
243
Bin Mengff0fa6c2020-04-16 08:09:32 -0700244config SBI_V02
245 bool "SBI v0.2 support"
246 depends on SBI
247 help
248 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
249 scalable and extendable to handle future needs for RISC-V supervisor
250 interfaces. For example, with SBI v0.2 HSM extension, only a single
251 hart need to boot and enter operating system. The booting hart can
252 bring up secondary harts one by one afterwards.
253
254 Choose this option if OpenSBI v0.7 or above release is used together
255 with U-Boot.
256
257endchoice
258
Lukas Auerf152feb2019-03-17 19:28:34 +0100259config SBI_IPI
260 bool
Bin Mengf58fc342020-03-09 19:35:28 -0700261 depends on SBI
Lukas Auerfbfd92b2019-08-21 21:14:43 +0200262 default y if RISCV_SMODE || SPL_RISCV_SMODE
Lukas Auerf152feb2019-03-17 19:28:34 +0100263 depends on SMP
264
Rick Chenbdce3892019-04-30 13:49:33 +0800265config XIP
266 bool "XIP mode"
267 help
268 XIP (eXecute In Place) is a method for executing code directly
269 from a NOR flash memory without copying the code to ram.
270 Say yes here if U-Boot boots from flash directly.
271
Nikita Shubinc2bdf022022-09-02 11:47:39 +0300272config SPL_XIP
273 bool "Enable XIP mode for SPL"
274 help
275 If SPL starts in read-only memory (XIP for example) then we shouldn't
276 rely on lock variables (for example hart_lottery and available_harts_lock),
277 this affects only SPL, other stages should proceed as non-XIP.
278
Sean Andersonfd1f6e92019-12-25 00:27:44 -0500279config SHOW_REGS
280 bool "Show registers on unhandled exception"
281
Sean Andersonb8bc1202020-06-24 06:41:19 -0400282config RISCV_PRIV_1_9
283 bool "Use version 1.9 of the RISC-V priviledged specification"
284 help
285 Older versions of the RISC-V priviledged specification had
286 separate counter enable CSRs for each privilege mode. Writing
287 to the unified mcounteren CSR on a processor implementing the
288 old specification will result in an illegal instruction
289 exception. In addition to counter CSR changes, the way virtual
290 memory is configured was also changed.
291
Lukas Auer3dea63c2019-03-17 19:28:37 +0100292config STACK_SIZE_SHIFT
293 int
Lukas Auer6b20dc12019-10-20 20:53:47 +0200294 default 14
Lukas Auer3dea63c2019-03-17 19:28:37 +0100295
Bin Meng1c17e552020-06-25 18:16:08 -0700296config OF_BOARD_FIXUP
Sean Anderson32cef692020-09-05 09:22:11 -0400297 default y if OF_SEPARATE && RISCV_SMODE
Bin Meng1c17e552020-06-25 18:16:08 -0700298
Bin Meng89419272021-05-13 16:46:18 +0800299menu "Use assembly optimized implementation of memory routines"
300
Heinrich Schuchardt8f0dc4c2021-03-27 12:37:04 +0100301config USE_ARCH_MEMCPY
302 bool "Use an assembly optimized implementation of memcpy"
303 default y
304 help
305 Enable the generation of an optimized version of memcpy.
306 Such an implementation may be faster under some conditions
307 but may increase the binary size.
308
309config SPL_USE_ARCH_MEMCPY
310 bool "Use an assembly optimized implementation of memcpy for SPL"
311 default y if USE_ARCH_MEMCPY
312 depends on SPL
313 help
314 Enable the generation of an optimized version of memcpy.
315 Such an implementation may be faster under some conditions
316 but may increase the binary size.
317
318config TPL_USE_ARCH_MEMCPY
319 bool "Use an assembly optimized implementation of memcpy for TPL"
320 default y if USE_ARCH_MEMCPY
321 depends on TPL
322 help
323 Enable the generation of an optimized version of memcpy.
324 Such an implementation may be faster under some conditions
325 but may increase the binary size.
326
327config USE_ARCH_MEMMOVE
328 bool "Use an assembly optimized implementation of memmove"
329 default y
330 help
331 Enable the generation of an optimized version of memmove.
332 Such an implementation may be faster under some conditions
333 but may increase the binary size.
334
335config SPL_USE_ARCH_MEMMOVE
336 bool "Use an assembly optimized implementation of memmove for SPL"
337 default y if USE_ARCH_MEMCPY
338 depends on SPL
339 help
340 Enable the generation of an optimized version of memmove.
341 Such an implementation may be faster under some conditions
342 but may increase the binary size.
343
344config TPL_USE_ARCH_MEMMOVE
345 bool "Use an assembly optimized implementation of memmove for TPL"
346 default y if USE_ARCH_MEMCPY
347 depends on TPL
348 help
349 Enable the generation of an optimized version of memmove.
350 Such an implementation may be faster under some conditions
351 but may increase the binary size.
352
353config USE_ARCH_MEMSET
354 bool "Use an assembly optimized implementation of memset"
355 default y
356 help
357 Enable the generation of an optimized version of memset.
358 Such an implementation may be faster under some conditions
359 but may increase the binary size.
360
361config SPL_USE_ARCH_MEMSET
362 bool "Use an assembly optimized implementation of memset for SPL"
363 default y if USE_ARCH_MEMSET
364 depends on SPL
365 help
366 Enable the generation of an optimized version of memset.
367 Such an implementation may be faster under some conditions
368 but may increase the binary size.
369
370config TPL_USE_ARCH_MEMSET
371 bool "Use an assembly optimized implementation of memset for TPL"
372 default y if USE_ARCH_MEMSET
373 depends on TPL
374 help
375 Enable the generation of an optimized version of memset.
376 Such an implementation may be faster under some conditions
377 but may increase the binary size.
378
Rick Chenf94c44e2017-12-26 13:55:52 +0800379endmenu
Bin Meng89419272021-05-13 16:46:18 +0800380
381endmenu