blob: 94a4323f11314b835b79d0f9333941f1953e396a [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Simon Glass53b5bf32016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glass77d2f7f2016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glass1646eba2016-09-12 23:18:42 -06009config SPL_LIBDISK_SUPPORT
10 default y
11
Simon Glasscc4288e2016-09-12 23:18:43 -060012config SPL_LIBGENERIC_SUPPORT
13 default y
14
Simon Glass1fdf7c62016-09-12 23:18:44 -060015config SPL_MMC_SUPPORT
16 default y
17
Hans de Goede44d8ae52015-04-06 20:33:34 +020018# Note only one of these may be selected at a time! But hidden choices are
19# not supported by Kconfig
20config SUNXI_GEN_SUN4I
21 bool
22 ---help---
23 Select this for sunxi SoCs which have resets and clocks set up
24 as the original A10 (mach-sun4i).
25
26config SUNXI_GEN_SUN6I
27 bool
28 ---help---
29 Select this for sunxi SoCs which have sun6i like periphery, like
30 separate ahb reset control registers, custom pmic bus, new style
31 watchdog, etc.
32
33
Ian Campbell2c7e3b92014-10-24 21:20:44 +010034choice
35 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020036 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010037
Ian Campbellc3be2792014-10-24 21:20:45 +010038config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010039 bool "sun4i (Allwinner A10)"
40 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020041 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010042 select SUPPORT_SPL
43
Ian Campbellc3be2792014-10-24 21:20:45 +010044config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010045 bool "sun5i (Allwinner A13)"
46 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020047 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010048 select SUPPORT_SPL
49
Ian Campbellc3be2792014-10-24 21:20:45 +010050config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010051 bool "sun6i (Allwinner A31)"
52 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080053 select CPU_V7_HAS_NONSEC
54 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090055 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020056 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020057 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080058 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010059
Ian Campbellc3be2792014-10-24 21:20:45 +010060config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010061 bool "sun7i (Allwinner A20)"
62 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010063 select CPU_V7_HAS_NONSEC
64 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090065 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020066 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010067 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020068 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010069
Hans de Goede5e6bacd2015-04-06 20:55:39 +020070config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010071 bool "sun8i (Allwinner A23)"
72 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080073 select CPU_V7_HAS_NONSEC
74 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090075 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020076 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010077 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080078 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010079
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053080config MACH_SUN8I_A33
81 bool "sun8i (Allwinner A33)"
82 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080083 select CPU_V7_HAS_NONSEC
84 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090085 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053086 select SUNXI_GEN_SUN6I
87 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080088 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053089
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +080090config MACH_SUN8I_A83T
91 bool "sun8i (Allwinner A83T)"
92 select CPU_V7
93 select SUNXI_GEN_SUN6I
94 select SUPPORT_SPL
95
Jens Kuske1c27b7d2015-11-17 15:12:58 +010096config MACH_SUN8I_H3
97 bool "sun8i (Allwinner H3)"
98 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080099 select CPU_V7_HAS_NONSEC
100 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900101 select ARCH_SUPPORT_PSCI
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100102 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +0100103 select SUPPORT_SPL
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800104 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100105
Hans de Goede1871a8c2015-01-13 19:25:06 +0100106config MACH_SUN9I
107 bool "sun9i (Allwinner A80)"
108 select CPU_V7
109 select SUNXI_GEN_SUN6I
110
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800111config MACH_SUN50I
112 bool "sun50i (Allwinner A64)"
113 select ARM64
114 select SUNXI_GEN_SUN6I
115
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100116endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800117
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200118# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
119config MACH_SUN8I
120 bool
vishnupatekar762e24a2015-11-29 01:07:19 +0800121 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200122
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800123config DRAM_TYPE
124 int "sunxi dram type"
125 depends on MACH_SUN8I_A83T
126 default 3
127 ---help---
128 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200129
Hans de Goede37781a12014-11-15 19:46:39 +0100130config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100131 int "sunxi dram clock speed"
132 default 312 if MACH_SUN6I || MACH_SUN8I
133 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100134 ---help---
135 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +0100136 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +0100137
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200138if MACH_SUN5I || MACH_SUN7I
139config DRAM_MBUS_CLK
140 int "sunxi mbus clock speed"
141 default 300
142 ---help---
143 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
144
145endif
146
Hans de Goede37781a12014-11-15 19:46:39 +0100147config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100148 int "sunxi dram zq value"
149 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
150 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100151 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100152 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100153
Hans de Goede8975cdf2015-05-13 15:00:46 +0200154config DRAM_ODT_EN
155 bool "sunxi dram odt enable"
156 default n if !MACH_SUN8I_A23
157 default y if MACH_SUN8I_A23
158 ---help---
159 Select this to enable dram odt (on die termination).
160
Hans de Goede8ffc4872015-01-17 14:24:55 +0100161if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
162config DRAM_EMR1
163 int "sunxi dram emr1 value"
164 default 0 if MACH_SUN4I
165 default 4 if MACH_SUN5I || MACH_SUN7I
166 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100167 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200168
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200169config DRAM_TPR3
170 hex "sunxi dram tpr3 value"
171 default 0
172 ---help---
173 Set the dram controller tpr3 parameter. This parameter configures
174 the delay on the command lane and also phase shifts, which are
175 applied for sampling incoming read data. The default value 0
176 means that no phase/delay adjustments are necessary. Properly
177 configuring this parameter increases reliability at high DRAM
178 clock speeds.
179
180config DRAM_DQS_GATING_DELAY
181 hex "sunxi dram dqs_gating_delay value"
182 default 0
183 ---help---
184 Set the dram controller dqs_gating_delay parmeter. Each byte
185 encodes the DQS gating delay for each byte lane. The delay
186 granularity is 1/4 cycle. For example, the value 0x05060606
187 means that the delay is 5 quarter-cycles for one lane (1.25
188 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
189 The default value 0 means autodetection. The results of hardware
190 autodetection are not very reliable and depend on the chip
191 temperature (sometimes producing different results on cold start
192 and warm reboot). But the accuracy of hardware autodetection
193 is usually good enough, unless running at really high DRAM
194 clocks speeds (up to 600MHz). If unsure, keep as 0.
195
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200196choice
197 prompt "sunxi dram timings"
198 default DRAM_TIMINGS_VENDOR_MAGIC
199 ---help---
200 Select the timings of the DDR3 chips.
201
202config DRAM_TIMINGS_VENDOR_MAGIC
203 bool "Magic vendor timings from Android"
204 ---help---
205 The same DRAM timings as in the Allwinner boot0 bootloader.
206
207config DRAM_TIMINGS_DDR3_1066F_1333H
208 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
209 ---help---
210 Use the timings of the standard JEDEC DDR3-1066F speed bin for
211 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
212 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
213 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
214 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
215 that down binning to DDR3-1066F is supported (because DDR3-1066F
216 uses a bit faster timings than DDR3-1333H).
217
218config DRAM_TIMINGS_DDR3_800E_1066G_1333J
219 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
220 ---help---
221 Use the timings of the slowest possible JEDEC speed bin for the
222 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
223 DDR3-800E, DDR3-1066G or DDR3-1333J.
224
225endchoice
226
Hans de Goede37781a12014-11-15 19:46:39 +0100227endif
228
Hans de Goede8975cdf2015-05-13 15:00:46 +0200229if MACH_SUN8I_A23
230config DRAM_ODT_CORRECTION
231 int "sunxi dram odt correction value"
232 default 0
233 ---help---
234 Set the dram odt correction value (range -255 - 255). In allwinner
235 fex files, this option is found in bits 8-15 of the u32 odt_en variable
236 in the [dram] section. When bit 31 of the odt_en variable is set
237 then the correction is negative. Usually the value for this is 0.
238endif
239
Iain Patone71b4222015-03-28 10:26:38 +0000240config SYS_CLK_FREQ
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200241 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000242 default 912000000 if MACH_SUN7I
243 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
244
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800245config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100246 default "sun4i" if MACH_SUN4I
247 default "sun5i" if MACH_SUN5I
248 default "sun6i" if MACH_SUN6I
249 default "sun7i" if MACH_SUN7I
250 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100251 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200252 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200253
Masahiro Yamadadd840582014-07-30 14:08:14 +0900254config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900255 default "sunxi"
256
257config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900258 default "sunxi"
259
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200260config UART0_PORT_F
261 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200262 default n
263 ---help---
264 Repurpose the SD card slot for getting access to the UART0 serial
265 console. Primarily useful only for low level u-boot debugging on
266 tablets, where normal UART0 is difficult to access and requires
267 device disassembly and/or soldering. As the SD card can't be used
268 at the same time, the system can be only booted in the FEL mode.
269 Only enable this if you really know what you are doing.
270
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200271config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900272 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200273 default n
274 ---help---
275 Set this to enable various workarounds for old kernels, this results in
276 sub-optimal settings for newer kernels, only enable if needed.
277
Maxime Ripard44c79872015-10-15 22:04:07 +0200278config MMC
279 depends on !UART0_PORT_F
280 default y if ARCH_SUNXI
281
Hans de Goedecd821132014-10-02 20:29:26 +0200282config MMC0_CD_PIN
283 string "Card detect pin for mmc0"
Chen-Yu Tsaiacdab172016-05-02 10:28:08 +0800284 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200285 default ""
286 ---help---
287 Set the card detect pin for mmc0, leave empty to not use cd. This
288 takes a string in the format understood by sunxi_name_to_gpio, e.g.
289 PH1 for pin 1 of port H.
290
291config MMC1_CD_PIN
292 string "Card detect pin for mmc1"
293 default ""
294 ---help---
295 See MMC0_CD_PIN help text.
296
297config MMC2_CD_PIN
298 string "Card detect pin for mmc2"
299 default ""
300 ---help---
301 See MMC0_CD_PIN help text.
302
303config MMC3_CD_PIN
304 string "Card detect pin for mmc3"
305 default ""
306 ---help---
307 See MMC0_CD_PIN help text.
308
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100309config MMC1_PINS
310 string "Pins for mmc1"
311 default ""
312 ---help---
313 Set the pins used for mmc1, when applicable. This takes a string in the
314 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
315
316config MMC2_PINS
317 string "Pins for mmc2"
318 default ""
319 ---help---
320 See MMC1_PINS help text.
321
322config MMC3_PINS
323 string "Pins for mmc3"
324 default ""
325 ---help---
326 See MMC1_PINS help text.
327
Hans de Goede2ccfac02014-10-02 20:43:50 +0200328config MMC_SUNXI_SLOT_EXTRA
329 int "mmc extra slot number"
330 default -1
331 ---help---
332 sunxi builds always enable mmc0, some boards also have a second sdcard
333 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
334 support for this.
335
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200336config INITIAL_USB_SCAN_DELAY
337 int "delay initial usb scan by x ms to allow builtin devices to init"
338 default 0
339 ---help---
340 Some boards have on board usb devices which need longer than the
341 USB spec's 1 second to connect from board powerup. Set this config
342 option to a non 0 value to add an extra delay before the first usb
343 bus scan.
344
Hans de Goede4458b7a2015-01-07 15:26:06 +0100345config USB0_VBUS_PIN
346 string "Vbus enable pin for usb0 (otg)"
347 default ""
348 ---help---
349 Set the Vbus enable pin for usb0 (otg). This takes a string in the
350 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
351
Hans de Goede52defe82015-02-16 22:13:43 +0100352config USB0_VBUS_DET
353 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100354 default ""
355 ---help---
356 Set the Vbus detect pin for usb0 (otg). This takes a string in the
357 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
358
Hans de Goede48c06c92015-06-14 17:29:53 +0200359config USB0_ID_DET
360 string "ID detect pin for usb0 (otg)"
361 default ""
362 ---help---
363 Set the ID detect pin for usb0 (otg). This takes a string in the
364 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
365
Hans de Goede115200c2014-11-07 16:09:00 +0100366config USB1_VBUS_PIN
367 string "Vbus enable pin for usb1 (ehci0)"
368 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100369 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100370 ---help---
371 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
372 a string in the format understood by sunxi_name_to_gpio, e.g.
373 PH1 for pin 1 of port H.
374
375config USB2_VBUS_PIN
376 string "Vbus enable pin for usb2 (ehci1)"
377 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100378 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100379 ---help---
380 See USB1_VBUS_PIN help text.
381
Hans de Goede60fa6302016-03-18 08:42:01 +0100382config USB3_VBUS_PIN
383 string "Vbus enable pin for usb3 (ehci2)"
384 default ""
385 ---help---
386 See USB1_VBUS_PIN help text.
387
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200388config I2C0_ENABLE
389 bool "Enable I2C/TWI controller 0"
390 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
391 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200392 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200393 ---help---
394 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
395 its clock and setting up the bus. This is especially useful on devices
396 with slaves connected to the bus or with pins exposed through e.g. an
397 expansion port/header.
398
399config I2C1_ENABLE
400 bool "Enable I2C/TWI controller 1"
401 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200402 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200403 ---help---
404 See I2C0_ENABLE help text.
405
406config I2C2_ENABLE
407 bool "Enable I2C/TWI controller 2"
408 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200409 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200410 ---help---
411 See I2C0_ENABLE help text.
412
413if MACH_SUN6I || MACH_SUN7I
414config I2C3_ENABLE
415 bool "Enable I2C/TWI controller 3"
416 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200417 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200418 ---help---
419 See I2C0_ENABLE help text.
420endif
421
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100422if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100423config R_I2C_ENABLE
424 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100425 # This is used for the pmic on H3
426 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200427 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100428 ---help---
429 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100430endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100431
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200432if MACH_SUN7I
433config I2C4_ENABLE
434 bool "Enable I2C/TWI controller 4"
435 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200436 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200437 ---help---
438 See I2C0_ENABLE help text.
439endif
440
Hans de Goede2fcf0332015-04-25 17:25:14 +0200441config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900442 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200443 default n
444 ---help---
445 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
446
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200447config VIDEO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900448 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywarafa855d32016-09-05 01:32:40 +0100449 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200450 default y
451 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100452 Say Y here to add support for using a cfb console on the HDMI, LCD
453 or VGA output found on most sunxi devices. See doc/README.video for
454 info on how to select the video output and mode.
455
Hans de Goede2fbf0912014-12-23 23:04:35 +0100456config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900457 bool "HDMI output support"
Hans de Goede2fbf0912014-12-23 23:04:35 +0100458 depends on VIDEO && !MACH_SUN8I
459 default y
460 ---help---
461 Say Y here to add support for outputting video over HDMI.
462
Hans de Goeded9786d22014-12-25 13:58:06 +0100463config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900464 bool "VGA output support"
Hans de Goeded9786d22014-12-25 13:58:06 +0100465 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
466 default n
467 ---help---
468 Say Y here to add support for outputting video over VGA.
469
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100470config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900471 bool "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800472 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100473 default n
474 ---help---
475 Say Y here to add support for external DACs connected to the parallel
476 LCD interface driving a VGA connector, such as found on the
477 Olimex A13 boards.
478
Hans de Goedefb75d972015-01-25 15:33:07 +0100479config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900480 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100481 depends on VIDEO_VGA_VIA_LCD
482 default n
483 ---help---
484 Say Y here if you've a board which uses opendrain drivers for the vga
485 hsync and vsync signals. Opendrain drivers cannot generate steep enough
486 positive edges for a stable video output, so on boards with opendrain
487 drivers the sync signals must always be active high.
488
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800489config VIDEO_VGA_EXTERNAL_DAC_EN
490 string "LCD panel power enable pin"
491 depends on VIDEO_VGA_VIA_LCD
492 default ""
493 ---help---
494 Set the enable pin for the external VGA DAC. This takes a string in the
495 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
496
Hans de Goede39920c82015-08-03 19:20:26 +0200497config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900498 bool "Composite video output support"
Hans de Goede39920c82015-08-03 19:20:26 +0200499 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
500 default n
501 ---help---
502 Say Y here to add support for outputting composite video.
503
Hans de Goede2dae8002014-12-21 16:28:32 +0100504config VIDEO_LCD_MODE
505 string "LCD panel timing details"
506 depends on VIDEO
507 default ""
508 ---help---
509 LCD panel timing details string, leave empty if there is no LCD panel.
510 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
511 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200512 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100513
Hans de Goede65150322015-01-13 13:21:46 +0100514config VIDEO_LCD_DCLK_PHASE
515 int "LCD panel display clock phase"
516 depends on VIDEO
517 default 1
518 ---help---
519 Select LCD panel display clock phase shift, range 0-3.
520
Hans de Goede2dae8002014-12-21 16:28:32 +0100521config VIDEO_LCD_POWER
522 string "LCD panel power enable pin"
523 depends on VIDEO
524 default ""
525 ---help---
526 Set the power enable pin for the LCD panel. This takes a string in the
527 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
528
Hans de Goede242e3d82015-02-16 17:26:41 +0100529config VIDEO_LCD_RESET
530 string "LCD panel reset pin"
531 depends on VIDEO
532 default ""
533 ---help---
534 Set the reset pin for the LCD panel. This takes a string in the format
535 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
536
Hans de Goede2dae8002014-12-21 16:28:32 +0100537config VIDEO_LCD_BL_EN
538 string "LCD panel backlight enable pin"
539 depends on VIDEO
540 default ""
541 ---help---
542 Set the backlight enable pin for the LCD panel. This takes a string in the
543 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
544 port H.
545
546config VIDEO_LCD_BL_PWM
547 string "LCD panel backlight pwm pin"
548 depends on VIDEO
549 default ""
550 ---help---
551 Set the backlight pwm pin for the LCD panel. This takes a string in the
552 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200553
Hans de Goedea7403ae2015-01-22 21:02:42 +0100554config VIDEO_LCD_BL_PWM_ACTIVE_LOW
555 bool "LCD panel backlight pwm is inverted"
556 depends on VIDEO
557 default y
558 ---help---
559 Set this if the backlight pwm output is active low.
560
Hans de Goede55410082015-02-16 17:23:25 +0100561config VIDEO_LCD_PANEL_I2C
562 bool "LCD panel needs to be configured via i2c"
563 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100564 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200565 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100566 ---help---
567 Say y here if the LCD panel needs to be configured via i2c. This
568 will add a bitbang i2c controller using gpios to talk to the LCD.
569
570config VIDEO_LCD_PANEL_I2C_SDA
571 string "LCD panel i2c interface SDA pin"
572 depends on VIDEO_LCD_PANEL_I2C
573 default "PG12"
574 ---help---
575 Set the SDA pin for the LCD i2c interface. This takes a string in the
576 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
577
578config VIDEO_LCD_PANEL_I2C_SCL
579 string "LCD panel i2c interface SCL pin"
580 depends on VIDEO_LCD_PANEL_I2C
581 default "PG10"
582 ---help---
583 Set the SCL pin for the LCD i2c interface. This takes a string in the
584 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
585
Hans de Goede213480e2015-01-01 22:04:34 +0100586
587# Note only one of these may be selected at a time! But hidden choices are
588# not supported by Kconfig
589config VIDEO_LCD_IF_PARALLEL
590 bool
591
592config VIDEO_LCD_IF_LVDS
593 bool
594
595
596choice
597 prompt "LCD panel support"
598 depends on VIDEO
599 ---help---
600 Select which type of LCD panel to support.
601
602config VIDEO_LCD_PANEL_PARALLEL
603 bool "Generic parallel interface LCD panel"
604 select VIDEO_LCD_IF_PARALLEL
605
606config VIDEO_LCD_PANEL_LVDS
607 bool "Generic lvds interface LCD panel"
608 select VIDEO_LCD_IF_LVDS
609
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200610config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
611 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
612 select VIDEO_LCD_SSD2828
613 select VIDEO_LCD_IF_PARALLEL
614 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200615 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
616
617config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
618 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
619 select VIDEO_LCD_ANX9804
620 select VIDEO_LCD_IF_PARALLEL
621 select VIDEO_LCD_PANEL_I2C
622 ---help---
623 Select this for eDP LCD panels with 4 lanes running at 1.62G,
624 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200625
Hans de Goede27515b22015-01-20 09:23:36 +0100626config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
627 bool "Hitachi tx18d42vm LCD panel"
628 select VIDEO_LCD_HITACHI_TX18D42VM
629 select VIDEO_LCD_IF_LVDS
630 ---help---
631 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
632
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100633config VIDEO_LCD_TL059WV5C0
634 bool "tl059wv5c0 LCD panel"
635 select VIDEO_LCD_PANEL_I2C
636 select VIDEO_LCD_IF_PARALLEL
637 ---help---
638 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
639 Aigo M60/M608/M606 tablets.
640
Hans de Goede213480e2015-01-01 22:04:34 +0100641endchoice
642
643
Hans de Goedec13f60d2015-01-25 12:10:48 +0100644config GMAC_TX_DELAY
645 int "GMAC Transmit Clock Delay Chain"
646 default 0
647 ---help---
648 Set the GMAC Transmit Clock Delay Chain value.
649
Hans de Goedeff42d102015-09-13 13:02:48 +0200650config SPL_STACK_R_ADDR
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200651 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200652 default 0x2fe00000 if MACH_SUN9I
653
Masahiro Yamadadd840582014-07-30 14:08:14 +0900654endif