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Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Simon Glass53b5bf32016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glass77d2f7f2016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glass1646eba2016-09-12 23:18:42 -06009config SPL_LIBDISK_SUPPORT
10 default y
11
Simon Glasscc4288e2016-09-12 23:18:43 -060012config SPL_LIBGENERIC_SUPPORT
13 default y
14
Hans de Goede44d8ae52015-04-06 20:33:34 +020015# Note only one of these may be selected at a time! But hidden choices are
16# not supported by Kconfig
17config SUNXI_GEN_SUN4I
18 bool
19 ---help---
20 Select this for sunxi SoCs which have resets and clocks set up
21 as the original A10 (mach-sun4i).
22
23config SUNXI_GEN_SUN6I
24 bool
25 ---help---
26 Select this for sunxi SoCs which have sun6i like periphery, like
27 separate ahb reset control registers, custom pmic bus, new style
28 watchdog, etc.
29
30
Ian Campbell2c7e3b92014-10-24 21:20:44 +010031choice
32 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020033 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010034
Ian Campbellc3be2792014-10-24 21:20:45 +010035config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 bool "sun4i (Allwinner A10)"
37 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020038 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010039 select SUPPORT_SPL
40
Ian Campbellc3be2792014-10-24 21:20:45 +010041config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010042 bool "sun5i (Allwinner A13)"
43 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020044 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010045 select SUPPORT_SPL
46
Ian Campbellc3be2792014-10-24 21:20:45 +010047config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010048 bool "sun6i (Allwinner A31)"
49 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080050 select CPU_V7_HAS_NONSEC
51 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090052 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020054 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080055 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010056
Ian Campbellc3be2792014-10-24 21:20:45 +010057config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010058 bool "sun7i (Allwinner A20)"
59 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010060 select CPU_V7_HAS_NONSEC
61 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090062 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020063 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010064 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020065 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010066
Hans de Goede5e6bacd2015-04-06 20:55:39 +020067config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010068 bool "sun8i (Allwinner A23)"
69 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080070 select CPU_V7_HAS_NONSEC
71 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090072 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020073 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010074 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080075 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010076
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053077config MACH_SUN8I_A33
78 bool "sun8i (Allwinner A33)"
79 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080080 select CPU_V7_HAS_NONSEC
81 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090082 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053083 select SUNXI_GEN_SUN6I
84 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080085 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053086
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +080087config MACH_SUN8I_A83T
88 bool "sun8i (Allwinner A83T)"
89 select CPU_V7
90 select SUNXI_GEN_SUN6I
91 select SUPPORT_SPL
92
Jens Kuske1c27b7d2015-11-17 15:12:58 +010093config MACH_SUN8I_H3
94 bool "sun8i (Allwinner H3)"
95 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080096 select CPU_V7_HAS_NONSEC
97 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090098 select ARCH_SUPPORT_PSCI
Jens Kuske1c27b7d2015-11-17 15:12:58 +010099 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +0100100 select SUPPORT_SPL
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800101 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100102
Hans de Goede1871a8c2015-01-13 19:25:06 +0100103config MACH_SUN9I
104 bool "sun9i (Allwinner A80)"
105 select CPU_V7
106 select SUNXI_GEN_SUN6I
107
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800108config MACH_SUN50I
109 bool "sun50i (Allwinner A64)"
110 select ARM64
111 select SUNXI_GEN_SUN6I
112
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100113endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800114
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200115# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
116config MACH_SUN8I
117 bool
vishnupatekar762e24a2015-11-29 01:07:19 +0800118 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200119
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800120config DRAM_TYPE
121 int "sunxi dram type"
122 depends on MACH_SUN8I_A83T
123 default 3
124 ---help---
125 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200126
Hans de Goede37781a12014-11-15 19:46:39 +0100127config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100128 int "sunxi dram clock speed"
129 default 312 if MACH_SUN6I || MACH_SUN8I
130 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100131 ---help---
132 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +0100133 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +0100134
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200135if MACH_SUN5I || MACH_SUN7I
136config DRAM_MBUS_CLK
137 int "sunxi mbus clock speed"
138 default 300
139 ---help---
140 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
141
142endif
143
Hans de Goede37781a12014-11-15 19:46:39 +0100144config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100145 int "sunxi dram zq value"
146 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
147 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100148 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100149 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100150
Hans de Goede8975cdf2015-05-13 15:00:46 +0200151config DRAM_ODT_EN
152 bool "sunxi dram odt enable"
153 default n if !MACH_SUN8I_A23
154 default y if MACH_SUN8I_A23
155 ---help---
156 Select this to enable dram odt (on die termination).
157
Hans de Goede8ffc4872015-01-17 14:24:55 +0100158if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
159config DRAM_EMR1
160 int "sunxi dram emr1 value"
161 default 0 if MACH_SUN4I
162 default 4 if MACH_SUN5I || MACH_SUN7I
163 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100164 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200165
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200166config DRAM_TPR3
167 hex "sunxi dram tpr3 value"
168 default 0
169 ---help---
170 Set the dram controller tpr3 parameter. This parameter configures
171 the delay on the command lane and also phase shifts, which are
172 applied for sampling incoming read data. The default value 0
173 means that no phase/delay adjustments are necessary. Properly
174 configuring this parameter increases reliability at high DRAM
175 clock speeds.
176
177config DRAM_DQS_GATING_DELAY
178 hex "sunxi dram dqs_gating_delay value"
179 default 0
180 ---help---
181 Set the dram controller dqs_gating_delay parmeter. Each byte
182 encodes the DQS gating delay for each byte lane. The delay
183 granularity is 1/4 cycle. For example, the value 0x05060606
184 means that the delay is 5 quarter-cycles for one lane (1.25
185 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
186 The default value 0 means autodetection. The results of hardware
187 autodetection are not very reliable and depend on the chip
188 temperature (sometimes producing different results on cold start
189 and warm reboot). But the accuracy of hardware autodetection
190 is usually good enough, unless running at really high DRAM
191 clocks speeds (up to 600MHz). If unsure, keep as 0.
192
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200193choice
194 prompt "sunxi dram timings"
195 default DRAM_TIMINGS_VENDOR_MAGIC
196 ---help---
197 Select the timings of the DDR3 chips.
198
199config DRAM_TIMINGS_VENDOR_MAGIC
200 bool "Magic vendor timings from Android"
201 ---help---
202 The same DRAM timings as in the Allwinner boot0 bootloader.
203
204config DRAM_TIMINGS_DDR3_1066F_1333H
205 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
206 ---help---
207 Use the timings of the standard JEDEC DDR3-1066F speed bin for
208 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
209 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
210 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
211 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
212 that down binning to DDR3-1066F is supported (because DDR3-1066F
213 uses a bit faster timings than DDR3-1333H).
214
215config DRAM_TIMINGS_DDR3_800E_1066G_1333J
216 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
217 ---help---
218 Use the timings of the slowest possible JEDEC speed bin for the
219 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
220 DDR3-800E, DDR3-1066G or DDR3-1333J.
221
222endchoice
223
Hans de Goede37781a12014-11-15 19:46:39 +0100224endif
225
Hans de Goede8975cdf2015-05-13 15:00:46 +0200226if MACH_SUN8I_A23
227config DRAM_ODT_CORRECTION
228 int "sunxi dram odt correction value"
229 default 0
230 ---help---
231 Set the dram odt correction value (range -255 - 255). In allwinner
232 fex files, this option is found in bits 8-15 of the u32 odt_en variable
233 in the [dram] section. When bit 31 of the odt_en variable is set
234 then the correction is negative. Usually the value for this is 0.
235endif
236
Iain Patone71b4222015-03-28 10:26:38 +0000237config SYS_CLK_FREQ
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200238 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000239 default 912000000 if MACH_SUN7I
240 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
241
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800242config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100243 default "sun4i" if MACH_SUN4I
244 default "sun5i" if MACH_SUN5I
245 default "sun6i" if MACH_SUN6I
246 default "sun7i" if MACH_SUN7I
247 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100248 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200249 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200250
Masahiro Yamadadd840582014-07-30 14:08:14 +0900251config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900252 default "sunxi"
253
254config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900255 default "sunxi"
256
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200257config UART0_PORT_F
258 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200259 default n
260 ---help---
261 Repurpose the SD card slot for getting access to the UART0 serial
262 console. Primarily useful only for low level u-boot debugging on
263 tablets, where normal UART0 is difficult to access and requires
264 device disassembly and/or soldering. As the SD card can't be used
265 at the same time, the system can be only booted in the FEL mode.
266 Only enable this if you really know what you are doing.
267
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200268config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900269 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200270 default n
271 ---help---
272 Set this to enable various workarounds for old kernels, this results in
273 sub-optimal settings for newer kernels, only enable if needed.
274
Maxime Ripard44c79872015-10-15 22:04:07 +0200275config MMC
276 depends on !UART0_PORT_F
277 default y if ARCH_SUNXI
278
Hans de Goedecd821132014-10-02 20:29:26 +0200279config MMC0_CD_PIN
280 string "Card detect pin for mmc0"
Chen-Yu Tsaiacdab172016-05-02 10:28:08 +0800281 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200282 default ""
283 ---help---
284 Set the card detect pin for mmc0, leave empty to not use cd. This
285 takes a string in the format understood by sunxi_name_to_gpio, e.g.
286 PH1 for pin 1 of port H.
287
288config MMC1_CD_PIN
289 string "Card detect pin for mmc1"
290 default ""
291 ---help---
292 See MMC0_CD_PIN help text.
293
294config MMC2_CD_PIN
295 string "Card detect pin for mmc2"
296 default ""
297 ---help---
298 See MMC0_CD_PIN help text.
299
300config MMC3_CD_PIN
301 string "Card detect pin for mmc3"
302 default ""
303 ---help---
304 See MMC0_CD_PIN help text.
305
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100306config MMC1_PINS
307 string "Pins for mmc1"
308 default ""
309 ---help---
310 Set the pins used for mmc1, when applicable. This takes a string in the
311 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
312
313config MMC2_PINS
314 string "Pins for mmc2"
315 default ""
316 ---help---
317 See MMC1_PINS help text.
318
319config MMC3_PINS
320 string "Pins for mmc3"
321 default ""
322 ---help---
323 See MMC1_PINS help text.
324
Hans de Goede2ccfac02014-10-02 20:43:50 +0200325config MMC_SUNXI_SLOT_EXTRA
326 int "mmc extra slot number"
327 default -1
328 ---help---
329 sunxi builds always enable mmc0, some boards also have a second sdcard
330 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
331 support for this.
332
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200333config INITIAL_USB_SCAN_DELAY
334 int "delay initial usb scan by x ms to allow builtin devices to init"
335 default 0
336 ---help---
337 Some boards have on board usb devices which need longer than the
338 USB spec's 1 second to connect from board powerup. Set this config
339 option to a non 0 value to add an extra delay before the first usb
340 bus scan.
341
Hans de Goede4458b7a2015-01-07 15:26:06 +0100342config USB0_VBUS_PIN
343 string "Vbus enable pin for usb0 (otg)"
344 default ""
345 ---help---
346 Set the Vbus enable pin for usb0 (otg). This takes a string in the
347 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
348
Hans de Goede52defe82015-02-16 22:13:43 +0100349config USB0_VBUS_DET
350 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100351 default ""
352 ---help---
353 Set the Vbus detect pin for usb0 (otg). This takes a string in the
354 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
355
Hans de Goede48c06c92015-06-14 17:29:53 +0200356config USB0_ID_DET
357 string "ID detect pin for usb0 (otg)"
358 default ""
359 ---help---
360 Set the ID detect pin for usb0 (otg). This takes a string in the
361 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
362
Hans de Goede115200c2014-11-07 16:09:00 +0100363config USB1_VBUS_PIN
364 string "Vbus enable pin for usb1 (ehci0)"
365 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100366 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100367 ---help---
368 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
369 a string in the format understood by sunxi_name_to_gpio, e.g.
370 PH1 for pin 1 of port H.
371
372config USB2_VBUS_PIN
373 string "Vbus enable pin for usb2 (ehci1)"
374 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100375 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100376 ---help---
377 See USB1_VBUS_PIN help text.
378
Hans de Goede60fa6302016-03-18 08:42:01 +0100379config USB3_VBUS_PIN
380 string "Vbus enable pin for usb3 (ehci2)"
381 default ""
382 ---help---
383 See USB1_VBUS_PIN help text.
384
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200385config I2C0_ENABLE
386 bool "Enable I2C/TWI controller 0"
387 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
388 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200389 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200390 ---help---
391 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
392 its clock and setting up the bus. This is especially useful on devices
393 with slaves connected to the bus or with pins exposed through e.g. an
394 expansion port/header.
395
396config I2C1_ENABLE
397 bool "Enable I2C/TWI controller 1"
398 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200399 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200400 ---help---
401 See I2C0_ENABLE help text.
402
403config I2C2_ENABLE
404 bool "Enable I2C/TWI controller 2"
405 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200406 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200407 ---help---
408 See I2C0_ENABLE help text.
409
410if MACH_SUN6I || MACH_SUN7I
411config I2C3_ENABLE
412 bool "Enable I2C/TWI controller 3"
413 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200414 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200415 ---help---
416 See I2C0_ENABLE help text.
417endif
418
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100419if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100420config R_I2C_ENABLE
421 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100422 # This is used for the pmic on H3
423 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200424 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100425 ---help---
426 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100427endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100428
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200429if MACH_SUN7I
430config I2C4_ENABLE
431 bool "Enable I2C/TWI controller 4"
432 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200433 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200434 ---help---
435 See I2C0_ENABLE help text.
436endif
437
Hans de Goede2fcf0332015-04-25 17:25:14 +0200438config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900439 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200440 default n
441 ---help---
442 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
443
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200444config VIDEO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900445 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywarafa855d32016-09-05 01:32:40 +0100446 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200447 default y
448 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100449 Say Y here to add support for using a cfb console on the HDMI, LCD
450 or VGA output found on most sunxi devices. See doc/README.video for
451 info on how to select the video output and mode.
452
Hans de Goede2fbf0912014-12-23 23:04:35 +0100453config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900454 bool "HDMI output support"
Hans de Goede2fbf0912014-12-23 23:04:35 +0100455 depends on VIDEO && !MACH_SUN8I
456 default y
457 ---help---
458 Say Y here to add support for outputting video over HDMI.
459
Hans de Goeded9786d22014-12-25 13:58:06 +0100460config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900461 bool "VGA output support"
Hans de Goeded9786d22014-12-25 13:58:06 +0100462 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
463 default n
464 ---help---
465 Say Y here to add support for outputting video over VGA.
466
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100467config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900468 bool "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800469 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100470 default n
471 ---help---
472 Say Y here to add support for external DACs connected to the parallel
473 LCD interface driving a VGA connector, such as found on the
474 Olimex A13 boards.
475
Hans de Goedefb75d972015-01-25 15:33:07 +0100476config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900477 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100478 depends on VIDEO_VGA_VIA_LCD
479 default n
480 ---help---
481 Say Y here if you've a board which uses opendrain drivers for the vga
482 hsync and vsync signals. Opendrain drivers cannot generate steep enough
483 positive edges for a stable video output, so on boards with opendrain
484 drivers the sync signals must always be active high.
485
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800486config VIDEO_VGA_EXTERNAL_DAC_EN
487 string "LCD panel power enable pin"
488 depends on VIDEO_VGA_VIA_LCD
489 default ""
490 ---help---
491 Set the enable pin for the external VGA DAC. This takes a string in the
492 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
493
Hans de Goede39920c82015-08-03 19:20:26 +0200494config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900495 bool "Composite video output support"
Hans de Goede39920c82015-08-03 19:20:26 +0200496 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
497 default n
498 ---help---
499 Say Y here to add support for outputting composite video.
500
Hans de Goede2dae8002014-12-21 16:28:32 +0100501config VIDEO_LCD_MODE
502 string "LCD panel timing details"
503 depends on VIDEO
504 default ""
505 ---help---
506 LCD panel timing details string, leave empty if there is no LCD panel.
507 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
508 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200509 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100510
Hans de Goede65150322015-01-13 13:21:46 +0100511config VIDEO_LCD_DCLK_PHASE
512 int "LCD panel display clock phase"
513 depends on VIDEO
514 default 1
515 ---help---
516 Select LCD panel display clock phase shift, range 0-3.
517
Hans de Goede2dae8002014-12-21 16:28:32 +0100518config VIDEO_LCD_POWER
519 string "LCD panel power enable pin"
520 depends on VIDEO
521 default ""
522 ---help---
523 Set the power enable pin for the LCD panel. This takes a string in the
524 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
525
Hans de Goede242e3d82015-02-16 17:26:41 +0100526config VIDEO_LCD_RESET
527 string "LCD panel reset pin"
528 depends on VIDEO
529 default ""
530 ---help---
531 Set the reset pin for the LCD panel. This takes a string in the format
532 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
533
Hans de Goede2dae8002014-12-21 16:28:32 +0100534config VIDEO_LCD_BL_EN
535 string "LCD panel backlight enable pin"
536 depends on VIDEO
537 default ""
538 ---help---
539 Set the backlight enable pin for the LCD panel. This takes a string in the
540 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
541 port H.
542
543config VIDEO_LCD_BL_PWM
544 string "LCD panel backlight pwm pin"
545 depends on VIDEO
546 default ""
547 ---help---
548 Set the backlight pwm pin for the LCD panel. This takes a string in the
549 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200550
Hans de Goedea7403ae2015-01-22 21:02:42 +0100551config VIDEO_LCD_BL_PWM_ACTIVE_LOW
552 bool "LCD panel backlight pwm is inverted"
553 depends on VIDEO
554 default y
555 ---help---
556 Set this if the backlight pwm output is active low.
557
Hans de Goede55410082015-02-16 17:23:25 +0100558config VIDEO_LCD_PANEL_I2C
559 bool "LCD panel needs to be configured via i2c"
560 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100561 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200562 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100563 ---help---
564 Say y here if the LCD panel needs to be configured via i2c. This
565 will add a bitbang i2c controller using gpios to talk to the LCD.
566
567config VIDEO_LCD_PANEL_I2C_SDA
568 string "LCD panel i2c interface SDA pin"
569 depends on VIDEO_LCD_PANEL_I2C
570 default "PG12"
571 ---help---
572 Set the SDA pin for the LCD i2c interface. This takes a string in the
573 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
574
575config VIDEO_LCD_PANEL_I2C_SCL
576 string "LCD panel i2c interface SCL pin"
577 depends on VIDEO_LCD_PANEL_I2C
578 default "PG10"
579 ---help---
580 Set the SCL pin for the LCD i2c interface. This takes a string in the
581 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
582
Hans de Goede213480e2015-01-01 22:04:34 +0100583
584# Note only one of these may be selected at a time! But hidden choices are
585# not supported by Kconfig
586config VIDEO_LCD_IF_PARALLEL
587 bool
588
589config VIDEO_LCD_IF_LVDS
590 bool
591
592
593choice
594 prompt "LCD panel support"
595 depends on VIDEO
596 ---help---
597 Select which type of LCD panel to support.
598
599config VIDEO_LCD_PANEL_PARALLEL
600 bool "Generic parallel interface LCD panel"
601 select VIDEO_LCD_IF_PARALLEL
602
603config VIDEO_LCD_PANEL_LVDS
604 bool "Generic lvds interface LCD panel"
605 select VIDEO_LCD_IF_LVDS
606
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200607config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
608 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
609 select VIDEO_LCD_SSD2828
610 select VIDEO_LCD_IF_PARALLEL
611 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200612 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
613
614config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
615 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
616 select VIDEO_LCD_ANX9804
617 select VIDEO_LCD_IF_PARALLEL
618 select VIDEO_LCD_PANEL_I2C
619 ---help---
620 Select this for eDP LCD panels with 4 lanes running at 1.62G,
621 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200622
Hans de Goede27515b22015-01-20 09:23:36 +0100623config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
624 bool "Hitachi tx18d42vm LCD panel"
625 select VIDEO_LCD_HITACHI_TX18D42VM
626 select VIDEO_LCD_IF_LVDS
627 ---help---
628 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
629
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100630config VIDEO_LCD_TL059WV5C0
631 bool "tl059wv5c0 LCD panel"
632 select VIDEO_LCD_PANEL_I2C
633 select VIDEO_LCD_IF_PARALLEL
634 ---help---
635 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
636 Aigo M60/M608/M606 tablets.
637
Hans de Goede213480e2015-01-01 22:04:34 +0100638endchoice
639
640
Hans de Goedec13f60d2015-01-25 12:10:48 +0100641config GMAC_TX_DELAY
642 int "GMAC Transmit Clock Delay Chain"
643 default 0
644 ---help---
645 Set the GMAC Transmit Clock Delay Chain value.
646
Hans de Goedeff42d102015-09-13 13:02:48 +0200647config SPL_STACK_R_ADDR
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200648 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200649 default 0x2fe00000 if MACH_SUN9I
650
Masahiro Yamadadd840582014-07-30 14:08:14 +0900651endif