Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bc527c6dfad229d9645e848f3e0e82de9bf9e9c7 / . / arch / riscv / Kconfig
blob: 8cfc7d0faaac1a98a00ac9e1b364f4016a05afaf [file] [log] [blame]
Bin Meng117a4332018-09-26 06:55:06 -0700[diff] [blame]1menu "RISC-V architecture"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]2 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]11config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]13
Padmarao Begari39494822019-05-28 15:47:51 +0530[diff] [blame]14config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
16
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]17config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
19
Anup Patel3fda0262019-02-25 08:15:19 +0000[diff] [blame]20config TARGET_SIFIVE_FU540
21 bool "Support SiFive FU540 Board"
22
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]23endchoice
24
Trevor Woernera0aba8a2019-05-03 09:40:59 -0400[diff] [blame]25config SYS_ICACHE_OFF
26 bool "Do not enable icache"
27 default n
28 help
29 Do not enable instruction cache in U-Boot.
30
Trevor Woerner10015022019-05-03 09:41:00 -0400[diff] [blame]31config SPL_SYS_ICACHE_OFF
32 bool "Do not enable icache in SPL"
33 depends on SPL
34 default SYS_ICACHE_OFF
35 help
36 Do not enable instruction cache in SPL.
37
Trevor Woernera0aba8a2019-05-03 09:40:59 -0400[diff] [blame]38config SYS_DCACHE_OFF
39 bool "Do not enable dcache"
40 default n
41 help
42 Do not enable data cache in U-Boot.
43
Trevor Woerner10015022019-05-03 09:41:00 -0400[diff] [blame]44config SPL_SYS_DCACHE_OFF
45 bool "Do not enable dcache in SPL"
46 depends on SPL
47 default SYS_DCACHE_OFF
48 help
49 Do not enable data cache in SPL.
50
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]51# board-specific options below
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]52source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]53source "board/emulation/qemu-riscv/Kconfig"
Padmarao Begari39494822019-05-28 15:47:51 +0530[diff] [blame]54source "board/microchip/mpfs_icicle/Kconfig"
Anup Patel3fda0262019-02-25 08:15:19 +0000[diff] [blame]55source "board/sifive/fu540/Kconfig"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]56
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]57# platform-specific options below
58source "arch/riscv/cpu/ax25/Kconfig"
Anup Patelfdff1f92019-02-25 08:14:10 +0000[diff] [blame]59source "arch/riscv/cpu/generic/Kconfig"
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]60
61# architecture-specific options below
62
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]63choice
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]64 prompt "Base ISA"
65 default ARCH_RV32I
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]66
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]67config ARCH_RV32I
68 bool "RV32I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]69 select 32BIT
70 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]71 Choose this option to target the RV32I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]72
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]73config ARCH_RV64I
74 bool "RV64I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]75 select 64BIT
Lukas Auer71158562018-11-22 11:26:13 +0100[diff] [blame]76 select PHYS_64BIT
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]77 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]78 Choose this option to target the RV64I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]79
80endchoice
81
Lukas Auer8176ea42018-12-12 06:12:23 -0800[diff] [blame]82choice
83 prompt "Code Model"
84 default CMODEL_MEDLOW
85
86config CMODEL_MEDLOW
87 bool "medium low code model"
88 help
89 U-Boot and its statically defined symbols must lie within a single 2 GiB
90 address range and must lie between absolute addresses -2 GiB and +2 GiB.
91
92config CMODEL_MEDANY
93 bool "medium any code model"
94 help
95 U-Boot and its statically defined symbols must be within any single 2 GiB
96 address range.
97
98endchoice
99
Anup Patel3cfc8252018-12-12 06:12:29 -0800[diff] [blame]100choice
101 prompt "Run Mode"
102 default RISCV_MMODE
103
104config RISCV_MMODE
105 bool "Machine"
106 help
107 Choose this option to build U-Boot for RISC-V M-Mode.
108
109config RISCV_SMODE
110 bool "Supervisor"
111 help
112 Choose this option to build U-Boot for RISC-V S-Mode.
113
114endchoice
115
Lukas Auerd57ffa62018-11-22 11:26:14 +0100[diff] [blame]116config RISCV_ISA_C
117 bool "Emit compressed instructions"
118 default y
119 help
120 Adds "C" to the ISA subsets that the toolchain is allowed to emit
121 when building U-Boot, which results in compressed instructions in the
122 U-Boot binary.
123
124config RISCV_ISA_A
125 def_bool y
126
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]127config 32BIT
128 bool
129
130config 64BIT
131 bool
132
Bin Meng644a3cd2018-12-12 06:12:30 -0800[diff] [blame]133config SIFIVE_CLINT
134 bool
135 depends on RISCV_MMODE
136 select REGMAP
137 select SYSCON
138 help
139 The SiFive CLINT block holds memory-mapped control and status registers
140 associated with software and timer interrupts.
141
Rick Chen0d389462019-04-02 15:56:39 +0800[diff] [blame]142config ANDES_PLIC
143 bool
144 depends on RISCV_MMODE
145 select REGMAP
146 select SYSCON
147 help
148 The Andes PLIC block holds memory-mapped claim and pending registers
149 associated with software interrupt.
150
Rick Chena1f24872019-04-02 15:56:40 +0800[diff] [blame]151config ANDES_PLMT
152 bool
153 depends on RISCV_MMODE
154 select REGMAP
155 select SYSCON
156 help
157 The Andes PLMT block holds memory-mapped mtime register
158 associated with timer tick.
159
Anup Patel511107d2018-12-12 06:12:31 -0800[diff] [blame]160config RISCV_RDTIME
161 bool
162 default y if RISCV_SMODE
163 help
164 The provides the riscv_get_time() API that is implemented using the
165 standard rdtime instruction. This is the case for S-mode U-Boot, and
166 is useful for processors that support rdtime in M-mode too.
167
Bin Meng92b64fe2018-12-12 06:12:33 -0800[diff] [blame]168config SYS_MALLOC_F_LEN
169 default 0x1000
170
Lukas Auerfa33f082019-03-17 19:28:32 +0100[diff] [blame]171config SMP
172 bool "Symmetric Multi-Processing"
173 help
174 This enables support for systems with more than one CPU. If
175 you say N here, U-Boot will run on single and multiprocessor
176 machines, but will use only one CPU of a multiprocessor
177 machine. If you say Y here, U-Boot will run on many, but not
178 all, single processor machines.
179
180config NR_CPUS
181 int "Maximum number of CPUs (2-32)"
182 range 2 32
183 depends on SMP
184 default 8
185 help
186 On multiprocessor machines, U-Boot sets up a stack for each CPU.
187 Stack memory is pre-allocated. U-Boot must therefore know the
188 maximum number of CPUs that may be present.
189
Lukas Auerf152feb2019-03-17 19:28:34 +0100[diff] [blame]190config SBI_IPI
191 bool
192 default y if RISCV_SMODE
193 depends on SMP
194
Rick Chenbdce3892019-04-30 13:49:33 +0800[diff] [blame]195config XIP
196 bool "XIP mode"
197 help
198 XIP (eXecute In Place) is a method for executing code directly
199 from a NOR flash memory without copying the code to ram.
200 Say yes here if U-Boot boots from flash directly.
201
Lukas Auer3dea63c2019-03-17 19:28:37 +0100[diff] [blame]202config STACK_SIZE_SHIFT
203 int
204 default 13
205
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]206endmenu