blob: f368d52c5612f2216941ebec7f666c113e57af99 [file] [log] [blame]
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson38127742022-04-22 16:11:37 -040019 default MISC
Simon Glassaaba7032018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson38127742022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glassaaba7032018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Andersonc8ce7ba2022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chouca844dd2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár467f0c42022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnaa5eb9a2017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harvey8479b9e2022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
95 This driver currently supports the RK3399 only, but can easily be
96 extended (by porting the read function from the Linux kernel sources)
97 to support other recent Rockchip devices.
98
Finley Xiaoa907dc32019-09-25 17:57:49 +020099config ROCKCHIP_OTP
100 bool "Rockchip OTP Support"
101 depends on MISC
102 help
103 Enable (read-only) access for the one-time-programmable memory block
104 found in Rockchip SoCs: accesses can either be made using byte
105 addressing and a length or through child-nodes that are generated
106 based on the e-fuse map retrieved from the DTS.
107
Pragnesh Patel05307212020-05-29 11:33:21 +0530108config SIFIVE_OTP
109 bool "SiFive eMemory OTP driver"
110 depends on MISC
111 help
112 Enable support for reading and writing the eMemory OTP on the
113 SiFive SoCs.
114
Liviu Dudau0fabfeb2018-09-28 13:43:31 +0100115config VEXPRESS_CONFIG
116 bool "Enable support for Arm Versatile Express config bus"
117 depends on MISC
118 help
119 If you say Y here, you will get support for accessing the
120 configuration bus on the Arm Versatile Express boards via
121 a sysreg driver.
122
Simon Glass6fb9ac12015-02-13 12:20:47 -0700123config CMD_CROS_EC
124 bool "Enable crosec command"
125 depends on CROS_EC
126 help
127 Enable command-line access to the Chrome OS EC (Embedded
128 Controller). This provides the 'crosec' command which has
129 a number of sub-commands for performing EC tasks such as
130 updating its flash, accessing a small saved context area
131 and talking to the I2C bus behind the EC (if there is one).
132
133config CROS_EC
134 bool "Enable Chrome OS EC"
135 help
136 Enable access to the Chrome OS EC. This is a separate
137 microcontroller typically available on a SPI bus on Chromebooks. It
138 provides access to the keyboard, some internal storage and may
139 control access to the battery and main PMIC depending on the
140 device. You can use the 'crosec' command to access it.
141
Simon Glassaaba7032018-11-18 08:14:27 -0700142config SPL_CROS_EC
143 bool "Enable Chrome OS EC in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400144 depends on SPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700145 help
146 Enable access to the Chrome OS EC in SPL. This is a separate
147 microcontroller typically available on a SPI bus on Chromebooks. It
148 provides access to the keyboard, some internal storage and may
149 control access to the battery and main PMIC depending on the
150 device. You can use the 'crosec' command to access it.
151
152config TPL_CROS_EC
153 bool "Enable Chrome OS EC in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400154 depends on TPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700155 help
156 Enable access to the Chrome OS EC in TPL. This is a separate
157 microcontroller typically available on a SPI bus on Chromebooks. It
158 provides access to the keyboard, some internal storage and may
159 control access to the battery and main PMIC depending on the
160 device. You can use the 'crosec' command to access it.
161
Simon Glass747093d2022-04-30 00:56:53 -0600162config VPL_CROS_EC
163 bool "Enable Chrome OS EC in VPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400164 depends on VPL_MISC
Simon Glass747093d2022-04-30 00:56:53 -0600165 help
166 Enable access to the Chrome OS EC in VPL. This is a separate
167 microcontroller typically available on a SPI bus on Chromebooks. It
168 provides access to the keyboard, some internal storage and may
169 control access to the battery and main PMIC depending on the
170 device. You can use the 'crosec' command to access it.
171
Simon Glass6fb9ac12015-02-13 12:20:47 -0700172config CROS_EC_I2C
173 bool "Enable Chrome OS EC I2C driver"
174 depends on CROS_EC
175 help
176 Enable I2C access to the Chrome OS EC. This is used on older
177 ARM Chromebooks such as snow and spring before the standard bus
178 changed to SPI. The EC will accept commands across the I2C using
179 a special message protocol, and provide responses.
180
181config CROS_EC_LPC
182 bool "Enable Chrome OS EC LPC driver"
183 depends on CROS_EC
184 help
185 Enable I2C access to the Chrome OS EC. This is used on x86
186 Chromebooks such as link and falco. The keyboard is provided
187 through a legacy port interface, so on x86 machines the main
188 function of the EC is power and thermal management.
189
Simon Glassaaba7032018-11-18 08:14:27 -0700190config SPL_CROS_EC_LPC
191 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400192 depends on CROS_EC && SPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700193 help
194 Enable I2C access to the Chrome OS EC. This is used on x86
195 Chromebooks such as link and falco. The keyboard is provided
196 through a legacy port interface, so on x86 machines the main
197 function of the EC is power and thermal management.
198
199config TPL_CROS_EC_LPC
200 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400201 depends on CROS_EC && TPL_MISC
Simon Glassaaba7032018-11-18 08:14:27 -0700202 help
203 Enable I2C access to the Chrome OS EC. This is used on x86
204 Chromebooks such as link and falco. The keyboard is provided
205 through a legacy port interface, so on x86 machines the main
206 function of the EC is power and thermal management.
207
Simon Glass747093d2022-04-30 00:56:53 -0600208config VPL_CROS_EC_LPC
209 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400210 depends on CROS_EC && VPL_MISC
Simon Glass747093d2022-04-30 00:56:53 -0600211 help
212 Enable I2C access to the Chrome OS EC. This is used on x86
213 Chromebooks such as link and falco. The keyboard is provided
214 through a legacy port interface, so on x86 machines the main
215 function of the EC is power and thermal management.
216
Simon Glass47cb8c62015-03-26 09:29:40 -0600217config CROS_EC_SANDBOX
218 bool "Enable Chrome OS EC sandbox driver"
219 depends on CROS_EC && SANDBOX
220 help
221 Enable a sandbox emulation of the Chrome OS EC. This supports
222 keyboard (use the -l flag to enable the LCD), verified boot context,
223 EC flash read/write/erase support and a few other things. It is
224 enough to perform a Chrome OS verified boot on sandbox.
225
Simon Glassaaba7032018-11-18 08:14:27 -0700226config SPL_CROS_EC_SANDBOX
227 bool "Enable Chrome OS EC sandbox driver in SPL"
228 depends on SPL_CROS_EC && SANDBOX
229 help
230 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
231 keyboard (use the -l flag to enable the LCD), verified boot context,
232 EC flash read/write/erase support and a few other things. It is
233 enough to perform a Chrome OS verified boot on sandbox.
234
235config TPL_CROS_EC_SANDBOX
236 bool "Enable Chrome OS EC sandbox driver in TPL"
237 depends on TPL_CROS_EC && SANDBOX
238 help
239 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
240 keyboard (use the -l flag to enable the LCD), verified boot context,
241 EC flash read/write/erase support and a few other things. It is
242 enough to perform a Chrome OS verified boot on sandbox.
243
Simon Glass747093d2022-04-30 00:56:53 -0600244config VPL_CROS_EC_SANDBOX
245 bool "Enable Chrome OS EC sandbox driver in VPL"
246 depends on VPL_CROS_EC && SANDBOX
247 help
248 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
249 keyboard (use the -l flag to enable the LCD), verified boot context,
250 EC flash read/write/erase support and a few other things. It is
251 enough to perform a Chrome OS verified boot on sandbox.
252
Simon Glass6fb9ac12015-02-13 12:20:47 -0700253config CROS_EC_SPI
254 bool "Enable Chrome OS EC SPI driver"
255 depends on CROS_EC
256 help
257 Enable SPI access to the Chrome OS EC. This is used on newer
258 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
259 provides a faster and more robust interface than I2C but the bugs
260 are less interesting.
261
Simon Glass879704d2017-05-17 03:25:02 -0600262config DS4510
263 bool "Enable support for DS4510 CPU supervisor"
264 help
265 Enable support for the Maxim DS4510 CPU supervisor. It has an
266 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
267 and a configurable timer for the supervisor function. The device is
268 connected over I2C.
269
Peng Fanc12e0d92015-08-26 15:41:33 +0800270config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530271 bool "Enable FSL SEC_MON Driver"
272 help
273 Freescale Security Monitor block is responsible for monitoring
274 system states.
275 Security Monitor can be transitioned on any security failures,
276 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100277
Simon Glass79d66a62019-12-06 21:41:58 -0700278config IRQ
Wasim Khan182c5f12021-03-08 16:48:13 +0100279 bool "Interrupt controller"
Simon Glass79d66a62019-12-06 21:41:58 -0700280 help
Wasim Khan182c5f12021-03-08 16:48:13 +0100281 This enables support for interrupt controllers, including ITSS.
Simon Glass79d66a62019-12-06 21:41:58 -0700282 Some devices have extra features, such as Apollo Lake. The
283 device has its own uclass since there are several operations
284 involved.
285
Paul Burtonb5392c52018-12-16 19:25:19 -0300286config JZ4780_EFUSE
287 bool "Ingenic JZ4780 eFUSE support"
288 depends on ARCH_JZ47XX
289 help
290 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
291
Peng Fan3e020f02015-08-27 14:49:05 +0800292config MXC_OCOTP
293 bool "Enable MXC OCOTP Driver"
Peng Fan994ab732019-07-22 01:24:55 +0000294 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100295 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800296 help
297 If you say Y here, you will get support for the One Time
298 Programmable memory pages that are stored on the some
299 Freescale i.MX processors.
300
Michael Scott33e9a692021-09-25 19:49:28 +0300301config SPL_MXC_OCOTP
302 bool "Enable MXC OCOTP driver in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400303 depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott33e9a692021-09-25 19:49:28 +0300304 default y
305 help
306 If you say Y here, you will get support for the One Time
307 Programmable memory pages, that are stored on some
308 Freescale i.MX processors, in SPL.
309
Stefan Roese4cf9e462016-07-19 07:45:46 +0200310config NUVOTON_NCT6102D
311 bool "Enable Nuvoton NCT6102D Super I/O driver"
312 help
313 If you say Y here, you will get support for the Nuvoton
314 NCT6102D Super I/O driver. This can be used to enable or
315 disable the legacy UART, the watchdog or other devices
316 in the Nuvoton Super IO chips on X86 platforms.
317
Simon Glass5bee27a2019-12-06 21:41:55 -0700318config P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200319 bool "Intel Primary to Sideband Bridge"
Simon Glass5bee27a2019-12-06 21:41:55 -0700320 depends on X86 || SANDBOX
321 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200322 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass5bee27a2019-12-06 21:41:55 -0700323 abbreviated to P2SB. The P2SB is used to access various peripherals
324 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
325 space. The space is segmented into different channels and peripherals
326 are accessed by device-specific means within those channels. Devices
327 should be added in the device tree as subnodes of the P2SB. A
328 Peripheral Channel Register? (PCR) API is provided to access those
329 devices - see pcr_readl(), etc.
330
331config SPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200332 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400333 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass5bee27a2019-12-06 21:41:55 -0700334 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200335 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700336 through memory-mapped I/O in a large chunk of PCI space. The space is
337 segmented into different channels and peripherals are accessed by
338 device-specific means within those channels. Devices should be added
339 in the device tree as subnodes of the p2sb.
340
341config TPL_P2SB
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200342 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400343 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass5bee27a2019-12-06 21:41:55 -0700344 help
Wolfgang Wallnerd872e7d2020-07-01 13:37:23 +0200345 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass5bee27a2019-12-06 21:41:55 -0700346 through memory-mapped I/O in a large chunk of PCI space. The space is
347 segmented into different channels and peripherals are accessed by
348 device-specific means within those channels. Devices should be added
349 in the device tree as subnodes of the p2sb.
350
Simon Glass5fd6bad2016-01-21 19:43:31 -0700351config PWRSEQ
352 bool "Enable power-sequencing drivers"
353 depends on DM
354 help
355 Power-sequencing drivers provide support for controlling power for
356 devices. They are typically referenced by a phandle from another
357 device. When the device is started up, its power sequence can be
358 initiated.
359
360config SPL_PWRSEQ
361 bool "Enable power-sequencing drivers for SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400362 depends on SPL_MISC && PWRSEQ
Simon Glass5fd6bad2016-01-21 19:43:31 -0700363 help
364 Power-sequencing drivers provide support for controlling power for
365 devices. They are typically referenced by a phandle from another
366 device. When the device is started up, its power sequence can be
367 initiated.
368
Stefan Roese1cdd9412015-03-12 11:22:46 +0100369config PCA9551_LED
370 bool "Enable PCA9551 LED driver"
371 help
372 Enable driver for PCA9551 LED controller. This controller
373 is connected via I2C. So I2C needs to be enabled.
374
375config PCA9551_I2C_ADDR
376 hex "I2C address of PCA9551 LED controller"
377 depends on PCA9551_LED
378 default 0x60
379 help
380 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600381
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200382config STM32MP_FUSE
383 bool "Enable STM32MP fuse wrapper providing the fuse API"
384 depends on ARCH_STM32MP && MISC
385 default y if CMD_FUSE
386 help
387 If you say Y here, you will get support for the fuse API (OTP)
388 for STM32MP architecture.
389 This API is needed for CMD_FUSE.
390
Christophe Kerello4e280b92017-09-13 18:00:08 +0200391config STM32_RCC
392 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner71f63542020-05-06 08:02:42 -0400393 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200394 help
395 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
396 block) is responsible of the management of the clock and reset
397 generation.
398 This driver is similar to an MFD driver in the Linux kernel.
399
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600400config TEGRA_CAR
401 bool "Enable support for the Tegra CAR driver"
402 depends on TEGRA_NO_BPMP
403 help
404 The Tegra CAR (Clock and Reset Controller) is a HW module that
405 controls almost all clocks and resets in a Tegra SoC.
406
Stephen Warren73dd5c42016-08-08 09:41:34 -0600407config TEGRA186_BPMP
408 bool "Enable support for the Tegra186 BPMP driver"
409 depends on TEGRA186
410 help
411 The Tegra BPMP (Boot and Power Management Processor) is a separate
412 auxiliary CPU embedded into Tegra to perform power management work,
413 and controls related features such as clocks, resets, power domains,
414 PMIC I2C bus, etc. This driver provides the core low-level
415 communication path by which feature-specific drivers (such as clock)
416 can make requests to the BPMP. This driver is similar to an MFD
417 driver in the Linux kernel.
418
Simon Glass079ac592020-12-23 08:11:18 -0700419config TEST_DRV
420 bool "Enable support for test drivers"
421 default y if SANDBOX
422 help
423 This enables drivers and uclasses that provides a way of testing the
424 operations of memory allocation and driver/uclass methods in driver
425 model. This should only be enabled for testing as it is not useful for
426 anything else.
427
Adam Fordcc3fedb2018-08-06 14:26:50 -0500428config TWL4030_LED
429 bool "Enable TWL4030 LED controller"
430 help
431 Enable this to add support for the TWL4030 LED controller.
432
Stefan Roese85056932016-01-19 14:05:10 +0100433config WINBOND_W83627
434 bool "Enable Winbond Super I/O driver"
435 help
436 If you say Y here, you will get support for the Winbond
437 W83627 Super I/O driver. This can be used to enable the
438 legacy UART or other devices in the Winbond Super IO chips
439 on X86 platforms.
440
Miao Yanfcf5c042016-05-22 19:37:14 -0700441config QFW
442 bool
443 help
Asherah Connor5b0b43e2021-03-19 18:21:40 +1100444 Hidden option to enable QEMU fw_cfg interface and uclass. This will
445 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
446
447config QFW_PIO
448 bool
449 depends on QFW
450 help
451 Hidden option to enable PIO QEMU fw_cfg interface. This will be
452 selected by the appropriate QEMU board.
Miao Yanfcf5c042016-05-22 19:37:14 -0700453
Asherah Connor5830b572021-03-19 18:21:42 +1100454config QFW_MMIO
455 bool
456 depends on QFW
457 help
458 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
459 selected by the appropriate QEMU board.
460
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200461config I2C_EEPROM
462 bool "Enable driver for generic I2C-attached EEPROMs"
463 depends on MISC
464 help
465 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500466
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800467
468config SPL_I2C_EEPROM
469 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400470 depends on SPL_MISC
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800471 help
472 This option is an SPL-variant of the I2C_EEPROM option.
473 See the help of I2C_EEPROM for details.
474
Adam Forde3f24d42017-08-13 09:00:28 -0500475config SYS_I2C_EEPROM_ADDR
476 hex "Chip address of the EEPROM device"
Tom Rini88cd7d02021-08-17 17:59:45 -0400477 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500478 default 0
479
Tom Rini88cd7d02021-08-17 17:59:45 -0400480if I2C_EEPROM
Adam Forde3f24d42017-08-13 09:00:28 -0500481
482config SYS_I2C_EEPROM_ADDR_OVERFLOW
483 hex "EEPROM Address Overflow"
Tom Rini5fd4a7e2021-12-11 14:55:47 -0500484 default 0x0
Adam Forde3f24d42017-08-13 09:00:28 -0500485 help
486 EEPROM chips that implement "address overflow" are ones
487 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
488 address and the extra bits end up in the "chip address" bit
489 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
490 byte chips.
491
492endif
493
Mario Six86da8c12018-04-27 14:53:33 +0200494config GDSYS_RXAUI_CTRL
495 bool "Enable gdsys RXAUI control driver"
496 depends on MISC
497 help
498 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200499
500config GDSYS_IOEP
501 bool "Enable gdsys IOEP driver"
502 depends on MISC
503 help
504 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200505
506config MPC83XX_SERDES
507 bool "Enable MPC83xx serdes driver"
508 depends on MISC
509 help
510 Support for serdes found on MPC83xx SoCs.
511
Tien Fong Chee62030002018-07-06 16:28:03 +0800512config FS_LOADER
513 bool "Enable loader driver for file system"
514 help
515 This is file system generic loader which can be used to load
516 the file image from the storage into target such as memory.
517
518 The consumer driver would then use this loader to program whatever,
519 ie. the FPGA device.
520
Keerthyb071a072022-01-27 13:16:53 +0100521config SPL_FS_LOADER
522 bool "Enable loader driver for file system"
Tom Rini8a1ab5e2022-05-10 12:51:47 -0400523 depends on SPL
Keerthyb071a072022-01-27 13:16:53 +0100524 help
525 This is file system generic loader which can be used to load
526 the file image from the storage into target such as memory.
527
528 The consumer driver would then use this loader to program whatever,
529 ie. the FPGA device.
530
Mario Sixc0a2b082018-10-04 09:00:54 +0200531config GDSYS_SOC
532 bool "Enable gdsys SOC driver"
533 depends on MISC
534 help
535 Support for gdsys IHS SOC, a simple bus associated with each gdsys
536 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
537 register maps are contained within the FPGA's register map.
538
Mario Sixab88bd22018-10-04 09:00:55 +0200539config IHS_FPGA
540 bool "Enable IHS FPGA driver"
541 depends on MISC
542 help
543 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
544 gdsys devices, which supply the majority of the functionality offered
545 by the devices. This driver supports both CON and CPU variants of the
546 devices, depending on the device tree entry.
Tero Kristo344eb6d2020-02-14 11:18:15 +0200547config ESM_K3
548 bool "Enable K3 ESM driver"
549 depends on ARCH_K3
550 help
551 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Sixab88bd22018-10-04 09:00:55 +0200552
Eugen Hristevf8164952019-10-09 09:23:39 +0000553config MICROCHIP_FLEXCOM
554 bool "Enable Microchip Flexcom driver"
555 depends on MISC
556 help
557 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
558 an I2C controller and an USART.
559 Only one function can be used at a time and is chosen at boot time
560 according to the device tree.
561
Tero Kristo9d233b42019-10-24 15:00:46 +0530562config K3_AVS0
563 depends on ARCH_K3 && SPL_DM_REGULATOR
564 bool "AVS class 0 support for K3 devices"
565 help
566 K3 devices have the optimized voltage values for the main voltage
567 domains stored in efuse within the VTM IP. This driver reads the
568 optimized voltage from the efuse, so that it can be programmed
569 to the PMIC on board.
570
Tero Kristo3b36b382020-02-14 11:18:16 +0200571config ESM_PMIC
572 bool "Enable PMIC ESM driver"
573 depends on DM_PMIC
574 help
575 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
576 typically to reboot the board in error condition.
577
Tom Rini98ab8312021-12-11 14:55:49 -0500578config FSL_IFC
579 bool
580
Michael Walle42595eb2022-02-25 18:06:24 +0530581config SL28CPLD
582 bool "Enable Kontron sl28cpld multi-function driver"
583 depends on DM_I2C
584 help
585 Support for the Kontron sl28cpld management controller. This is
586 the base driver which provides common access methods for the
587 sub-drivers.
588
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900589endmenu